1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * ATI Mach64 Register Definitions 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 1997 Michael AK Tesch 61da177e4SLinus Torvalds * written with much help from Jon Howell 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven 91da177e4SLinus Torvalds */ 101da177e4SLinus Torvalds 111da177e4SLinus Torvalds /* 121da177e4SLinus Torvalds * most of the rest of this file comes from ATI sample code 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds #ifndef REGMACH64_H 151da177e4SLinus Torvalds #define REGMACH64_H 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds /* Accelerator CRTC */ 201da177e4SLinus Torvalds #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ 211da177e4SLinus Torvalds #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ 221da177e4SLinus Torvalds #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ 231da177e4SLinus Torvalds #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ 241da177e4SLinus Torvalds #define CRTC_H_SYNC_STRT 0x0004 251da177e4SLinus Torvalds #define CRTC2_H_SYNC_STRT 0x0004 261da177e4SLinus Torvalds #define CRTC_H_SYNC_DLY 0x0005 271da177e4SLinus Torvalds #define CRTC2_H_SYNC_DLY 0x0005 281da177e4SLinus Torvalds #define CRTC_H_SYNC_WID 0x0006 291da177e4SLinus Torvalds #define CRTC2_H_SYNC_WID 0x0006 301da177e4SLinus Torvalds #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ 311da177e4SLinus Torvalds #define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ 321da177e4SLinus Torvalds #define CRTC_V_TOTAL 0x0008 331da177e4SLinus Torvalds #define CRTC2_V_TOTAL 0x0008 341da177e4SLinus Torvalds #define CRTC_V_DISP 0x000A 351da177e4SLinus Torvalds #define CRTC2_V_DISP 0x000A 361da177e4SLinus Torvalds #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ 371da177e4SLinus Torvalds #define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ 381da177e4SLinus Torvalds #define CRTC_V_SYNC_STRT 0x000C 391da177e4SLinus Torvalds #define CRTC2_V_SYNC_STRT 0x000C 401da177e4SLinus Torvalds #define CRTC_V_SYNC_WID 0x000E 411da177e4SLinus Torvalds #define CRTC2_V_SYNC_WID 0x000E 421da177e4SLinus Torvalds #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ 431da177e4SLinus Torvalds #define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ 441da177e4SLinus Torvalds #define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */ 451da177e4SLinus Torvalds #define CRTC_OFFSET 0x0014 461da177e4SLinus Torvalds #define CRTC_PITCH 0x0016 471da177e4SLinus Torvalds #define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */ 481da177e4SLinus Torvalds #define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */ 491da177e4SLinus Torvalds #define CRTC_PIX_WIDTH 0x001D 501da177e4SLinus Torvalds #define CRTC_FIFO 0x001E 511da177e4SLinus Torvalds #define CRTC_EXT_DISP 0x001F 521da177e4SLinus Torvalds 531da177e4SLinus Torvalds /* Memory Buffer Control */ 541da177e4SLinus Torvalds #define DSP_CONFIG 0x0020 /* Dword offset 0_08 */ 551da177e4SLinus Torvalds #define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */ 561da177e4SLinus Torvalds #define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */ 571da177e4SLinus Torvalds #define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */ 581da177e4SLinus Torvalds #define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */ 591da177e4SLinus Torvalds #define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */ 601da177e4SLinus Torvalds #define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */ 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds /* Accelerator CRTC */ 631da177e4SLinus Torvalds #define CRT_TRAP 0x0038 /* Dword offset 0_0E */ 641da177e4SLinus Torvalds 651da177e4SLinus Torvalds #define I2C_CNTL_0 0x003C /* Dword offset 0_0F */ 661da177e4SLinus Torvalds 671da177e4SLinus Torvalds #define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */ 681da177e4SLinus Torvalds 691da177e4SLinus Torvalds /* Overscan */ 701da177e4SLinus Torvalds #define OVR_CLR 0x0040 /* Dword offset 0_10 */ 711da177e4SLinus Torvalds #define OVR2_CLR 0x0040 /* Dword offset 0_10 */ 721da177e4SLinus Torvalds #define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ 731da177e4SLinus Torvalds #define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ 741da177e4SLinus Torvalds #define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ 751da177e4SLinus Torvalds #define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ 761da177e4SLinus Torvalds 771da177e4SLinus Torvalds /* Memory Buffer Control */ 781da177e4SLinus Torvalds #define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */ 791da177e4SLinus Torvalds #define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */ 801da177e4SLinus Torvalds #define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */ 811da177e4SLinus Torvalds #define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */ 821da177e4SLinus Torvalds #define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */ 831da177e4SLinus Torvalds #define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */ 841da177e4SLinus Torvalds #define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */ 851da177e4SLinus Torvalds #define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */ 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds /* Accelerator CRTC */ 881da177e4SLinus Torvalds #define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */ 891da177e4SLinus Torvalds 901da177e4SLinus Torvalds /* Hardware Cursor */ 911da177e4SLinus Torvalds #define CUR_CLR0 0x0060 /* Dword offset 0_18 */ 921da177e4SLinus Torvalds #define CUR2_CLR0 0x0060 /* Dword offset 0_18 */ 931da177e4SLinus Torvalds #define CUR_CLR1 0x0064 /* Dword offset 0_19 */ 941da177e4SLinus Torvalds #define CUR2_CLR1 0x0064 /* Dword offset 0_19 */ 951da177e4SLinus Torvalds #define CUR_OFFSET 0x0068 /* Dword offset 0_1A */ 961da177e4SLinus Torvalds #define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */ 971da177e4SLinus Torvalds #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ 981da177e4SLinus Torvalds #define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ 991da177e4SLinus Torvalds #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ 1001da177e4SLinus Torvalds #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ 1011da177e4SLinus Torvalds 102fe86175bSRandy Dunlap #define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */ 1031da177e4SLinus Torvalds 1041da177e4SLinus Torvalds /* General I/O Control */ 1051da177e4SLinus Torvalds #define GP_IO 0x0078 /* Dword offset 0_1E */ 1061da177e4SLinus Torvalds 1071da177e4SLinus Torvalds /* Test and Debug */ 1081da177e4SLinus Torvalds #define HW_DEBUG 0x007C /* Dword offset 0_1F */ 1091da177e4SLinus Torvalds 1101da177e4SLinus Torvalds /* Scratch Pad and Test */ 1111da177e4SLinus Torvalds #define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */ 1121da177e4SLinus Torvalds #define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */ 1131da177e4SLinus Torvalds #define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */ 1141da177e4SLinus Torvalds #define SCRATCH_REG3 0x008C /* Dword offset 0_23 */ 1151da177e4SLinus Torvalds 1161da177e4SLinus Torvalds /* Clock Control */ 1171da177e4SLinus Torvalds #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ 1181da177e4SLinus Torvalds /* CLOCK_CNTL register constants CT LAYOUT */ 1191da177e4SLinus Torvalds #define CLOCK_SEL 0x0f 1201da177e4SLinus Torvalds #define CLOCK_SEL_INTERNAL 0x03 1211da177e4SLinus Torvalds #define CLOCK_SEL_EXTERNAL 0x0c 1221da177e4SLinus Torvalds #define CLOCK_DIV 0x30 1231da177e4SLinus Torvalds #define CLOCK_DIV1 0x00 1241da177e4SLinus Torvalds #define CLOCK_DIV2 0x10 1251da177e4SLinus Torvalds #define CLOCK_DIV4 0x20 1261da177e4SLinus Torvalds #define CLOCK_STROBE 0x40 1271da177e4SLinus Torvalds /* ? 0x80 */ 1281da177e4SLinus Torvalds /* CLOCK_CNTL register constants GX LAYOUT */ 1291da177e4SLinus Torvalds #define CLOCK_BIT 0x04 /* For ICS2595 */ 1301da177e4SLinus Torvalds #define CLOCK_PULSE 0x08 /* For ICS2595 */ 1311da177e4SLinus Torvalds /*#define CLOCK_STROBE 0x40 dito as CT */ 1321da177e4SLinus Torvalds #define CLOCK_DATA 0x80 1331da177e4SLinus Torvalds 1341da177e4SLinus Torvalds /* For internal PLL(CT) start */ 1351da177e4SLinus Torvalds #define CLOCK_CNTL_ADDR CLOCK_CNTL + 1 1361da177e4SLinus Torvalds #define PLL_WR_EN 0x02 1371da177e4SLinus Torvalds #define PLL_ADDR 0xfc 1381da177e4SLinus Torvalds #define CLOCK_CNTL_DATA CLOCK_CNTL + 2 1391da177e4SLinus Torvalds #define PLL_DATA 0xff 1401da177e4SLinus Torvalds /* For internal PLL(CT) end */ 1411da177e4SLinus Torvalds 1421da177e4SLinus Torvalds #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ 1431da177e4SLinus Torvalds 1441da177e4SLinus Torvalds /* Configuration */ 145fe86175bSRandy Dunlap #define CNFG_STAT1 0x0094 /* Dword offset 0_25 */ 146fe86175bSRandy Dunlap #define CNFG_STAT2 0x0098 /* Dword offset 0_26 */ 1471da177e4SLinus Torvalds 1481da177e4SLinus Torvalds /* Bus Control */ 1491da177e4SLinus Torvalds #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ 1501da177e4SLinus Torvalds 1511da177e4SLinus Torvalds #define LCD_INDEX 0x00A4 /* Dword offset 0_29 */ 1521da177e4SLinus Torvalds #define LCD_DATA 0x00A8 /* Dword offset 0_2A */ 1531da177e4SLinus Torvalds 1541da177e4SLinus Torvalds #define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */ 1551da177e4SLinus Torvalds 1561da177e4SLinus Torvalds /* Memory Control */ 1571da177e4SLinus Torvalds #define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */ 1581da177e4SLinus Torvalds #define MEM_CNTL 0x00B0 /* Dword offset 0_2C */ 1591da177e4SLinus Torvalds #define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */ 1601da177e4SLinus Torvalds #define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */ 1611da177e4SLinus Torvalds 1621da177e4SLinus Torvalds #define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */ 1631da177e4SLinus Torvalds 1641da177e4SLinus Torvalds #define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */ 1651da177e4SLinus Torvalds 1661da177e4SLinus Torvalds /* DAC Control */ 1671da177e4SLinus Torvalds #define DAC_REGS 0x00C0 /* Dword offset 0_30 */ 1681da177e4SLinus Torvalds #define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */ 1691da177e4SLinus Torvalds #define DAC_DATA 0x00C1 /* Dword offset 0_30 */ 1701da177e4SLinus Torvalds #define DAC_MASK 0x00C2 /* Dword offset 0_30 */ 1711da177e4SLinus Torvalds #define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */ 1721da177e4SLinus Torvalds #define DAC_CNTL 0x00C4 /* Dword offset 0_31 */ 1731da177e4SLinus Torvalds 1741da177e4SLinus Torvalds #define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */ 1751da177e4SLinus Torvalds 1761da177e4SLinus Torvalds #define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */ 1771da177e4SLinus Torvalds #define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */ 1781da177e4SLinus Torvalds 1791da177e4SLinus Torvalds /* Test and Debug */ 1801da177e4SLinus Torvalds #define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */ 1811da177e4SLinus Torvalds 1821da177e4SLinus Torvalds /* Custom Macros */ 1831da177e4SLinus Torvalds #define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */ 1841da177e4SLinus Torvalds 1851da177e4SLinus Torvalds #define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */ 1861da177e4SLinus Torvalds #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ 1871da177e4SLinus Torvalds 1881da177e4SLinus Torvalds /* Configuration */ 189fe86175bSRandy Dunlap #define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ 190fe86175bSRandy Dunlap #define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ 191fe86175bSRandy Dunlap #define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */ 1921da177e4SLinus Torvalds 1931da177e4SLinus Torvalds /* Test and Debug */ 1941da177e4SLinus Torvalds #define CRC_SIG 0x00E8 /* Dword offset 0_3A */ 1951da177e4SLinus Torvalds #define CRC2_SIG 0x00E8 /* Dword offset 0_3A */ 1961da177e4SLinus Torvalds 1971da177e4SLinus Torvalds 1981da177e4SLinus Torvalds /* GUI MEMORY MAPPED Registers */ 1991da177e4SLinus Torvalds 2001da177e4SLinus Torvalds /* Draw Engine Destination Trajectory */ 2011da177e4SLinus Torvalds #define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */ 2021da177e4SLinus Torvalds #define DST_X 0x0104 /* Dword offset 0_41 */ 2031da177e4SLinus Torvalds #define DST_Y 0x0108 /* Dword offset 0_42 */ 2041da177e4SLinus Torvalds #define DST_Y_X 0x010C /* Dword offset 0_43 */ 2051da177e4SLinus Torvalds #define DST_WIDTH 0x0110 /* Dword offset 0_44 */ 2061da177e4SLinus Torvalds #define DST_HEIGHT 0x0114 /* Dword offset 0_45 */ 2071da177e4SLinus Torvalds #define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */ 2081da177e4SLinus Torvalds #define DST_X_WIDTH 0x011C /* Dword offset 0_47 */ 2091da177e4SLinus Torvalds #define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */ 2101da177e4SLinus Torvalds #define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */ 2111da177e4SLinus Torvalds #define DST_BRES_INC 0x0128 /* Dword offset 0_4A */ 2121da177e4SLinus Torvalds #define DST_BRES_DEC 0x012C /* Dword offset 0_4B */ 2131da177e4SLinus Torvalds #define DST_CNTL 0x0130 /* Dword offset 0_4C */ 2141da177e4SLinus Torvalds #define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */ 2151da177e4SLinus Torvalds #define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */ 2161da177e4SLinus Torvalds #define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */ 2171da177e4SLinus Torvalds #define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */ 2181da177e4SLinus Torvalds #define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */ 2191da177e4SLinus Torvalds #define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */ 2201da177e4SLinus Torvalds #define Z_CNTL 0x014C /* Dword offset 0_53 */ 2211da177e4SLinus Torvalds #define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */ 2221da177e4SLinus Torvalds #define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */ 2231da177e4SLinus Torvalds #define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */ 2241da177e4SLinus Torvalds #define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */ 2251da177e4SLinus Torvalds #define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */ 2261da177e4SLinus Torvalds #define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */ 2271da177e4SLinus Torvalds #define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */ 2281da177e4SLinus Torvalds #define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */ 2291da177e4SLinus Torvalds #define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */ 2301da177e4SLinus Torvalds #define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */ 2311da177e4SLinus Torvalds #define SECONDARY_T_START 0x017C /* Dword offset 0_5F */ 2321da177e4SLinus Torvalds 2331da177e4SLinus Torvalds /* Draw Engine Source Trajectory */ 2341da177e4SLinus Torvalds #define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */ 2351da177e4SLinus Torvalds #define SRC_X 0x0184 /* Dword offset 0_61 */ 2361da177e4SLinus Torvalds #define SRC_Y 0x0188 /* Dword offset 0_62 */ 2371da177e4SLinus Torvalds #define SRC_Y_X 0x018C /* Dword offset 0_63 */ 2381da177e4SLinus Torvalds #define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */ 2391da177e4SLinus Torvalds #define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */ 2401da177e4SLinus Torvalds #define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */ 2411da177e4SLinus Torvalds #define SRC_X_START 0x019C /* Dword offset 0_67 */ 2421da177e4SLinus Torvalds #define SRC_Y_START 0x01A0 /* Dword offset 0_68 */ 2431da177e4SLinus Torvalds #define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */ 2441da177e4SLinus Torvalds #define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */ 2451da177e4SLinus Torvalds #define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */ 2461da177e4SLinus Torvalds #define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */ 2471da177e4SLinus Torvalds #define SRC_CNTL 0x01B4 /* Dword offset 0_6D */ 2481da177e4SLinus Torvalds 2491da177e4SLinus Torvalds #define SCALE_OFF 0x01C0 /* Dword offset 0_70 */ 2501da177e4SLinus Torvalds #define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */ 2511da177e4SLinus Torvalds 2521da177e4SLinus Torvalds #define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */ 2531da177e4SLinus Torvalds #define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */ 2541da177e4SLinus Torvalds #define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */ 2551da177e4SLinus Torvalds #define TEX_3_OFF 0x01CC /* Dword offset 0_73 */ 2561da177e4SLinus Torvalds #define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */ 2571da177e4SLinus Torvalds #define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */ 2581da177e4SLinus Torvalds #define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */ 2591da177e4SLinus Torvalds #define TEX_7_OFF 0x01DC /* Dword offset 0_77 */ 2601da177e4SLinus Torvalds 2611da177e4SLinus Torvalds #define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */ 2621da177e4SLinus Torvalds #define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */ 2631da177e4SLinus Torvalds 2641da177e4SLinus Torvalds #define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */ 2651da177e4SLinus Torvalds #define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */ 2661da177e4SLinus Torvalds #define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */ 2671da177e4SLinus Torvalds #define S_Y_INC 0x01EC /* Dword offset 0_7B */ 2681da177e4SLinus Torvalds 2691da177e4SLinus Torvalds #define SCALE_PITCH 0x01EC /* Dword offset 0_7B */ 2701da177e4SLinus Torvalds #define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */ 2711da177e4SLinus Torvalds 2721da177e4SLinus Torvalds #define RED_X_INC 0x01F0 /* Dword offset 0_7C */ 2731da177e4SLinus Torvalds #define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */ 2741da177e4SLinus Torvalds 2751da177e4SLinus Torvalds #define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */ 2761da177e4SLinus Torvalds #define SCALE_VACC 0x01F8 /* Dword offset 0_7E */ 2771da177e4SLinus Torvalds #define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */ 2781da177e4SLinus Torvalds 2791da177e4SLinus Torvalds /* Host Data */ 2801da177e4SLinus Torvalds #define HOST_DATA0 0x0200 /* Dword offset 0_80 */ 2811da177e4SLinus Torvalds #define HOST_DATA1 0x0204 /* Dword offset 0_81 */ 2821da177e4SLinus Torvalds #define HOST_DATA2 0x0208 /* Dword offset 0_82 */ 2831da177e4SLinus Torvalds #define HOST_DATA3 0x020C /* Dword offset 0_83 */ 2841da177e4SLinus Torvalds #define HOST_DATA4 0x0210 /* Dword offset 0_84 */ 2851da177e4SLinus Torvalds #define HOST_DATA5 0x0214 /* Dword offset 0_85 */ 2861da177e4SLinus Torvalds #define HOST_DATA6 0x0218 /* Dword offset 0_86 */ 2871da177e4SLinus Torvalds #define HOST_DATA7 0x021C /* Dword offset 0_87 */ 2881da177e4SLinus Torvalds #define HOST_DATA8 0x0220 /* Dword offset 0_88 */ 2891da177e4SLinus Torvalds #define HOST_DATA9 0x0224 /* Dword offset 0_89 */ 2901da177e4SLinus Torvalds #define HOST_DATAA 0x0228 /* Dword offset 0_8A */ 2911da177e4SLinus Torvalds #define HOST_DATAB 0x022C /* Dword offset 0_8B */ 2921da177e4SLinus Torvalds #define HOST_DATAC 0x0230 /* Dword offset 0_8C */ 2931da177e4SLinus Torvalds #define HOST_DATAD 0x0234 /* Dword offset 0_8D */ 2941da177e4SLinus Torvalds #define HOST_DATAE 0x0238 /* Dword offset 0_8E */ 2951da177e4SLinus Torvalds #define HOST_DATAF 0x023C /* Dword offset 0_8F */ 2961da177e4SLinus Torvalds #define HOST_CNTL 0x0240 /* Dword offset 0_90 */ 2971da177e4SLinus Torvalds 2981da177e4SLinus Torvalds /* GUI Bus Mastering */ 2991da177e4SLinus Torvalds #define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */ 3001da177e4SLinus Torvalds #define BM_ADDR 0x0248 /* Dword offset 0_92 */ 3011da177e4SLinus Torvalds #define BM_DATA 0x0248 /* Dword offset 0_92 */ 3021da177e4SLinus Torvalds #define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */ 3031da177e4SLinus Torvalds 3041da177e4SLinus Torvalds /* Pattern */ 3051da177e4SLinus Torvalds #define PAT_REG0 0x0280 /* Dword offset 0_A0 */ 3061da177e4SLinus Torvalds #define PAT_REG1 0x0284 /* Dword offset 0_A1 */ 3071da177e4SLinus Torvalds #define PAT_CNTL 0x0288 /* Dword offset 0_A2 */ 3081da177e4SLinus Torvalds 3091da177e4SLinus Torvalds /* Scissors */ 3101da177e4SLinus Torvalds #define SC_LEFT 0x02A0 /* Dword offset 0_A8 */ 3111da177e4SLinus Torvalds #define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */ 3121da177e4SLinus Torvalds #define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */ 3131da177e4SLinus Torvalds #define SC_TOP 0x02AC /* Dword offset 0_AB */ 3141da177e4SLinus Torvalds #define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */ 3151da177e4SLinus Torvalds #define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */ 3161da177e4SLinus Torvalds 3171da177e4SLinus Torvalds /* Data Path */ 3181da177e4SLinus Torvalds #define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */ 3191da177e4SLinus Torvalds #define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */ 3201da177e4SLinus Torvalds #define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */ 3211da177e4SLinus Torvalds #define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */ 3221da177e4SLinus Torvalds #define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */ 3231da177e4SLinus Torvalds #define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */ 3241da177e4SLinus Torvalds #define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */ 3251da177e4SLinus Torvalds #define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */ 3261da177e4SLinus Torvalds #define DP_MIX 0x02D4 /* Dword offset 0_B5 */ 3271da177e4SLinus Torvalds #define DP_SRC 0x02D8 /* Dword offset 0_B6 */ 3281da177e4SLinus Torvalds #define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */ 3291da177e4SLinus Torvalds #define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */ 3301da177e4SLinus Torvalds 3311da177e4SLinus Torvalds /* Draw Engine Destination Trajectory */ 3321da177e4SLinus Torvalds #define DST_X_Y 0x02E8 /* Dword offset 0_BA */ 3331da177e4SLinus Torvalds #define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */ 3341da177e4SLinus Torvalds 3351da177e4SLinus Torvalds /* Data Path */ 3361da177e4SLinus Torvalds #define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */ 3371da177e4SLinus Torvalds #define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */ 3381da177e4SLinus Torvalds #define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */ 3391da177e4SLinus Torvalds 3401da177e4SLinus Torvalds /* Color Compare */ 3411da177e4SLinus Torvalds #define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */ 3421da177e4SLinus Torvalds #define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */ 3431da177e4SLinus Torvalds #define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */ 3441da177e4SLinus Torvalds 3451da177e4SLinus Torvalds /* Command FIFO */ 3461da177e4SLinus Torvalds #define FIFO_STAT 0x0310 /* Dword offset 0_C4 */ 3471da177e4SLinus Torvalds 3481da177e4SLinus Torvalds #define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */ 3491da177e4SLinus Torvalds #define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */ 3501da177e4SLinus Torvalds 3511da177e4SLinus Torvalds /* Engine Control */ 3521da177e4SLinus Torvalds #define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */ 3531da177e4SLinus Torvalds 3541da177e4SLinus Torvalds /* Engine Status/FIFO */ 3551da177e4SLinus Torvalds #define GUI_STAT 0x0338 /* Dword offset 0_CE */ 3561da177e4SLinus Torvalds 3571da177e4SLinus Torvalds #define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */ 3581da177e4SLinus Torvalds #define STW_EXP 0x0344 /* Dword offset 0_D1 */ 3591da177e4SLinus Torvalds #define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */ 3601da177e4SLinus Torvalds #define S_X_INC 0x034C /* Dword offset 0_D3 */ 3611da177e4SLinus Torvalds #define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */ 3621da177e4SLinus Torvalds 3631da177e4SLinus Torvalds #define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */ 3641da177e4SLinus Torvalds 3651da177e4SLinus Torvalds #define S_START 0x0354 /* Dword offset 0_D5 */ 3661da177e4SLinus Torvalds #define W_X_INC 0x0358 /* Dword offset 0_D6 */ 3671da177e4SLinus Torvalds #define W_Y_INC 0x035C /* Dword offset 0_D7 */ 3681da177e4SLinus Torvalds #define W_START 0x0360 /* Dword offset 0_D8 */ 3691da177e4SLinus Torvalds #define T_X_INC 0x0364 /* Dword offset 0_D9 */ 3701da177e4SLinus Torvalds #define T_Y_INC 0x0368 /* Dword offset 0_DA */ 3711da177e4SLinus Torvalds 3721da177e4SLinus Torvalds #define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */ 3731da177e4SLinus Torvalds 3741da177e4SLinus Torvalds #define T_START 0x036C /* Dword offset 0_DB */ 3751da177e4SLinus Torvalds #define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */ 3761da177e4SLinus Torvalds #define TEX_CNTL 0x0374 /* Dword offset 0_DD */ 3771da177e4SLinus Torvalds #define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */ 3781da177e4SLinus Torvalds #define TEX_PALETTE 0x037C /* Dword offset 0_DF */ 3791da177e4SLinus Torvalds 3801da177e4SLinus Torvalds #define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */ 3811da177e4SLinus Torvalds #define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */ 3821da177e4SLinus Torvalds #define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */ 3831da177e4SLinus Torvalds #define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */ 3841da177e4SLinus Torvalds 3851da177e4SLinus Torvalds /* Draw Engine Destination Trajectory */ 3861da177e4SLinus Torvalds #define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */ 3871da177e4SLinus Torvalds 3881da177e4SLinus Torvalds #define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */ 3891da177e4SLinus Torvalds 3901da177e4SLinus Torvalds #define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */ 3911da177e4SLinus Torvalds #define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */ 3921da177e4SLinus Torvalds #define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */ 3931da177e4SLinus Torvalds 3941da177e4SLinus Torvalds #define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */ 3951da177e4SLinus Torvalds 3961da177e4SLinus Torvalds #define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */ 3971da177e4SLinus Torvalds #define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */ 3981da177e4SLinus Torvalds #define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */ 3991da177e4SLinus Torvalds #define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */ 4001da177e4SLinus Torvalds #define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */ 4011da177e4SLinus Torvalds #define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */ 4021da177e4SLinus Torvalds 4031da177e4SLinus Torvalds #define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ 4041da177e4SLinus Torvalds 4051da177e4SLinus Torvalds #define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ 4061da177e4SLinus Torvalds #define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */ 4071da177e4SLinus Torvalds #define RED_START 0x03C8 /* Dword offset 0_F2 */ 4081da177e4SLinus Torvalds 4091da177e4SLinus Torvalds #define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */ 4101da177e4SLinus Torvalds #define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ 4111da177e4SLinus Torvalds 4121da177e4SLinus Torvalds #define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ 4131da177e4SLinus Torvalds #define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */ 4141da177e4SLinus Torvalds 4151da177e4SLinus Torvalds #define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */ 4161da177e4SLinus Torvalds #define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */ 4171da177e4SLinus Torvalds 4181da177e4SLinus Torvalds #define GREEN_START 0x03D4 /* Dword offset 0_F5 */ 4191da177e4SLinus Torvalds #define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */ 4201da177e4SLinus Torvalds #define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */ 4211da177e4SLinus Torvalds #define BLUE_START 0x03E0 /* Dword offset 0_F8 */ 4221da177e4SLinus Torvalds #define Z_X_INC 0x03E4 /* Dword offset 0_F9 */ 4231da177e4SLinus Torvalds #define Z_Y_INC 0x03E8 /* Dword offset 0_FA */ 4241da177e4SLinus Torvalds #define Z_START 0x03EC /* Dword offset 0_FB */ 4251da177e4SLinus Torvalds #define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */ 4261da177e4SLinus Torvalds #define FOG_X_INC 0x03F0 /* Dword offset 0_FC */ 4271da177e4SLinus Torvalds #define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */ 4281da177e4SLinus Torvalds #define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */ 4291da177e4SLinus Torvalds #define ALPHA_START 0x03F8 /* Dword offset 0_FE */ 4301da177e4SLinus Torvalds #define FOG_START 0x03F8 /* Dword offset 0_FE */ 4311da177e4SLinus Torvalds 4321da177e4SLinus Torvalds #define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */ 4331da177e4SLinus Torvalds #define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */ 4341da177e4SLinus Torvalds #define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */ 4351da177e4SLinus Torvalds #define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */ 4361da177e4SLinus Torvalds #define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */ 4371da177e4SLinus Torvalds #define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */ 4381da177e4SLinus Torvalds #define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */ 4391da177e4SLinus Torvalds 4401da177e4SLinus Torvalds #define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */ 4411da177e4SLinus Torvalds #define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */ 4421da177e4SLinus Torvalds #define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */ 4431da177e4SLinus Torvalds #define SCALER_TEST 0x042C /* Dword offset 1_0B */ 4441da177e4SLinus Torvalds #define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */ 4451da177e4SLinus Torvalds #define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */ 4461da177e4SLinus Torvalds #define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */ 4471da177e4SLinus Torvalds 4481da177e4SLinus Torvalds #define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */ 4491da177e4SLinus Torvalds #define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */ 4501da177e4SLinus Torvalds #define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */ 4511da177e4SLinus Torvalds #define VBI_START_END 0x044C /* Dword offset 1_13 */ 4521da177e4SLinus Torvalds #define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */ 4531da177e4SLinus Torvalds #define TRIG_CNTL 0x0454 /* Dword offset 1_15 */ 4541da177e4SLinus Torvalds 4551da177e4SLinus Torvalds #define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */ 4561da177e4SLinus Torvalds #define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */ 4571da177e4SLinus Torvalds 4581da177e4SLinus Torvalds #define VAL_WIDTH 0x0460 /* Dword offset 1_18 */ 4591da177e4SLinus Torvalds #define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */ 4601da177e4SLinus Torvalds #define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */ 4611da177e4SLinus Torvalds 4621da177e4SLinus Torvalds /* GenLocking */ 4631da177e4SLinus Torvalds #define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */ 4641da177e4SLinus Torvalds #define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */ 4651da177e4SLinus Torvalds #define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */ 4661da177e4SLinus Torvalds #define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */ 4671da177e4SLinus Torvalds 4681da177e4SLinus Torvalds #define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */ 4691da177e4SLinus Torvalds #define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */ 4701da177e4SLinus Torvalds #define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */ 4711da177e4SLinus Torvalds 4721da177e4SLinus Torvalds /* GenLocking */ 4731da177e4SLinus Torvalds #define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */ 4741da177e4SLinus Torvalds #define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */ 4751da177e4SLinus Torvalds #define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */ 4761da177e4SLinus Torvalds #define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */ 4771da177e4SLinus Torvalds 4781da177e4SLinus Torvalds #define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */ 4791da177e4SLinus Torvalds #define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */ 4801da177e4SLinus Torvalds #define MPP_ADDR 0x04C8 /* Dword offset 1_32 */ 4811da177e4SLinus Torvalds #define MPP_DATA 0x04CC /* Dword offset 1_33 */ 4821da177e4SLinus Torvalds #define TVO_CNTL 0x0500 /* Dword offset 1_40 */ 4831da177e4SLinus Torvalds 4841da177e4SLinus Torvalds /* Test and Debug */ 4851da177e4SLinus Torvalds #define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */ 4861da177e4SLinus Torvalds 4871da177e4SLinus Torvalds /* AGP */ 4881da177e4SLinus Torvalds #define AGP_BASE 0x0548 /* Dword offset 1_52 */ 4891da177e4SLinus Torvalds #define AGP_CNTL 0x054C /* Dword offset 1_53 */ 4901da177e4SLinus Torvalds 4911da177e4SLinus Torvalds #define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */ 4921da177e4SLinus Torvalds #define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */ 4931da177e4SLinus Torvalds #define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */ 4941da177e4SLinus Torvalds #define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */ 4951da177e4SLinus Torvalds #define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */ 4961da177e4SLinus Torvalds #define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */ 4971da177e4SLinus Torvalds 4981da177e4SLinus Torvalds /* Command FIFO */ 4991da177e4SLinus Torvalds #define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */ 5001da177e4SLinus Torvalds #define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */ 5011da177e4SLinus Torvalds #define GUI_CNTL 0x0578 /* Dword offset 1_5E */ 5021da177e4SLinus Torvalds 5031da177e4SLinus Torvalds /* Bus Mastering */ 5041da177e4SLinus Torvalds #define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */ 5051da177e4SLinus Torvalds #define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */ 5061da177e4SLinus Torvalds #define BM_COMMAND 0x0588 /* Dword offset 1_62 */ 5071da177e4SLinus Torvalds #define BM_STATUS 0x058C /* Dword offset 1_63 */ 5081da177e4SLinus Torvalds #define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */ 5091da177e4SLinus Torvalds #define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */ 5101da177e4SLinus Torvalds 5111da177e4SLinus Torvalds #define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */ 5121da177e4SLinus Torvalds #define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */ 5131da177e4SLinus Torvalds #define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */ 5141da177e4SLinus Torvalds #define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */ 5151da177e4SLinus Torvalds 5161da177e4SLinus Torvalds /* Setup Engine */ 5171da177e4SLinus Torvalds #define VERTEX_1_S 0x0640 /* Dword offset 1_90 */ 5181da177e4SLinus Torvalds #define VERTEX_1_T 0x0644 /* Dword offset 1_91 */ 5191da177e4SLinus Torvalds #define VERTEX_1_W 0x0648 /* Dword offset 1_92 */ 5201da177e4SLinus Torvalds #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */ 5211da177e4SLinus Torvalds #define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */ 5221da177e4SLinus Torvalds #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */ 5231da177e4SLinus Torvalds #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */ 5241da177e4SLinus Torvalds #define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */ 5251da177e4SLinus Torvalds #define VERTEX_2_S 0x0660 /* Dword offset 1_98 */ 5261da177e4SLinus Torvalds #define VERTEX_2_T 0x0664 /* Dword offset 1_99 */ 5271da177e4SLinus Torvalds #define VERTEX_2_W 0x0668 /* Dword offset 1_9A */ 5281da177e4SLinus Torvalds #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */ 5291da177e4SLinus Torvalds #define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */ 5301da177e4SLinus Torvalds #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */ 5311da177e4SLinus Torvalds #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */ 5321da177e4SLinus Torvalds #define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */ 5331da177e4SLinus Torvalds #define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */ 5341da177e4SLinus Torvalds #define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */ 5351da177e4SLinus Torvalds #define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */ 5361da177e4SLinus Torvalds #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */ 5371da177e4SLinus Torvalds #define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */ 5381da177e4SLinus Torvalds #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */ 5391da177e4SLinus Torvalds #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */ 5401da177e4SLinus Torvalds #define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */ 5411da177e4SLinus Torvalds #define VERTEX_1_S 0x0640 /* Dword offset 1_AB */ 5421da177e4SLinus Torvalds #define VERTEX_1_T 0x0644 /* Dword offset 1_AC */ 5431da177e4SLinus Torvalds #define VERTEX_1_W 0x0648 /* Dword offset 1_AD */ 5441da177e4SLinus Torvalds #define VERTEX_2_S 0x0660 /* Dword offset 1_AE */ 5451da177e4SLinus Torvalds #define VERTEX_2_T 0x0664 /* Dword offset 1_AF */ 5461da177e4SLinus Torvalds #define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */ 5471da177e4SLinus Torvalds #define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */ 5481da177e4SLinus Torvalds #define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */ 5491da177e4SLinus Torvalds #define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */ 5501da177e4SLinus Torvalds #define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */ 5511da177e4SLinus Torvalds #define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */ 5521da177e4SLinus Torvalds #define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */ 5531da177e4SLinus Torvalds #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */ 5541da177e4SLinus Torvalds #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */ 5551da177e4SLinus Torvalds #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */ 5561da177e4SLinus Torvalds #define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */ 5571da177e4SLinus Torvalds #define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */ 5581da177e4SLinus Torvalds #define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */ 5591da177e4SLinus Torvalds #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */ 5601da177e4SLinus Torvalds #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */ 5611da177e4SLinus Torvalds #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */ 5621da177e4SLinus Torvalds #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */ 5631da177e4SLinus Torvalds #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */ 5641da177e4SLinus Torvalds #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */ 5651da177e4SLinus Torvalds #define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */ 5661da177e4SLinus Torvalds #define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */ 5671da177e4SLinus Torvalds #define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */ 5681da177e4SLinus Torvalds #define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */ 5691da177e4SLinus Torvalds #define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */ 5701da177e4SLinus Torvalds #define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */ 5711da177e4SLinus Torvalds #define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */ 5721da177e4SLinus Torvalds #define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */ 5731da177e4SLinus Torvalds 5741da177e4SLinus Torvalds 5751da177e4SLinus Torvalds #define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */ 5761da177e4SLinus Torvalds 5771da177e4SLinus Torvalds /* CRTC control values (mostly CRTC_GEN_CNTL) */ 5781da177e4SLinus Torvalds 5791da177e4SLinus Torvalds #define CRTC_H_SYNC_NEG 0x00200000 5801da177e4SLinus Torvalds #define CRTC_V_SYNC_NEG 0x00200000 5811da177e4SLinus Torvalds 5821da177e4SLinus Torvalds #define CRTC_DBL_SCAN_EN 0x00000001 5831da177e4SLinus Torvalds #define CRTC_INTERLACE_EN 0x00000002 5841da177e4SLinus Torvalds #define CRTC_HSYNC_DIS 0x00000004 5851da177e4SLinus Torvalds #define CRTC_VSYNC_DIS 0x00000008 5861da177e4SLinus Torvalds #define CRTC_CSYNC_EN 0x00000010 5871da177e4SLinus Torvalds #define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */ 5881da177e4SLinus Torvalds #define CRTC_DISPLAY_DIS 0x00000040 5891da177e4SLinus Torvalds #define CRTC_VGA_XOVERSCAN 0x00000080 5901da177e4SLinus Torvalds 5911da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_MASK 0x00000700 5921da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_4BPP 0x00000100 5931da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_8BPP 0x00000200 5941da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_15BPP 0x00000300 5951da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_16BPP 0x00000400 5961da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_24BPP 0x00000500 5971da177e4SLinus Torvalds #define CRTC_PIX_WIDTH_32BPP 0x00000600 5981da177e4SLinus Torvalds 5991da177e4SLinus Torvalds #define CRTC_BYTE_PIX_ORDER 0x00000800 6001da177e4SLinus Torvalds #define CRTC_PIX_ORDER_MSN_LSN 0x00000000 6011da177e4SLinus Torvalds #define CRTC_PIX_ORDER_LSN_MSN 0x00000800 6021da177e4SLinus Torvalds 6031da177e4SLinus Torvalds #define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ 6041da177e4SLinus Torvalds #define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ 6051da177e4SLinus Torvalds #define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ 6061da177e4SLinus Torvalds #define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ 6071da177e4SLinus Torvalds #define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ 6081da177e4SLinus Torvalds 6091da177e4SLinus Torvalds #define CRTC_FIFO_LWM 0x000f0000 6101da177e4SLinus Torvalds #define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */ 6111da177e4SLinus Torvalds #define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */ 6121da177e4SLinus Torvalds 6131da177e4SLinus Torvalds #define CRTC_VGA_128KAP_PAGING 0x00100000 6141da177e4SLinus Torvalds #define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */ 6151da177e4SLinus Torvalds #define CRTC2_EN 0x00200000 /* LTPro */ 6161da177e4SLinus Torvalds #define CRTC_LOCK_REGS 0x00400000 6171da177e4SLinus Torvalds #define CRTC_SYNC_TRISTATE 0x00800000 6181da177e4SLinus Torvalds 6191da177e4SLinus Torvalds #define CRTC_EXT_DISP_EN 0x01000000 6201da177e4SLinus Torvalds #define CRTC_EN 0x02000000 6211da177e4SLinus Torvalds #define CRTC_DISP_REQ_EN 0x04000000 6221da177e4SLinus Torvalds #define CRTC_VGA_LINEAR 0x08000000 6231da177e4SLinus Torvalds #define CRTC_VSYNC_FALL_EDGE 0x10000000 6241da177e4SLinus Torvalds #define CRTC_VGA_TEXT_132 0x20000000 6251da177e4SLinus Torvalds #define CRTC_CNT_EN 0x40000000 6261da177e4SLinus Torvalds #define CRTC_CUR_B_TEST 0x80000000 6271da177e4SLinus Torvalds 6281da177e4SLinus Torvalds #define CRTC_CRNT_VLINE 0x07f00000 6291da177e4SLinus Torvalds 6301da177e4SLinus Torvalds #define CRTC_PRESERVED_MASK 0x0001f000 6311da177e4SLinus Torvalds 6321da177e4SLinus Torvalds #define CRTC_VBLANK 0x00000001 6331da177e4SLinus Torvalds #define CRTC_VBLANK_INT_EN 0x00000002 6341da177e4SLinus Torvalds #define CRTC_VBLANK_INT 0x00000004 6351da177e4SLinus Torvalds #define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT 6361da177e4SLinus Torvalds #define CRTC_VLINE_INT_EN 0x00000008 6371da177e4SLinus Torvalds #define CRTC_VLINE_INT 0x00000010 6381da177e4SLinus Torvalds #define CRTC_VLINE_INT_AK CRTC_VLINE_INT 6391da177e4SLinus Torvalds #define CRTC_VLINE_SYNC 0x00000020 6401da177e4SLinus Torvalds #define CRTC_FRAME 0x00000040 6411da177e4SLinus Torvalds #define SNAPSHOT_INT_EN 0x00000080 6421da177e4SLinus Torvalds #define SNAPSHOT_INT 0x00000100 6431da177e4SLinus Torvalds #define SNAPSHOT_INT_AK SNAPSHOT_INT 6441da177e4SLinus Torvalds #define I2C_INT_EN 0x00000200 6451da177e4SLinus Torvalds #define I2C_INT 0x00000400 6461da177e4SLinus Torvalds #define I2C_INT_AK I2C_INT 6471da177e4SLinus Torvalds #define CRTC2_VBLANK 0x00000800 6481da177e4SLinus Torvalds #define CRTC2_VBLANK_INT_EN 0x00001000 6491da177e4SLinus Torvalds #define CRTC2_VBLANK_INT 0x00002000 6501da177e4SLinus Torvalds #define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT 6511da177e4SLinus Torvalds #define CRTC2_VLINE_INT_EN 0x00004000 6521da177e4SLinus Torvalds #define CRTC2_VLINE_INT 0x00008000 6531da177e4SLinus Torvalds #define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT 6541da177e4SLinus Torvalds #define CAPBUF0_INT_EN 0x00010000 6551da177e4SLinus Torvalds #define CAPBUF0_INT 0x00020000 6561da177e4SLinus Torvalds #define CAPBUF0_INT_AK CAPBUF0_INT 6571da177e4SLinus Torvalds #define CAPBUF1_INT_EN 0x00040000 6581da177e4SLinus Torvalds #define CAPBUF1_INT 0x00080000 6591da177e4SLinus Torvalds #define CAPBUF1_INT_AK CAPBUF1_INT 6601da177e4SLinus Torvalds #define OVERLAY_EOF_INT_EN 0x00100000 6611da177e4SLinus Torvalds #define OVERLAY_EOF_INT 0x00200000 6621da177e4SLinus Torvalds #define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT 6631da177e4SLinus Torvalds #define ONESHOT_CAP_INT_EN 0x00400000 6641da177e4SLinus Torvalds #define ONESHOT_CAP_INT 0x00800000 6651da177e4SLinus Torvalds #define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT 6661da177e4SLinus Torvalds #define BUSMASTER_EOL_INT_EN 0x01000000 6671da177e4SLinus Torvalds #define BUSMASTER_EOL_INT 0x02000000 6681da177e4SLinus Torvalds #define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT 6691da177e4SLinus Torvalds #define GP_INT_EN 0x04000000 6701da177e4SLinus Torvalds #define GP_INT 0x08000000 6711da177e4SLinus Torvalds #define GP_INT_AK GP_INT 6721da177e4SLinus Torvalds #define CRTC2_VLINE_SYNC 0x10000000 6731da177e4SLinus Torvalds #define SNAPSHOT2_INT_EN 0x20000000 6741da177e4SLinus Torvalds #define SNAPSHOT2_INT 0x40000000 6751da177e4SLinus Torvalds #define SNAPSHOT2_INT_AK SNAPSHOT2_INT 6761da177e4SLinus Torvalds #define VBLANK_BIT2_INT 0x80000000 6771da177e4SLinus Torvalds #define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT 6781da177e4SLinus Torvalds 6791da177e4SLinus Torvalds #define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \ 6801da177e4SLinus Torvalds CRTC_VLINE_INT_EN | \ 6811da177e4SLinus Torvalds SNAPSHOT_INT_EN | \ 6821da177e4SLinus Torvalds I2C_INT_EN | \ 6831da177e4SLinus Torvalds CRTC2_VBLANK_INT_EN | \ 6841da177e4SLinus Torvalds CRTC2_VLINE_INT_EN | \ 6851da177e4SLinus Torvalds CAPBUF0_INT_EN | \ 6861da177e4SLinus Torvalds CAPBUF1_INT_EN | \ 6871da177e4SLinus Torvalds OVERLAY_EOF_INT_EN | \ 6881da177e4SLinus Torvalds ONESHOT_CAP_INT_EN | \ 6891da177e4SLinus Torvalds BUSMASTER_EOL_INT_EN | \ 6901da177e4SLinus Torvalds GP_INT_EN | \ 6911da177e4SLinus Torvalds SNAPSHOT2_INT_EN) 6921da177e4SLinus Torvalds 6931da177e4SLinus Torvalds /* DAC control values */ 6941da177e4SLinus Torvalds 6951da177e4SLinus Torvalds #define DAC_EXT_SEL_RS2 0x01 6961da177e4SLinus Torvalds #define DAC_EXT_SEL_RS3 0x02 6971da177e4SLinus Torvalds #define DAC_8BIT_EN 0x00000100 6981da177e4SLinus Torvalds #define DAC_PIX_DLY_MASK 0x00000600 6991da177e4SLinus Torvalds #define DAC_PIX_DLY_0NS 0x00000000 7001da177e4SLinus Torvalds #define DAC_PIX_DLY_2NS 0x00000200 7011da177e4SLinus Torvalds #define DAC_PIX_DLY_4NS 0x00000400 7021da177e4SLinus Torvalds #define DAC_BLANK_ADJ_MASK 0x00001800 7031da177e4SLinus Torvalds #define DAC_BLANK_ADJ_0 0x00000000 7041da177e4SLinus Torvalds #define DAC_BLANK_ADJ_1 0x00000800 7051da177e4SLinus Torvalds #define DAC_BLANK_ADJ_2 0x00001000 7061da177e4SLinus Torvalds 7071da177e4SLinus Torvalds /* DAC control values (my source XL/XC Register reference) */ 7081da177e4SLinus Torvalds #define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */ 7091da177e4SLinus Torvalds #define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */ 7101da177e4SLinus Torvalds #define DAC_BLANKING 0x00000004 7111da177e4SLinus Torvalds #define DAC_CMP_DISABLE 0x00000008 7121da177e4SLinus Torvalds #define DAC1_CLK_SEL 0x00000010 7131da177e4SLinus Torvalds #define PALETTE_ACCESS_CNTL 0x00000020 7141da177e4SLinus Torvalds #define PALETTE2_SNOOP_EN 0x00000040 7151da177e4SLinus Torvalds #define DAC_CMP_OUTPUT 0x00000080 /* read only */ 7161da177e4SLinus Torvalds /* #define DAC_8BIT_EN is ok */ 7171da177e4SLinus Torvalds #define CRT_SENSE 0x00000800 /* read only */ 7181da177e4SLinus Torvalds #define CRT_DETECTION_ON 0x00001000 7191da177e4SLinus Torvalds #define DAC_VGA_ADR_EN 0x00002000 7201da177e4SLinus Torvalds #define DAC_FEA_CON_EN 0x00004000 7211da177e4SLinus Torvalds #define DAC_PDWN 0x00008000 7221da177e4SLinus Torvalds #define DAC_TYPE_MASK 0x00070000 /* read only */ 7231da177e4SLinus Torvalds 7241da177e4SLinus Torvalds 7251da177e4SLinus Torvalds 7261da177e4SLinus Torvalds /* Mix control values */ 7271da177e4SLinus Torvalds 7281da177e4SLinus Torvalds #define MIX_NOT_DST 0x0000 7291da177e4SLinus Torvalds #define MIX_0 0x0001 7301da177e4SLinus Torvalds #define MIX_1 0x0002 7311da177e4SLinus Torvalds #define MIX_DST 0x0003 7321da177e4SLinus Torvalds #define MIX_NOT_SRC 0x0004 7331da177e4SLinus Torvalds #define MIX_XOR 0x0005 7341da177e4SLinus Torvalds #define MIX_XNOR 0x0006 7351da177e4SLinus Torvalds #define MIX_SRC 0x0007 7361da177e4SLinus Torvalds #define MIX_NAND 0x0008 7371da177e4SLinus Torvalds #define MIX_NOT_SRC_OR_DST 0x0009 7381da177e4SLinus Torvalds #define MIX_SRC_OR_NOT_DST 0x000a 7391da177e4SLinus Torvalds #define MIX_OR 0x000b 7401da177e4SLinus Torvalds #define MIX_AND 0x000c 7411da177e4SLinus Torvalds #define MIX_SRC_AND_NOT_DST 0x000d 7421da177e4SLinus Torvalds #define MIX_NOT_SRC_AND_DST 0x000e 7431da177e4SLinus Torvalds #define MIX_NOR 0x000f 7441da177e4SLinus Torvalds 7451da177e4SLinus Torvalds /* Maximum engine dimensions */ 7461da177e4SLinus Torvalds #define ENGINE_MIN_X 0 7471da177e4SLinus Torvalds #define ENGINE_MIN_Y 0 7481da177e4SLinus Torvalds #define ENGINE_MAX_X 4095 7491da177e4SLinus Torvalds #define ENGINE_MAX_Y 16383 7501da177e4SLinus Torvalds 7511da177e4SLinus Torvalds /* Mach64 engine bit constants - these are typically ORed together */ 7521da177e4SLinus Torvalds 7531da177e4SLinus Torvalds /* BUS_CNTL register constants */ 7541da177e4SLinus Torvalds #define BUS_APER_REG_DIS 0x00000010 7551da177e4SLinus Torvalds #define BUS_FIFO_ERR_ACK 0x00200000 7561da177e4SLinus Torvalds #define BUS_HOST_ERR_ACK 0x00800000 7571da177e4SLinus Torvalds 7581da177e4SLinus Torvalds /* GEN_TEST_CNTL register constants */ 7591da177e4SLinus Torvalds #define GEN_OVR_OUTPUT_EN 0x20 7601da177e4SLinus Torvalds #define HWCURSOR_ENABLE 0x80 7611da177e4SLinus Torvalds #define GUI_ENGINE_ENABLE 0x100 7621da177e4SLinus Torvalds #define BLOCK_WRITE_ENABLE 0x200 7631da177e4SLinus Torvalds 7641da177e4SLinus Torvalds /* DSP_CONFIG register constants */ 7651da177e4SLinus Torvalds #define DSP_XCLKS_PER_QW 0x00003fff 7661da177e4SLinus Torvalds #define DSP_LOOP_LATENCY 0x000f0000 7671da177e4SLinus Torvalds #define DSP_PRECISION 0x00700000 7681da177e4SLinus Torvalds 7691da177e4SLinus Torvalds /* DSP_ON_OFF register constants */ 7701da177e4SLinus Torvalds #define DSP_OFF 0x000007ff 7711da177e4SLinus Torvalds #define DSP_ON 0x07ff0000 7721da177e4SLinus Torvalds #define VGA_DSP_OFF DSP_OFF 7731da177e4SLinus Torvalds #define VGA_DSP_ON DSP_ON 7741da177e4SLinus Torvalds #define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW 7751da177e4SLinus Torvalds 7761da177e4SLinus Torvalds /* PLL register indices and fields */ 7771da177e4SLinus Torvalds #define MPLL_CNTL 0x00 7781da177e4SLinus Torvalds #define PLL_PC_GAIN 0x07 7791da177e4SLinus Torvalds #define PLL_VC_GAIN 0x18 7801da177e4SLinus Torvalds #define PLL_DUTY_CYC 0xE0 7811da177e4SLinus Torvalds #define VPLL_CNTL 0x01 7821da177e4SLinus Torvalds #define PLL_REF_DIV 0x02 7831da177e4SLinus Torvalds #define PLL_GEN_CNTL 0x03 7841da177e4SLinus Torvalds #define PLL_OVERRIDE 0x01 /* PLL_SLEEP */ 7851da177e4SLinus Torvalds #define PLL_MCLK_RST 0x02 /* PLL_MRESET */ 7861da177e4SLinus Torvalds #define OSC_EN 0x04 7871da177e4SLinus Torvalds #define EXT_CLK_EN 0x08 7881da177e4SLinus Torvalds #define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */ 7891da177e4SLinus Torvalds #define MCLK_SRC_SEL 0x70 7901da177e4SLinus Torvalds #define EXT_CLK_CNTL 0x80 7911da177e4SLinus Torvalds #define DLL_PWDN 0x80 /* VT4 -> */ 7921da177e4SLinus Torvalds #define MCLK_FB_DIV 0x04 7931da177e4SLinus Torvalds #define PLL_VCLK_CNTL 0x05 7941da177e4SLinus Torvalds #define PLL_VCLK_SRC_SEL 0x03 7951da177e4SLinus Torvalds #define PLL_VCLK_RST 0x04 7961da177e4SLinus Torvalds #define PLL_VCLK_INVERT 0x08 7971da177e4SLinus Torvalds #define VCLK_POST_DIV 0x06 7981da177e4SLinus Torvalds #define VCLK0_POST 0x03 7991da177e4SLinus Torvalds #define VCLK1_POST 0x0C 8001da177e4SLinus Torvalds #define VCLK2_POST 0x30 8011da177e4SLinus Torvalds #define VCLK3_POST 0xC0 8021da177e4SLinus Torvalds #define VCLK0_FB_DIV 0x07 8031da177e4SLinus Torvalds #define VCLK1_FB_DIV 0x08 8041da177e4SLinus Torvalds #define VCLK2_FB_DIV 0x09 8051da177e4SLinus Torvalds #define VCLK3_FB_DIV 0x0A 8061da177e4SLinus Torvalds #define PLL_EXT_CNTL 0x0B 8071da177e4SLinus Torvalds #define PLL_XCLK_MCLK_RATIO 0x03 8081da177e4SLinus Torvalds #define PLL_XCLK_SRC_SEL 0x07 8091da177e4SLinus Torvalds #define PLL_MFB_TIMES_4_2B 0x08 8101da177e4SLinus Torvalds #define PLL_VCLK0_XDIV 0x10 8111da177e4SLinus Torvalds #define PLL_VCLK1_XDIV 0x20 8121da177e4SLinus Torvalds #define PLL_VCLK2_XDIV 0x40 8131da177e4SLinus Torvalds #define PLL_VCLK3_XDIV 0x80 8141da177e4SLinus Torvalds #define DLL_CNTL 0x0C 8151da177e4SLinus Torvalds #define DLL1_CNTL 0x0C 8161da177e4SLinus Torvalds #define VFC_CNTL 0x0D 8171da177e4SLinus Torvalds #define PLL_TEST_CNTL 0x0E 8181da177e4SLinus Torvalds #define PLL_TEST_COUNT 0x0F 8191da177e4SLinus Torvalds #define LVDS_CNTL0 0x10 8201da177e4SLinus Torvalds #define LVDS_CNTL1 0x11 8211da177e4SLinus Torvalds #define AGP1_CNTL 0x12 8221da177e4SLinus Torvalds #define AGP2_CNTL 0x13 8231da177e4SLinus Torvalds #define DLL2_CNTL 0x14 8241da177e4SLinus Torvalds #define SCLK_FB_DIV 0x15 8251da177e4SLinus Torvalds #define SPLL_CNTL1 0x16 8261da177e4SLinus Torvalds #define SPLL_CNTL2 0x17 8271da177e4SLinus Torvalds #define APLL_STRAPS 0x18 8281da177e4SLinus Torvalds #define EXT_VPLL_CNTL 0x19 8291da177e4SLinus Torvalds #define EXT_VPLL_EN 0x04 8301da177e4SLinus Torvalds #define EXT_VPLL_VGA_EN 0x08 8311da177e4SLinus Torvalds #define EXT_VPLL_INSYNC 0x10 8321da177e4SLinus Torvalds #define EXT_VPLL_REF_DIV 0x1A 8331da177e4SLinus Torvalds #define EXT_VPLL_FB_DIV 0x1B 8341da177e4SLinus Torvalds #define EXT_VPLL_MSB 0x1C 8351da177e4SLinus Torvalds #define HTOTAL_CNTL 0x1D 8361da177e4SLinus Torvalds #define BYTE_CLK_CNTL 0x1E 8371da177e4SLinus Torvalds #define TV_PLL_CNTL1 0x1F 8381da177e4SLinus Torvalds #define TV_PLL_CNTL2 0x20 8391da177e4SLinus Torvalds #define TV_PLL_CNTL 0x21 8401da177e4SLinus Torvalds #define EXT_TV_PLL 0x22 8411da177e4SLinus Torvalds #define V2PLL_CNTL 0x23 8421da177e4SLinus Torvalds #define PLL_V2CLK_CNTL 0x24 8431da177e4SLinus Torvalds #define EXT_V2PLL_REF_DIV 0x25 8441da177e4SLinus Torvalds #define EXT_V2PLL_FB_DIV 0x26 8451da177e4SLinus Torvalds #define EXT_V2PLL_MSB 0x27 8461da177e4SLinus Torvalds #define HTOTAL2_CNTL 0x28 8471da177e4SLinus Torvalds #define PLL_YCLK_CNTL 0x29 8481da177e4SLinus Torvalds #define PM_DYN_CLK_CNTL 0x2A 8491da177e4SLinus Torvalds 850fe86175bSRandy Dunlap /* CNFG_CNTL register constants */ 8511da177e4SLinus Torvalds #define APERTURE_4M_ENABLE 1 8521da177e4SLinus Torvalds #define APERTURE_8M_ENABLE 2 8531da177e4SLinus Torvalds #define VGA_APERTURE_ENABLE 4 8541da177e4SLinus Torvalds 855fe86175bSRandy Dunlap /* CNFG_STAT0 register constants (GX, CX) */ 8561da177e4SLinus Torvalds #define CFG_BUS_TYPE 0x00000007 8571da177e4SLinus Torvalds #define CFG_MEM_TYPE 0x00000038 8581da177e4SLinus Torvalds #define CFG_INIT_DAC_TYPE 0x00000e00 8591da177e4SLinus Torvalds 860fe86175bSRandy Dunlap /* CNFG_STAT0 register constants (CT, ET, VT) */ 8611da177e4SLinus Torvalds #define CFG_MEM_TYPE_xT 0x00000007 8621da177e4SLinus Torvalds 8631da177e4SLinus Torvalds #define ISA 0 8641da177e4SLinus Torvalds #define EISA 1 8651da177e4SLinus Torvalds #define LOCAL_BUS 6 8661da177e4SLinus Torvalds #define PCI 7 8671da177e4SLinus Torvalds 8681da177e4SLinus Torvalds /* Memory types for GX, CX */ 8691da177e4SLinus Torvalds #define DRAMx4 0 8701da177e4SLinus Torvalds #define VRAMx16 1 8711da177e4SLinus Torvalds #define VRAMx16ssr 2 8721da177e4SLinus Torvalds #define DRAMx16 3 8731da177e4SLinus Torvalds #define GraphicsDRAMx16 4 8741da177e4SLinus Torvalds #define EnhancedVRAMx16 5 8751da177e4SLinus Torvalds #define EnhancedVRAMx16ssr 6 8761da177e4SLinus Torvalds 8771da177e4SLinus Torvalds /* Memory types for CT, ET, VT, GT */ 8781da177e4SLinus Torvalds #define DRAM 1 8791da177e4SLinus Torvalds #define EDO 2 8801da177e4SLinus Torvalds #define PSEUDO_EDO 3 8811da177e4SLinus Torvalds #define SDRAM 4 8821da177e4SLinus Torvalds #define SGRAM 5 8831da177e4SLinus Torvalds #define WRAM 6 884159dde93SVille Syrjala #define SDRAM32 6 8851da177e4SLinus Torvalds 8861da177e4SLinus Torvalds #define DAC_INTERNAL 0x00 8871da177e4SLinus Torvalds #define DAC_IBMRGB514 0x01 8881da177e4SLinus Torvalds #define DAC_ATI68875 0x02 8891da177e4SLinus Torvalds #define DAC_TVP3026_A 0x72 8901da177e4SLinus Torvalds #define DAC_BT476 0x03 8911da177e4SLinus Torvalds #define DAC_BT481 0x04 8921da177e4SLinus Torvalds #define DAC_ATT20C491 0x14 8931da177e4SLinus Torvalds #define DAC_SC15026 0x24 8941da177e4SLinus Torvalds #define DAC_MU9C1880 0x34 8951da177e4SLinus Torvalds #define DAC_IMSG174 0x44 8961da177e4SLinus Torvalds #define DAC_ATI68860_B 0x05 8971da177e4SLinus Torvalds #define DAC_ATI68860_C 0x15 8981da177e4SLinus Torvalds #define DAC_TVP3026_B 0x75 8991da177e4SLinus Torvalds #define DAC_STG1700 0x06 9001da177e4SLinus Torvalds #define DAC_ATT498 0x16 9011da177e4SLinus Torvalds #define DAC_STG1702 0x07 9021da177e4SLinus Torvalds #define DAC_SC15021 0x17 9031da177e4SLinus Torvalds #define DAC_ATT21C498 0x27 9041da177e4SLinus Torvalds #define DAC_STG1703 0x37 9051da177e4SLinus Torvalds #define DAC_CH8398 0x47 9061da177e4SLinus Torvalds #define DAC_ATT20C408 0x57 9071da177e4SLinus Torvalds 9081da177e4SLinus Torvalds #define CLK_ATI18818_0 0 9091da177e4SLinus Torvalds #define CLK_ATI18818_1 1 9101da177e4SLinus Torvalds #define CLK_STG1703 2 9111da177e4SLinus Torvalds #define CLK_CH8398 3 9121da177e4SLinus Torvalds #define CLK_INTERNAL 4 9131da177e4SLinus Torvalds #define CLK_ATT20C408 5 9141da177e4SLinus Torvalds #define CLK_IBMRGB514 6 9151da177e4SLinus Torvalds 9161da177e4SLinus Torvalds /* MEM_CNTL register constants */ 9171da177e4SLinus Torvalds #define MEM_SIZE_ALIAS 0x00000007 9181da177e4SLinus Torvalds #define MEM_SIZE_512K 0x00000000 9191da177e4SLinus Torvalds #define MEM_SIZE_1M 0x00000001 9201da177e4SLinus Torvalds #define MEM_SIZE_2M 0x00000002 9211da177e4SLinus Torvalds #define MEM_SIZE_4M 0x00000003 9221da177e4SLinus Torvalds #define MEM_SIZE_6M 0x00000004 9231da177e4SLinus Torvalds #define MEM_SIZE_8M 0x00000005 9241da177e4SLinus Torvalds #define MEM_SIZE_ALIAS_GTB 0x0000000F 9251da177e4SLinus Torvalds #define MEM_SIZE_2M_GTB 0x00000003 9261da177e4SLinus Torvalds #define MEM_SIZE_4M_GTB 0x00000007 9271da177e4SLinus Torvalds #define MEM_SIZE_6M_GTB 0x00000009 9281da177e4SLinus Torvalds #define MEM_SIZE_8M_GTB 0x0000000B 9291da177e4SLinus Torvalds #define MEM_BNDRY 0x00030000 9301da177e4SLinus Torvalds #define MEM_BNDRY_0K 0x00000000 9311da177e4SLinus Torvalds #define MEM_BNDRY_256K 0x00010000 9321da177e4SLinus Torvalds #define MEM_BNDRY_512K 0x00020000 9331da177e4SLinus Torvalds #define MEM_BNDRY_1M 0x00030000 9341da177e4SLinus Torvalds #define MEM_BNDRY_EN 0x00040000 9351da177e4SLinus Torvalds 9361da177e4SLinus Torvalds #define ONE_MB 0x100000 9371da177e4SLinus Torvalds /* ATI PCI constants */ 9381da177e4SLinus Torvalds #define PCI_ATI_VENDOR_ID 0x1002 9391da177e4SLinus Torvalds 9401da177e4SLinus Torvalds 941fe86175bSRandy Dunlap /* CNFG_CHIP_ID register constants */ 9421da177e4SLinus Torvalds #define CFG_CHIP_TYPE 0x0000FFFF 9431da177e4SLinus Torvalds #define CFG_CHIP_CLASS 0x00FF0000 9441da177e4SLinus Torvalds #define CFG_CHIP_REV 0xFF000000 9451da177e4SLinus Torvalds #define CFG_CHIP_MAJOR 0x07000000 9461da177e4SLinus Torvalds #define CFG_CHIP_FND_ID 0x38000000 9471da177e4SLinus Torvalds #define CFG_CHIP_MINOR 0xC0000000 9481da177e4SLinus Torvalds 9491da177e4SLinus Torvalds 950fe86175bSRandy Dunlap /* Chip IDs read from CNFG_CHIP_ID */ 9511da177e4SLinus Torvalds 9521da177e4SLinus Torvalds /* mach64GX family */ 9531da177e4SLinus Torvalds #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ 9541da177e4SLinus Torvalds #define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */ 9551da177e4SLinus Torvalds 9561da177e4SLinus Torvalds #define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */ 9571da177e4SLinus Torvalds #define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */ 9581da177e4SLinus Torvalds 9591da177e4SLinus Torvalds /* mach64CT family */ 9601da177e4SLinus Torvalds #define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */ 9611da177e4SLinus Torvalds #define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */ 9621da177e4SLinus Torvalds 9631da177e4SLinus Torvalds /* mach64CT family / mach64VT class */ 9641da177e4SLinus Torvalds #define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */ 9651da177e4SLinus Torvalds #define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */ 9661da177e4SLinus Torvalds #define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */ 9671da177e4SLinus Torvalds 9681da177e4SLinus Torvalds /* mach64CT family / mach64GT (3D RAGE) class */ 9691da177e4SLinus Torvalds #define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */ 9701da177e4SLinus Torvalds #define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */ 9711da177e4SLinus Torvalds #define LG_CHIP_ID 0x4c47 /* RAGE LT */ 9721da177e4SLinus Torvalds #define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */ 9731da177e4SLinus Torvalds #define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */ 9741da177e4SLinus Torvalds #define LT_CHIP_ID 0x4c54 /* RAGE LT */ 9751da177e4SLinus Torvalds 9761da177e4SLinus Torvalds /* mach64CT family / (Rage XL) class */ 9771da177e4SLinus Torvalds #define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */ 9781da177e4SLinus Torvalds #define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */ 9791da177e4SLinus Torvalds #define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */ 9801da177e4SLinus Torvalds #define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */ 9811da177e4SLinus Torvalds #define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */ 9821da177e4SLinus Torvalds #define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */ 9831da177e4SLinus Torvalds 9841da177e4SLinus Torvalds #define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \ 9851da177e4SLinus Torvalds (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ 9861da177e4SLinus Torvalds (id)==GO_CHIP_ID || (id)==GL_CHIP_ID) 9871da177e4SLinus Torvalds 9881da177e4SLinus Torvalds #define GT_CHIP_ID 0x4754 /* RAGE (GT) */ 9891da177e4SLinus Torvalds #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ 9901da177e4SLinus Torvalds #define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */ 9911da177e4SLinus Torvalds #define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */ 9921da177e4SLinus Torvalds #define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */ 9931da177e4SLinus Torvalds #define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */ 9941da177e4SLinus Torvalds #define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */ 9951da177e4SLinus Torvalds #define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */ 9961da177e4SLinus Torvalds #define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */ 9971da177e4SLinus Torvalds #define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */ 9981da177e4SLinus Torvalds 9991da177e4SLinus Torvalds #define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */ 10001da177e4SLinus Torvalds #define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */ 10011da177e4SLinus Torvalds #define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */ 10021da177e4SLinus Torvalds #define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */ 10031da177e4SLinus Torvalds 10041da177e4SLinus Torvalds #define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \ 10051da177e4SLinus Torvalds (id)==LR_CHIP_ID || (id)==LS_CHIP_ID) 10061da177e4SLinus Torvalds /* Mach64 major ASIC revisions */ 10071da177e4SLinus Torvalds #define MACH64_ASIC_NEC_VT_A3 0x08 10081da177e4SLinus Torvalds #define MACH64_ASIC_NEC_VT_A4 0x48 10091da177e4SLinus Torvalds #define MACH64_ASIC_SGS_VT_A4 0x40 10101da177e4SLinus Torvalds #define MACH64_ASIC_SGS_VT_B1S1 0x01 10111da177e4SLinus Torvalds #define MACH64_ASIC_SGS_GT_B1S1 0x01 10121da177e4SLinus Torvalds #define MACH64_ASIC_SGS_GT_B1S2 0x41 10131da177e4SLinus Torvalds #define MACH64_ASIC_UMC_GT_B2U1 0x1a 10141da177e4SLinus Torvalds #define MACH64_ASIC_UMC_GT_B2U2 0x5a 10151da177e4SLinus Torvalds #define MACH64_ASIC_UMC_VT_B2U3 0x9a 10161da177e4SLinus Torvalds #define MACH64_ASIC_UMC_GT_B2U3 0x9a 10171da177e4SLinus Torvalds #define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b 10181da177e4SLinus Torvalds #define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b 10191da177e4SLinus Torvalds #define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c 10201da177e4SLinus Torvalds #define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c 10211da177e4SLinus Torvalds 10221da177e4SLinus Torvalds /* Mach64 foundries */ 10231da177e4SLinus Torvalds #define MACH64_FND_SGS 0 10241da177e4SLinus Torvalds #define MACH64_FND_NEC 1 10251da177e4SLinus Torvalds #define MACH64_FND_UMC 3 10261da177e4SLinus Torvalds 10271da177e4SLinus Torvalds /* Mach64 chip types */ 10281da177e4SLinus Torvalds #define MACH64_UNKNOWN 0 10291da177e4SLinus Torvalds #define MACH64_GX 1 10301da177e4SLinus Torvalds #define MACH64_CX 2 10311da177e4SLinus Torvalds #define MACH64_CT 3Restore 10321da177e4SLinus Torvalds #define MACH64_ET 4 10331da177e4SLinus Torvalds #define MACH64_VT 5 10341da177e4SLinus Torvalds #define MACH64_GT 6 10351da177e4SLinus Torvalds 10361da177e4SLinus Torvalds /* DST_CNTL register constants */ 10371da177e4SLinus Torvalds #define DST_X_RIGHT_TO_LEFT 0 10381da177e4SLinus Torvalds #define DST_X_LEFT_TO_RIGHT 1 10391da177e4SLinus Torvalds #define DST_Y_BOTTOM_TO_TOP 0 10401da177e4SLinus Torvalds #define DST_Y_TOP_TO_BOTTOM 2 10411da177e4SLinus Torvalds #define DST_X_MAJOR 0 10421da177e4SLinus Torvalds #define DST_Y_MAJOR 4 10431da177e4SLinus Torvalds #define DST_X_TILE 8 10441da177e4SLinus Torvalds #define DST_Y_TILE 0x10 10451da177e4SLinus Torvalds #define DST_LAST_PEL 0x20 10461da177e4SLinus Torvalds #define DST_POLYGON_ENABLE 0x40 10471da177e4SLinus Torvalds #define DST_24_ROTATION_ENABLE 0x80 10481da177e4SLinus Torvalds 10491da177e4SLinus Torvalds /* SRC_CNTL register constants */ 10501da177e4SLinus Torvalds #define SRC_PATTERN_ENABLE 1 10511da177e4SLinus Torvalds #define SRC_ROTATION_ENABLE 2 10521da177e4SLinus Torvalds #define SRC_LINEAR_ENABLE 4 10531da177e4SLinus Torvalds #define SRC_BYTE_ALIGN 8 10541da177e4SLinus Torvalds #define SRC_LINE_X_RIGHT_TO_LEFT 0 10551da177e4SLinus Torvalds #define SRC_LINE_X_LEFT_TO_RIGHT 0x10 10561da177e4SLinus Torvalds 10571da177e4SLinus Torvalds /* HOST_CNTL register constants */ 10581da177e4SLinus Torvalds #define HOST_BYTE_ALIGN 1 10591da177e4SLinus Torvalds 10601da177e4SLinus Torvalds /* GUI_TRAJ_CNTL register constants */ 10611da177e4SLinus Torvalds #define PAT_MONO_8x8_ENABLE 0x01000000 10621da177e4SLinus Torvalds #define PAT_CLR_4x2_ENABLE 0x02000000 10631da177e4SLinus Torvalds #define PAT_CLR_8x1_ENABLE 0x04000000 10641da177e4SLinus Torvalds 10651da177e4SLinus Torvalds /* DP_CHAIN_MASK register constants */ 10661da177e4SLinus Torvalds #define DP_CHAIN_4BPP 0x8888 10671da177e4SLinus Torvalds #define DP_CHAIN_7BPP 0xD2D2 10681da177e4SLinus Torvalds #define DP_CHAIN_8BPP 0x8080 10691da177e4SLinus Torvalds #define DP_CHAIN_8BPP_RGB 0x9292 10701da177e4SLinus Torvalds #define DP_CHAIN_15BPP 0x4210 10711da177e4SLinus Torvalds #define DP_CHAIN_16BPP 0x8410 10721da177e4SLinus Torvalds #define DP_CHAIN_24BPP 0x8080 10731da177e4SLinus Torvalds #define DP_CHAIN_32BPP 0x8080 10741da177e4SLinus Torvalds 10751da177e4SLinus Torvalds /* DP_PIX_WIDTH register constants */ 10761da177e4SLinus Torvalds #define DST_1BPP 0x0 10771da177e4SLinus Torvalds #define DST_4BPP 0x1 10781da177e4SLinus Torvalds #define DST_8BPP 0x2 10791da177e4SLinus Torvalds #define DST_15BPP 0x3 10801da177e4SLinus Torvalds #define DST_16BPP 0x4 10811da177e4SLinus Torvalds #define DST_24BPP 0x5 10821da177e4SLinus Torvalds #define DST_32BPP 0x6 10831da177e4SLinus Torvalds #define DST_MASK 0xF 10841da177e4SLinus Torvalds #define SRC_1BPP 0x000 10851da177e4SLinus Torvalds #define SRC_4BPP 0x100 10861da177e4SLinus Torvalds #define SRC_8BPP 0x200 10871da177e4SLinus Torvalds #define SRC_15BPP 0x300 10881da177e4SLinus Torvalds #define SRC_16BPP 0x400 10891da177e4SLinus Torvalds #define SRC_24BPP 0x500 10901da177e4SLinus Torvalds #define SRC_32BPP 0x600 10911da177e4SLinus Torvalds #define SRC_MASK 0xF00 10921da177e4SLinus Torvalds #define DP_HOST_TRIPLE_EN 0x2000 10931da177e4SLinus Torvalds #define HOST_1BPP 0x00000 10941da177e4SLinus Torvalds #define HOST_4BPP 0x10000 10951da177e4SLinus Torvalds #define HOST_8BPP 0x20000 10961da177e4SLinus Torvalds #define HOST_15BPP 0x30000 10971da177e4SLinus Torvalds #define HOST_16BPP 0x40000 10981da177e4SLinus Torvalds #define HOST_24BPP 0x50000 10991da177e4SLinus Torvalds #define HOST_32BPP 0x60000 11001da177e4SLinus Torvalds #define HOST_MASK 0xF0000 11011da177e4SLinus Torvalds #define BYTE_ORDER_MSB_TO_LSB 0 11021da177e4SLinus Torvalds #define BYTE_ORDER_LSB_TO_MSB 0x1000000 11031da177e4SLinus Torvalds #define BYTE_ORDER_MASK 0x1000000 11041da177e4SLinus Torvalds 11051da177e4SLinus Torvalds /* DP_MIX register constants */ 11061da177e4SLinus Torvalds #define BKGD_MIX_NOT_D 0 11071da177e4SLinus Torvalds #define BKGD_MIX_ZERO 1 11081da177e4SLinus Torvalds #define BKGD_MIX_ONE 2 11091da177e4SLinus Torvalds #define BKGD_MIX_D 3 11101da177e4SLinus Torvalds #define BKGD_MIX_NOT_S 4 11111da177e4SLinus Torvalds #define BKGD_MIX_D_XOR_S 5 11121da177e4SLinus Torvalds #define BKGD_MIX_NOT_D_XOR_S 6 11131da177e4SLinus Torvalds #define BKGD_MIX_S 7 11141da177e4SLinus Torvalds #define BKGD_MIX_NOT_D_OR_NOT_S 8 11151da177e4SLinus Torvalds #define BKGD_MIX_D_OR_NOT_S 9 11161da177e4SLinus Torvalds #define BKGD_MIX_NOT_D_OR_S 10 11171da177e4SLinus Torvalds #define BKGD_MIX_D_OR_S 11 11181da177e4SLinus Torvalds #define BKGD_MIX_D_AND_S 12 11191da177e4SLinus Torvalds #define BKGD_MIX_NOT_D_AND_S 13 11201da177e4SLinus Torvalds #define BKGD_MIX_D_AND_NOT_S 14 11211da177e4SLinus Torvalds #define BKGD_MIX_NOT_D_AND_NOT_S 15 11221da177e4SLinus Torvalds #define BKGD_MIX_D_PLUS_S_DIV2 0x17 11231da177e4SLinus Torvalds #define FRGD_MIX_NOT_D 0 11241da177e4SLinus Torvalds #define FRGD_MIX_ZERO 0x10000 11251da177e4SLinus Torvalds #define FRGD_MIX_ONE 0x20000 11261da177e4SLinus Torvalds #define FRGD_MIX_D 0x30000 11271da177e4SLinus Torvalds #define FRGD_MIX_NOT_S 0x40000 11281da177e4SLinus Torvalds #define FRGD_MIX_D_XOR_S 0x50000 11291da177e4SLinus Torvalds #define FRGD_MIX_NOT_D_XOR_S 0x60000 11301da177e4SLinus Torvalds #define FRGD_MIX_S 0x70000 11311da177e4SLinus Torvalds #define FRGD_MIX_NOT_D_OR_NOT_S 0x80000 11321da177e4SLinus Torvalds #define FRGD_MIX_D_OR_NOT_S 0x90000 11331da177e4SLinus Torvalds #define FRGD_MIX_NOT_D_OR_S 0xa0000 11341da177e4SLinus Torvalds #define FRGD_MIX_D_OR_S 0xb0000 11351da177e4SLinus Torvalds #define FRGD_MIX_D_AND_S 0xc0000 11361da177e4SLinus Torvalds #define FRGD_MIX_NOT_D_AND_S 0xd0000 11371da177e4SLinus Torvalds #define FRGD_MIX_D_AND_NOT_S 0xe0000 11381da177e4SLinus Torvalds #define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000 11391da177e4SLinus Torvalds #define FRGD_MIX_D_PLUS_S_DIV2 0x170000 11401da177e4SLinus Torvalds 11411da177e4SLinus Torvalds /* DP_SRC register constants */ 11421da177e4SLinus Torvalds #define BKGD_SRC_BKGD_CLR 0 11431da177e4SLinus Torvalds #define BKGD_SRC_FRGD_CLR 1 11441da177e4SLinus Torvalds #define BKGD_SRC_HOST 2 11451da177e4SLinus Torvalds #define BKGD_SRC_BLIT 3 11461da177e4SLinus Torvalds #define BKGD_SRC_PATTERN 4 11471da177e4SLinus Torvalds #define FRGD_SRC_BKGD_CLR 0 11481da177e4SLinus Torvalds #define FRGD_SRC_FRGD_CLR 0x100 11491da177e4SLinus Torvalds #define FRGD_SRC_HOST 0x200 11501da177e4SLinus Torvalds #define FRGD_SRC_BLIT 0x300 11511da177e4SLinus Torvalds #define FRGD_SRC_PATTERN 0x400 11521da177e4SLinus Torvalds #define MONO_SRC_ONE 0 11531da177e4SLinus Torvalds #define MONO_SRC_PATTERN 0x10000 11541da177e4SLinus Torvalds #define MONO_SRC_HOST 0x20000 11551da177e4SLinus Torvalds #define MONO_SRC_BLIT 0x30000 11561da177e4SLinus Torvalds 11571da177e4SLinus Torvalds /* CLR_CMP_CNTL register constants */ 11581da177e4SLinus Torvalds #define COMPARE_FALSE 0 11591da177e4SLinus Torvalds #define COMPARE_TRUE 1 11601da177e4SLinus Torvalds #define COMPARE_NOT_EQUAL 4 11611da177e4SLinus Torvalds #define COMPARE_EQUAL 5 11621da177e4SLinus Torvalds #define COMPARE_DESTINATION 0 11631da177e4SLinus Torvalds #define COMPARE_SOURCE 0x1000000 11641da177e4SLinus Torvalds 11651da177e4SLinus Torvalds /* FIFO_STAT register constants */ 11661da177e4SLinus Torvalds #define FIFO_ERR 0x80000000 11671da177e4SLinus Torvalds 11681da177e4SLinus Torvalds /* CONTEXT_LOAD_CNTL constants */ 11691da177e4SLinus Torvalds #define CONTEXT_NO_LOAD 0 11701da177e4SLinus Torvalds #define CONTEXT_LOAD 0x10000 11711da177e4SLinus Torvalds #define CONTEXT_LOAD_AND_DO_FILL 0x20000 11721da177e4SLinus Torvalds #define CONTEXT_LOAD_AND_DO_LINE 0x30000 11731da177e4SLinus Torvalds #define CONTEXT_EXECUTE 0 11741da177e4SLinus Torvalds #define CONTEXT_CMD_DISABLE 0x80000000 11751da177e4SLinus Torvalds 11761da177e4SLinus Torvalds /* GUI_STAT register constants */ 11771da177e4SLinus Torvalds #define ENGINE_IDLE 0 11781da177e4SLinus Torvalds #define ENGINE_BUSY 1 11791da177e4SLinus Torvalds #define SCISSOR_LEFT_FLAG 0x10 11801da177e4SLinus Torvalds #define SCISSOR_RIGHT_FLAG 0x20 11811da177e4SLinus Torvalds #define SCISSOR_TOP_FLAG 0x40 11821da177e4SLinus Torvalds #define SCISSOR_BOTTOM_FLAG 0x80 11831da177e4SLinus Torvalds 11841da177e4SLinus Torvalds /* ATI VGA Extended Regsiters */ 11851da177e4SLinus Torvalds #define sioATIEXT 0x1ce 11861da177e4SLinus Torvalds #define bioATIEXT 0x3ce 11871da177e4SLinus Torvalds 11881da177e4SLinus Torvalds #define ATI2E 0xae 11891da177e4SLinus Torvalds #define ATI32 0xb2 11901da177e4SLinus Torvalds #define ATI36 0xb6 11911da177e4SLinus Torvalds 11921da177e4SLinus Torvalds /* VGA Graphics Controller Registers */ 11931da177e4SLinus Torvalds #define R_GENMO 0x3cc 11941da177e4SLinus Torvalds #define VGAGRA 0x3ce 11951da177e4SLinus Torvalds #define GRA06 0x06 11961da177e4SLinus Torvalds 11971da177e4SLinus Torvalds /* VGA Seququencer Registers */ 11981da177e4SLinus Torvalds #define VGASEQ 0x3c4 11991da177e4SLinus Torvalds #define SEQ02 0x02 12001da177e4SLinus Torvalds #define SEQ04 0x04 12011da177e4SLinus Torvalds 12021da177e4SLinus Torvalds #define MACH64_MAX_X ENGINE_MAX_X 12031da177e4SLinus Torvalds #define MACH64_MAX_Y ENGINE_MAX_Y 12041da177e4SLinus Torvalds 12051da177e4SLinus Torvalds #define INC_X 0x0020 12061da177e4SLinus Torvalds #define INC_Y 0x0080 12071da177e4SLinus Torvalds 12081da177e4SLinus Torvalds #define RGB16_555 0x0000 12091da177e4SLinus Torvalds #define RGB16_565 0x0040 12101da177e4SLinus Torvalds #define RGB16_655 0x0080 12111da177e4SLinus Torvalds #define RGB16_664 0x00c0 12121da177e4SLinus Torvalds 12131da177e4SLinus Torvalds #define POLY_TEXT_TYPE 0x0001 12141da177e4SLinus Torvalds #define IMAGE_TEXT_TYPE 0x0002 12151da177e4SLinus Torvalds #define TEXT_TYPE_8_BIT 0x0004 12161da177e4SLinus Torvalds #define TEXT_TYPE_16_BIT 0x0008 12171da177e4SLinus Torvalds #define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT) 12181da177e4SLinus Torvalds #define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT) 12191da177e4SLinus Torvalds #define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT) 12201da177e4SLinus Torvalds #define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT) 12211da177e4SLinus Torvalds 12221da177e4SLinus Torvalds #define MACH64_NUM_CLOCKS 16 12231da177e4SLinus Torvalds #define MACH64_NUM_FREQS 50 12241da177e4SLinus Torvalds 12251da177e4SLinus Torvalds /* Power Management register constants (LT & LT Pro) */ 12261da177e4SLinus Torvalds #define PWR_MGT_ON 0x00000001 12271da177e4SLinus Torvalds #define PWR_MGT_MODE_MASK 0x00000006 12281da177e4SLinus Torvalds #define AUTO_PWR_UP 0x00000008 12291da177e4SLinus Torvalds #define USE_F32KHZ 0x00000400 12301da177e4SLinus Torvalds #define TRISTATE_MEM_EN 0x00000800 12311da177e4SLinus Torvalds #define SELF_REFRESH 0x00000080 12321da177e4SLinus Torvalds #define PWR_BLON 0x02000000 12331da177e4SLinus Torvalds #define STANDBY_NOW 0x10000000 12341da177e4SLinus Torvalds #define SUSPEND_NOW 0x20000000 12351da177e4SLinus Torvalds #define PWR_MGT_STATUS_MASK 0xC0000000 12361da177e4SLinus Torvalds #define PWR_MGT_STATUS_SUSPEND 0x80000000 12371da177e4SLinus Torvalds 12381da177e4SLinus Torvalds /* PM Mode constants */ 12391da177e4SLinus Torvalds #define PWR_MGT_MODE_PIN 0x00000000 12401da177e4SLinus Torvalds #define PWR_MGT_MODE_REG 0x00000002 12411da177e4SLinus Torvalds #define PWR_MGT_MODE_TIMER 0x00000004 12421da177e4SLinus Torvalds #define PWR_MGT_MODE_PCI 0x00000006 12431da177e4SLinus Torvalds 12441da177e4SLinus Torvalds /* LCD registers (LT Pro) */ 12451da177e4SLinus Torvalds 12461da177e4SLinus Torvalds /* LCD Index register */ 12471da177e4SLinus Torvalds #define LCD_INDEX_MASK 0x0000003F 12481da177e4SLinus Torvalds #define LCD_DISPLAY_DIS 0x00000100 12491da177e4SLinus Torvalds #define LCD_SRC_SEL 0x00000200 12501da177e4SLinus Torvalds #define CRTC2_DISPLAY_DIS 0x00000400 12511da177e4SLinus Torvalds 12521da177e4SLinus Torvalds /* LCD register indices */ 1253fe86175bSRandy Dunlap #define CNFG_PANEL 0x00 12541da177e4SLinus Torvalds #define LCD_GEN_CNTL 0x01 12551da177e4SLinus Torvalds #define DSTN_CONTROL 0x02 12561da177e4SLinus Torvalds #define HFB_PITCH_ADDR 0x03 12571da177e4SLinus Torvalds #define HORZ_STRETCHING 0x04 12581da177e4SLinus Torvalds #define VERT_STRETCHING 0x05 12591da177e4SLinus Torvalds #define EXT_VERT_STRETCH 0x06 12601da177e4SLinus Torvalds #define LT_GIO 0x07 12611da177e4SLinus Torvalds #define POWER_MANAGEMENT 0x08 12621da177e4SLinus Torvalds #define ZVGPIO 0x09 12631da177e4SLinus Torvalds #define ICON_CLR0 0x0A 12641da177e4SLinus Torvalds #define ICON_CLR1 0x0B 12651da177e4SLinus Torvalds #define ICON_OFFSET 0x0C 12661da177e4SLinus Torvalds #define ICON_HORZ_VERT_POSN 0x0D 12671da177e4SLinus Torvalds #define ICON_HORZ_VERT_OFF 0x0E 12681da177e4SLinus Torvalds #define ICON2_CLR0 0x0F 12691da177e4SLinus Torvalds #define ICON2_CLR1 0x10 12701da177e4SLinus Torvalds #define ICON2_OFFSET 0x11 12711da177e4SLinus Torvalds #define ICON2_HORZ_VERT_POSN 0x12 12721da177e4SLinus Torvalds #define ICON2_HORZ_VERT_OFF 0x13 12731da177e4SLinus Torvalds #define LCD_MISC_CNTL 0x14 12741da177e4SLinus Torvalds #define APC_CNTL 0x1C 12751da177e4SLinus Torvalds #define POWER_MANAGEMENT_2 0x1D 12761da177e4SLinus Torvalds #define ALPHA_BLENDING 0x25 12771da177e4SLinus Torvalds #define PORTRAIT_GEN_CNTL 0x26 12781da177e4SLinus Torvalds #define APC_CTRL_IO 0x27 12791da177e4SLinus Torvalds #define TEST_IO 0x28 12801da177e4SLinus Torvalds #define TEST_OUTPUTS 0x29 12811da177e4SLinus Torvalds #define DP1_MEM_ACCESS 0x2A 12821da177e4SLinus Torvalds #define DP0_MEM_ACCESS 0x2B 12831da177e4SLinus Torvalds #define DP0_DEBUG_A 0x2C 12841da177e4SLinus Torvalds #define DP0_DEBUG_B 0x2D 12851da177e4SLinus Torvalds #define DP1_DEBUG_A 0x2E 12861da177e4SLinus Torvalds #define DP1_DEBUG_B 0x2F 12871da177e4SLinus Torvalds #define DPCTRL_DEBUG_A 0x30 12881da177e4SLinus Torvalds #define DPCTRL_DEBUG_B 0x31 12891da177e4SLinus Torvalds #define MEMBLK_DEBUG 0x32 12901da177e4SLinus Torvalds #define APC_LUT_AB 0x33 12911da177e4SLinus Torvalds #define APC_LUT_CD 0x34 12921da177e4SLinus Torvalds #define APC_LUT_EF 0x35 12931da177e4SLinus Torvalds #define APC_LUT_GH 0x36 12941da177e4SLinus Torvalds #define APC_LUT_IJ 0x37 12951da177e4SLinus Torvalds #define APC_LUT_KL 0x38 12961da177e4SLinus Torvalds #define APC_LUT_MN 0x39 12971da177e4SLinus Torvalds #define APC_LUT_OP 0x3A 12981da177e4SLinus Torvalds 12991da177e4SLinus Torvalds /* Values in LCD_GEN_CTRL */ 13001da177e4SLinus Torvalds #define CRT_ON 0x00000001ul 13011da177e4SLinus Torvalds #define LCD_ON 0x00000002ul 13021da177e4SLinus Torvalds #define HORZ_DIVBY2_EN 0x00000004ul 13031da177e4SLinus Torvalds #define DONT_DS_ICON 0x00000008ul 13041da177e4SLinus Torvalds #define LOCK_8DOT 0x00000010ul 13051da177e4SLinus Torvalds #define ICON_ENABLE 0x00000020ul 13061da177e4SLinus Torvalds #define DONT_SHADOW_VPAR 0x00000040ul 13071da177e4SLinus Torvalds #define V2CLK_PM_EN 0x00000080ul 13081da177e4SLinus Torvalds #define RST_FM 0x00000100ul 13091da177e4SLinus Torvalds #define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ 13101da177e4SLinus Torvalds #define DIS_HOR_CRT_DIVBY2 0x00000400ul 13111da177e4SLinus Torvalds #define SCLK_SEL 0x00000800ul 13121da177e4SLinus Torvalds #define SCLK_DELAY 0x0000f000ul 13131da177e4SLinus Torvalds #define TVCLK_PM_EN 0x00010000ul 13141da177e4SLinus Torvalds #define VCLK_DAC_PM_EN 0x00020000ul 13151da177e4SLinus Torvalds #define VCLK_LCD_OFF 0x00040000ul 13161da177e4SLinus Torvalds #define SELECT_WAIT_4MS 0x00080000ul 13171da177e4SLinus Torvalds #define XTALIN_PM_EN 0x00080000ul /* XC/XL */ 13181da177e4SLinus Torvalds #define V2CLK_DAC_PM_EN 0x00100000ul 13191da177e4SLinus Torvalds #define LVDS_EN 0x00200000ul 13201da177e4SLinus Torvalds #define LVDS_PLL_EN 0x00400000ul 13211da177e4SLinus Torvalds #define LVDS_PLL_RESET 0x00800000ul 13221da177e4SLinus Torvalds #define LVDS_RESERVED_BITS 0x07000000ul 13231da177e4SLinus Torvalds #define CRTC_RW_SELECT 0x08000000ul /* LTPro */ 13241da177e4SLinus Torvalds #define USE_SHADOWED_VEND 0x10000000ul 13251da177e4SLinus Torvalds #define USE_SHADOWED_ROWCUR 0x20000000ul 13261da177e4SLinus Torvalds #define SHADOW_EN 0x40000000ul 13271da177e4SLinus Torvalds #define SHADOW_RW_EN 0x80000000ul 13281da177e4SLinus Torvalds 13291da177e4SLinus Torvalds #define LCD_SET_PRIMARY_MASK 0x07FFFBFBul 13301da177e4SLinus Torvalds 13311da177e4SLinus Torvalds /* Values in HORZ_STRETCHING */ 13321da177e4SLinus Torvalds #define HORZ_STRETCH_BLEND 0x00000ffful 13331da177e4SLinus Torvalds #define HORZ_STRETCH_RATIO 0x0000fffful 13341da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP 0x00070000ul 13351da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP09 0x00000000ul 13361da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP11 0x00010000ul 13371da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP12 0x00020000ul 13381da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP14 0x00030000ul 13391da177e4SLinus Torvalds #define HORZ_STRETCH_LOOP15 0x00040000ul 13401da177e4SLinus Torvalds /* ? 0x00050000ul */ 13411da177e4SLinus Torvalds /* ? 0x00060000ul */ 13421da177e4SLinus Torvalds /* ? 0x00070000ul */ 13431da177e4SLinus Torvalds /* ? 0x00080000ul */ 13441da177e4SLinus Torvalds #define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ 13451da177e4SLinus Torvalds /* ? 0x10000000ul */ 13461da177e4SLinus Torvalds #define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ 13471da177e4SLinus Torvalds #define HORZ_STRETCH_MODE 0x40000000ul 13481da177e4SLinus Torvalds #define HORZ_STRETCH_EN 0x80000000ul 13491da177e4SLinus Torvalds 13501da177e4SLinus Torvalds /* Values in VERT_STRETCHING */ 13511da177e4SLinus Torvalds #define VERT_STRETCH_RATIO0 0x000003fful 13521da177e4SLinus Torvalds #define VERT_STRETCH_RATIO1 0x000ffc00ul 13531da177e4SLinus Torvalds #define VERT_STRETCH_RATIO2 0x3ff00000ul 13541da177e4SLinus Torvalds #define VERT_STRETCH_USE0 0x40000000ul 13551da177e4SLinus Torvalds #define VERT_STRETCH_EN 0x80000000ul 13561da177e4SLinus Torvalds 13571da177e4SLinus Torvalds /* Values in EXT_VERT_STRETCH */ 13581da177e4SLinus Torvalds #define VERT_STRETCH_RATIO3 0x000003fful 13591da177e4SLinus Torvalds #define FORCE_DAC_DATA 0x000000fful 13601da177e4SLinus Torvalds #define FORCE_DAC_DATA_SEL 0x00000300ul 13611da177e4SLinus Torvalds #define VERT_STRETCH_MODE 0x00000400ul 13621da177e4SLinus Torvalds #define VERT_PANEL_SIZE 0x003ff800ul 13631da177e4SLinus Torvalds #define AUTO_VERT_RATIO 0x00400000ul 13641da177e4SLinus Torvalds #define USE_AUTO_FP_POS 0x00800000ul 13651da177e4SLinus Torvalds #define USE_AUTO_LCD_VSYNC 0x01000000ul 13661da177e4SLinus Torvalds /* ? 0xfe000000ul */ 13671da177e4SLinus Torvalds 13681da177e4SLinus Torvalds /* Values in LCD_MISC_CNTL */ 13691da177e4SLinus Torvalds #define BIAS_MOD_LEVEL_MASK 0x0000ff00 13701da177e4SLinus Torvalds #define BIAS_MOD_LEVEL_SHIFT 8 13711da177e4SLinus Torvalds #define BLMOD_EN 0x00010000 13721da177e4SLinus Torvalds #define BIASMOD_EN 0x00020000 13731da177e4SLinus Torvalds 13741da177e4SLinus Torvalds #endif /* REGMACH64_H */ 1375