1f30c2269SUwe Zeisberger /* include/video/s1d13xxxfb.h 21da177e4SLinus Torvalds * 31da177e4SLinus Torvalds * (c) 2004 Simtec Electronics 41da177e4SLinus Torvalds * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org> 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Header file for Epson S1D13XXX driver code 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 91da177e4SLinus Torvalds * License. See the file COPYING in the main directory of this archive for 101da177e4SLinus Torvalds * more details. 111da177e4SLinus Torvalds */ 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds #ifndef S1D13XXXFB_H 141da177e4SLinus Torvalds #define S1D13XXXFB_H 151da177e4SLinus Torvalds 161da177e4SLinus Torvalds #define S1D_PALETTE_SIZE 256 17afbb9d8dSKristoffer Ericson #define S1D_FBID "S1D13xxx" 18afbb9d8dSKristoffer Ericson #define S1D_DEVICENAME "s1d13xxxfb" 19afbb9d8dSKristoffer Ericson 20afbb9d8dSKristoffer Ericson /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */ 21afbb9d8dSKristoffer Ericson #define S1D13505_PROD_ID 0x3 /* 000011 */ 22afbb9d8dSKristoffer Ericson #define S1D13506_PROD_ID 0x4 /* 000100 */ 23afbb9d8dSKristoffer Ericson #define S1D13806_PROD_ID 0x7 /* 000111 */ 241da177e4SLinus Torvalds 251da177e4SLinus Torvalds /* register definitions (tested on s1d13896) */ 26afbb9d8dSKristoffer Ericson #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */ 271da177e4SLinus Torvalds #define S1DREG_MISC 0x0001 /* Miscellaneous Register */ 281da177e4SLinus Torvalds #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */ 291da177e4SLinus Torvalds #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */ 301da177e4SLinus Torvalds #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */ 311da177e4SLinus Torvalds #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */ 321da177e4SLinus Torvalds #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */ 331da177e4SLinus Torvalds #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */ 341da177e4SLinus Torvalds #define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */ 351da177e4SLinus Torvalds #define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */ 361da177e4SLinus Torvalds #define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */ 371da177e4SLinus Torvalds #define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */ 381da177e4SLinus Torvalds #define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */ 391da177e4SLinus Torvalds #define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */ 401da177e4SLinus Torvalds #define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */ 411da177e4SLinus Torvalds #define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */ 421da177e4SLinus Torvalds #define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */ 431da177e4SLinus Torvalds #define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */ 441da177e4SLinus Torvalds #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */ 451da177e4SLinus Torvalds #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */ 461da177e4SLinus Torvalds #define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */ 471da177e4SLinus Torvalds #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */ 481da177e4SLinus Torvalds #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */ 491da177e4SLinus Torvalds #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */ 501da177e4SLinus Torvalds #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */ 511da177e4SLinus Torvalds #define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */ 521da177e4SLinus Torvalds #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */ 531da177e4SLinus Torvalds #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */ 541da177e4SLinus Torvalds #define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */ 551da177e4SLinus Torvalds #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */ 561da177e4SLinus Torvalds #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */ 571da177e4SLinus Torvalds #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */ 581da177e4SLinus Torvalds #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */ 591da177e4SLinus Torvalds #define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */ 601da177e4SLinus Torvalds #define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */ 611da177e4SLinus Torvalds #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */ 621da177e4SLinus Torvalds #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */ 631da177e4SLinus Torvalds #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */ 641da177e4SLinus Torvalds #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */ 651da177e4SLinus Torvalds #define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */ 661da177e4SLinus Torvalds #define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */ 671da177e4SLinus Torvalds #define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */ 681da177e4SLinus Torvalds #define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */ 691da177e4SLinus Torvalds #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */ 701da177e4SLinus Torvalds #define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */ 711da177e4SLinus Torvalds #define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */ 721da177e4SLinus Torvalds #define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */ 731da177e4SLinus Torvalds #define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */ 741da177e4SLinus Torvalds #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */ 751da177e4SLinus Torvalds #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */ 761da177e4SLinus Torvalds #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */ 771da177e4SLinus Torvalds #define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */ 781da177e4SLinus Torvalds #define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */ 791da177e4SLinus Torvalds #define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */ 801da177e4SLinus Torvalds #define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */ 811da177e4SLinus Torvalds #define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */ 821da177e4SLinus Torvalds #define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */ 831da177e4SLinus Torvalds #define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */ 841da177e4SLinus Torvalds #define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */ 851da177e4SLinus Torvalds #define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */ 861da177e4SLinus Torvalds #define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */ 871da177e4SLinus Torvalds #define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */ 881da177e4SLinus Torvalds #define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */ 891da177e4SLinus Torvalds #define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */ 901da177e4SLinus Torvalds #define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */ 911da177e4SLinus Torvalds #define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */ 921da177e4SLinus Torvalds #define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */ 931da177e4SLinus Torvalds #define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */ 941da177e4SLinus Torvalds #define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */ 951da177e4SLinus Torvalds #define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */ 961da177e4SLinus Torvalds #define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */ 971da177e4SLinus Torvalds #define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */ 981da177e4SLinus Torvalds #define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */ 991da177e4SLinus Torvalds #define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */ 1001da177e4SLinus Torvalds #define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */ 1011da177e4SLinus Torvalds #define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */ 1021da177e4SLinus Torvalds #define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */ 1031da177e4SLinus Torvalds #define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */ 1041da177e4SLinus Torvalds #define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */ 1051da177e4SLinus Torvalds #define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */ 1061da177e4SLinus Torvalds #define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */ 1071da177e4SLinus Torvalds #define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */ 1081da177e4SLinus Torvalds #define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */ 1091da177e4SLinus Torvalds #define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */ 1101da177e4SLinus Torvalds #define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */ 1111da177e4SLinus Torvalds #define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */ 1121da177e4SLinus Torvalds #define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */ 1131da177e4SLinus Torvalds #define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */ 1141da177e4SLinus Torvalds #define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */ 1151da177e4SLinus Torvalds #define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */ 1161da177e4SLinus Torvalds #define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */ 1171da177e4SLinus Torvalds #define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */ 1181da177e4SLinus Torvalds #define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */ 1191da177e4SLinus Torvalds #define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */ 1201da177e4SLinus Torvalds #define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */ 1211da177e4SLinus Torvalds #define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */ 1221da177e4SLinus Torvalds #define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */ 1231da177e4SLinus Torvalds #define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */ 1241da177e4SLinus Torvalds #define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */ 1251da177e4SLinus Torvalds #define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */ 1261da177e4SLinus Torvalds #define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */ 1271da177e4SLinus Torvalds #define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */ 1281da177e4SLinus Torvalds #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */ 1291da177e4SLinus Torvalds #define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */ 1301da177e4SLinus Torvalds #define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */ 1311da177e4SLinus Torvalds #define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */ 1321da177e4SLinus Torvalds #define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */ 1331da177e4SLinus Torvalds #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */ 1341da177e4SLinus Torvalds #define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */ 1351da177e4SLinus Torvalds 1361da177e4SLinus Torvalds #define S1DREG_DELAYOFF 0xFFFE 1371da177e4SLinus Torvalds #define S1DREG_DELAYON 0xFFFF 1381da177e4SLinus Torvalds 139*3ed167afSKristoffer Ericson #define BBLT_SOLID_FILL 0x0c 140*3ed167afSKristoffer Ericson 141*3ed167afSKristoffer Ericson 1421da177e4SLinus Torvalds /* Note: all above defines should go in separate header files 1431da177e4SLinus Torvalds when implementing other S1D13xxx chip support. */ 1441da177e4SLinus Torvalds 1451da177e4SLinus Torvalds struct s1d13xxxfb_regval { 1461da177e4SLinus Torvalds u16 addr; 1471da177e4SLinus Torvalds u8 value; 1481da177e4SLinus Torvalds }; 1491da177e4SLinus Torvalds 1501da177e4SLinus Torvalds struct s1d13xxxfb_par { 1511da177e4SLinus Torvalds void __iomem *regs; 1521da177e4SLinus Torvalds unsigned char display; 153afbb9d8dSKristoffer Ericson unsigned char prod_id; 154afbb9d8dSKristoffer Ericson unsigned char revision; 1551da177e4SLinus Torvalds 1561da177e4SLinus Torvalds unsigned int pseudo_palette[16]; 1571da177e4SLinus Torvalds #ifdef CONFIG_PM 1581da177e4SLinus Torvalds void *regs_save; /* pm saves all registers here */ 1591da177e4SLinus Torvalds void *disp_save; /* pm saves entire screen here */ 1601da177e4SLinus Torvalds #endif 1611da177e4SLinus Torvalds }; 1621da177e4SLinus Torvalds 1631da177e4SLinus Torvalds struct s1d13xxxfb_pdata { 1641da177e4SLinus Torvalds const struct s1d13xxxfb_regval *initregs; 1651da177e4SLinus Torvalds const unsigned int initregssize; 1661da177e4SLinus Torvalds void (*platform_init_video)(void); 1671da177e4SLinus Torvalds #ifdef CONFIG_PM 1681da177e4SLinus Torvalds int (*platform_suspend_video)(void); 1691da177e4SLinus Torvalds int (*platform_resume_video)(void); 1701da177e4SLinus Torvalds #endif 1711da177e4SLinus Torvalds }; 1721da177e4SLinus Torvalds 1731da177e4SLinus Torvalds #endif 1741da177e4SLinus Torvalds 175