1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 214ff6a09STakashi Sakamoto #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED 314ff6a09STakashi Sakamoto #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED 414ff6a09STakashi Sakamoto 514ff6a09STakashi Sakamoto /* 614ff6a09STakashi Sakamoto * DICE device interface definitions 714ff6a09STakashi Sakamoto */ 814ff6a09STakashi Sakamoto 914ff6a09STakashi Sakamoto /* 1014ff6a09STakashi Sakamoto * Generally, all registers can be read like memory, i.e., with quadlet read or 1114ff6a09STakashi Sakamoto * block read transactions with at least quadlet-aligned offset and length. 1214ff6a09STakashi Sakamoto * Writes are not allowed except where noted; quadlet-sized registers must be 1314ff6a09STakashi Sakamoto * written with a quadlet write transaction. 1414ff6a09STakashi Sakamoto * 1514ff6a09STakashi Sakamoto * All values are in big endian. The DICE firmware runs on a little-endian CPU 1614ff6a09STakashi Sakamoto * and just byte-swaps _all_ quadlets on the bus, so values without endianness 1714ff6a09STakashi Sakamoto * (e.g. strings) get scrambled and must be byte-swapped again by the driver. 1814ff6a09STakashi Sakamoto */ 1914ff6a09STakashi Sakamoto 2014ff6a09STakashi Sakamoto /* 2114ff6a09STakashi Sakamoto * Streaming is handled by the "DICE driver" interface. Its registers are 2214ff6a09STakashi Sakamoto * located in this private address space. 2314ff6a09STakashi Sakamoto */ 2414ff6a09STakashi Sakamoto #define DICE_PRIVATE_SPACE 0xffffe0000000uLL 2514ff6a09STakashi Sakamoto 2614ff6a09STakashi Sakamoto /* 2714ff6a09STakashi Sakamoto * The registers are organized in several sections, which are organized 2814ff6a09STakashi Sakamoto * separately to allow them to be extended individually. Whether a register is 2914ff6a09STakashi Sakamoto * supported can be detected by checking its offset against its section's size. 3014ff6a09STakashi Sakamoto * 3114ff6a09STakashi Sakamoto * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/ 3214ff6a09STakashi Sakamoto * size values are measured in quadlets. Read-only. 3314ff6a09STakashi Sakamoto */ 3414ff6a09STakashi Sakamoto #define DICE_GLOBAL_OFFSET 0x00 3514ff6a09STakashi Sakamoto #define DICE_GLOBAL_SIZE 0x04 3614ff6a09STakashi Sakamoto #define DICE_TX_OFFSET 0x08 3714ff6a09STakashi Sakamoto #define DICE_TX_SIZE 0x0c 3814ff6a09STakashi Sakamoto #define DICE_RX_OFFSET 0x10 3914ff6a09STakashi Sakamoto #define DICE_RX_SIZE 0x14 4014ff6a09STakashi Sakamoto #define DICE_EXT_SYNC_OFFSET 0x18 4114ff6a09STakashi Sakamoto #define DICE_EXT_SYNC_SIZE 0x1c 4214ff6a09STakashi Sakamoto #define DICE_UNUSED2_OFFSET 0x20 4314ff6a09STakashi Sakamoto #define DICE_UNUSED2_SIZE 0x24 4414ff6a09STakashi Sakamoto 4514ff6a09STakashi Sakamoto /* 4614ff6a09STakashi Sakamoto * Global settings. 4714ff6a09STakashi Sakamoto */ 4814ff6a09STakashi Sakamoto 4914ff6a09STakashi Sakamoto /* 5014ff6a09STakashi Sakamoto * Stores the full 64-bit address (node ID and offset in the node's address 5114ff6a09STakashi Sakamoto * space) where the device will send notifications. Must be changed with 5214ff6a09STakashi Sakamoto * a compare/swap transaction by the owner. This register is automatically 5314ff6a09STakashi Sakamoto * cleared on a bus reset. 5414ff6a09STakashi Sakamoto */ 5514ff6a09STakashi Sakamoto #define GLOBAL_OWNER 0x000 5614ff6a09STakashi Sakamoto #define OWNER_NO_OWNER 0xffff000000000000uLL 5714ff6a09STakashi Sakamoto #define OWNER_NODE_SHIFT 48 5814ff6a09STakashi Sakamoto 5914ff6a09STakashi Sakamoto /* 6014ff6a09STakashi Sakamoto * A bitmask with asynchronous events; read-only. When any event(s) happen, 6114ff6a09STakashi Sakamoto * the bits of previous events are cleared, and the value of this register is 6214ff6a09STakashi Sakamoto * also written to the address stored in the owner register. 6314ff6a09STakashi Sakamoto */ 6414ff6a09STakashi Sakamoto #define GLOBAL_NOTIFICATION 0x008 6514ff6a09STakashi Sakamoto /* Some registers in the Rx/Tx sections may have changed. */ 6614ff6a09STakashi Sakamoto #define NOTIFY_RX_CFG_CHG 0x00000001 6714ff6a09STakashi Sakamoto #define NOTIFY_TX_CFG_CHG 0x00000002 6814ff6a09STakashi Sakamoto /* Lock status of the current clock source may have changed. */ 6914ff6a09STakashi Sakamoto #define NOTIFY_LOCK_CHG 0x00000010 7014ff6a09STakashi Sakamoto /* Write to the clock select register has been finished. */ 7114ff6a09STakashi Sakamoto #define NOTIFY_CLOCK_ACCEPTED 0x00000020 7214ff6a09STakashi Sakamoto /* Lock status of some clock source has changed. */ 7314ff6a09STakashi Sakamoto #define NOTIFY_EXT_STATUS 0x00000040 7414ff6a09STakashi Sakamoto /* Other bits may be used for device-specific events. */ 7514ff6a09STakashi Sakamoto 7614ff6a09STakashi Sakamoto /* 7714ff6a09STakashi Sakamoto * A name that can be customized for each device; read/write. Padded with zero 7814ff6a09STakashi Sakamoto * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver 7914ff6a09STakashi Sakamoto * happens to be using. 8014ff6a09STakashi Sakamoto */ 8114ff6a09STakashi Sakamoto #define GLOBAL_NICK_NAME 0x00c 8214ff6a09STakashi Sakamoto #define NICK_NAME_SIZE 64 8314ff6a09STakashi Sakamoto 8414ff6a09STakashi Sakamoto /* 8514ff6a09STakashi Sakamoto * The current sample rate and clock source; read/write. Whether a clock 8614ff6a09STakashi Sakamoto * source or sample rate is supported is device-specific; the internal clock 8714ff6a09STakashi Sakamoto * source is always available. Low/mid/high = up to 48/96/192 kHz. This 8814ff6a09STakashi Sakamoto * register can be changed even while streams are running. 8914ff6a09STakashi Sakamoto */ 9014ff6a09STakashi Sakamoto #define GLOBAL_CLOCK_SELECT 0x04c 9114ff6a09STakashi Sakamoto #define CLOCK_SOURCE_MASK 0x000000ff 9214ff6a09STakashi Sakamoto #define CLOCK_SOURCE_AES1 0x00000000 9314ff6a09STakashi Sakamoto #define CLOCK_SOURCE_AES2 0x00000001 9414ff6a09STakashi Sakamoto #define CLOCK_SOURCE_AES3 0x00000002 9514ff6a09STakashi Sakamoto #define CLOCK_SOURCE_AES4 0x00000003 9614ff6a09STakashi Sakamoto #define CLOCK_SOURCE_AES_ANY 0x00000004 9714ff6a09STakashi Sakamoto #define CLOCK_SOURCE_ADAT 0x00000005 9814ff6a09STakashi Sakamoto #define CLOCK_SOURCE_TDIF 0x00000006 9914ff6a09STakashi Sakamoto #define CLOCK_SOURCE_WC 0x00000007 10014ff6a09STakashi Sakamoto #define CLOCK_SOURCE_ARX1 0x00000008 10114ff6a09STakashi Sakamoto #define CLOCK_SOURCE_ARX2 0x00000009 10214ff6a09STakashi Sakamoto #define CLOCK_SOURCE_ARX3 0x0000000a 10314ff6a09STakashi Sakamoto #define CLOCK_SOURCE_ARX4 0x0000000b 10414ff6a09STakashi Sakamoto #define CLOCK_SOURCE_INTERNAL 0x0000000c 10514ff6a09STakashi Sakamoto #define CLOCK_RATE_MASK 0x0000ff00 10614ff6a09STakashi Sakamoto #define CLOCK_RATE_32000 0x00000000 10714ff6a09STakashi Sakamoto #define CLOCK_RATE_44100 0x00000100 10814ff6a09STakashi Sakamoto #define CLOCK_RATE_48000 0x00000200 10914ff6a09STakashi Sakamoto #define CLOCK_RATE_88200 0x00000300 11014ff6a09STakashi Sakamoto #define CLOCK_RATE_96000 0x00000400 11114ff6a09STakashi Sakamoto #define CLOCK_RATE_176400 0x00000500 11214ff6a09STakashi Sakamoto #define CLOCK_RATE_192000 0x00000600 11314ff6a09STakashi Sakamoto #define CLOCK_RATE_ANY_LOW 0x00000700 11414ff6a09STakashi Sakamoto #define CLOCK_RATE_ANY_MID 0x00000800 11514ff6a09STakashi Sakamoto #define CLOCK_RATE_ANY_HIGH 0x00000900 11614ff6a09STakashi Sakamoto #define CLOCK_RATE_NONE 0x00000a00 11714ff6a09STakashi Sakamoto #define CLOCK_RATE_SHIFT 8 11814ff6a09STakashi Sakamoto 11914ff6a09STakashi Sakamoto /* 12014ff6a09STakashi Sakamoto * Enable streaming; read/write. Writing a non-zero value (re)starts all 12114ff6a09STakashi Sakamoto * streams that have a valid iso channel set; zero stops all streams. The 12214ff6a09STakashi Sakamoto * streams' parameters must be configured before starting. This register is 12314ff6a09STakashi Sakamoto * automatically cleared on a bus reset. 12414ff6a09STakashi Sakamoto */ 12514ff6a09STakashi Sakamoto #define GLOBAL_ENABLE 0x050 12614ff6a09STakashi Sakamoto 12714ff6a09STakashi Sakamoto /* 12814ff6a09STakashi Sakamoto * Status of the sample clock; read-only. 12914ff6a09STakashi Sakamoto */ 13014ff6a09STakashi Sakamoto #define GLOBAL_STATUS 0x054 13114ff6a09STakashi Sakamoto /* The current clock source is locked. */ 13214ff6a09STakashi Sakamoto #define STATUS_SOURCE_LOCKED 0x00000001 13314ff6a09STakashi Sakamoto /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */ 13414ff6a09STakashi Sakamoto #define STATUS_NOMINAL_RATE_MASK 0x0000ff00 13514ff6a09STakashi Sakamoto 13614ff6a09STakashi Sakamoto /* 13714ff6a09STakashi Sakamoto * Status of all clock sources; read-only. 13814ff6a09STakashi Sakamoto */ 13914ff6a09STakashi Sakamoto #define GLOBAL_EXTENDED_STATUS 0x058 14014ff6a09STakashi Sakamoto /* 14114ff6a09STakashi Sakamoto * The _LOCKED bits always show the current status; any change generates 14214ff6a09STakashi Sakamoto * a notification. 14314ff6a09STakashi Sakamoto */ 14414ff6a09STakashi Sakamoto #define EXT_STATUS_AES1_LOCKED 0x00000001 14514ff6a09STakashi Sakamoto #define EXT_STATUS_AES2_LOCKED 0x00000002 14614ff6a09STakashi Sakamoto #define EXT_STATUS_AES3_LOCKED 0x00000004 14714ff6a09STakashi Sakamoto #define EXT_STATUS_AES4_LOCKED 0x00000008 14814ff6a09STakashi Sakamoto #define EXT_STATUS_ADAT_LOCKED 0x00000010 14914ff6a09STakashi Sakamoto #define EXT_STATUS_TDIF_LOCKED 0x00000020 15014ff6a09STakashi Sakamoto #define EXT_STATUS_ARX1_LOCKED 0x00000040 15114ff6a09STakashi Sakamoto #define EXT_STATUS_ARX2_LOCKED 0x00000080 15214ff6a09STakashi Sakamoto #define EXT_STATUS_ARX3_LOCKED 0x00000100 15314ff6a09STakashi Sakamoto #define EXT_STATUS_ARX4_LOCKED 0x00000200 15414ff6a09STakashi Sakamoto #define EXT_STATUS_WC_LOCKED 0x00000400 15514ff6a09STakashi Sakamoto /* 15614ff6a09STakashi Sakamoto * The _SLIP bits do not generate notifications; a set bit indicates that an 15714ff6a09STakashi Sakamoto * error occurred since the last time when this register was read with 15814ff6a09STakashi Sakamoto * a quadlet read transaction. 15914ff6a09STakashi Sakamoto */ 16014ff6a09STakashi Sakamoto #define EXT_STATUS_AES1_SLIP 0x00010000 16114ff6a09STakashi Sakamoto #define EXT_STATUS_AES2_SLIP 0x00020000 16214ff6a09STakashi Sakamoto #define EXT_STATUS_AES3_SLIP 0x00040000 16314ff6a09STakashi Sakamoto #define EXT_STATUS_AES4_SLIP 0x00080000 16414ff6a09STakashi Sakamoto #define EXT_STATUS_ADAT_SLIP 0x00100000 16514ff6a09STakashi Sakamoto #define EXT_STATUS_TDIF_SLIP 0x00200000 16614ff6a09STakashi Sakamoto #define EXT_STATUS_ARX1_SLIP 0x00400000 16714ff6a09STakashi Sakamoto #define EXT_STATUS_ARX2_SLIP 0x00800000 16814ff6a09STakashi Sakamoto #define EXT_STATUS_ARX3_SLIP 0x01000000 16914ff6a09STakashi Sakamoto #define EXT_STATUS_ARX4_SLIP 0x02000000 17014ff6a09STakashi Sakamoto #define EXT_STATUS_WC_SLIP 0x04000000 17114ff6a09STakashi Sakamoto 17214ff6a09STakashi Sakamoto /* 17314ff6a09STakashi Sakamoto * The measured rate of the current clock source, in Hz; read-only. 17414ff6a09STakashi Sakamoto */ 17514ff6a09STakashi Sakamoto #define GLOBAL_SAMPLE_RATE 0x05c 17614ff6a09STakashi Sakamoto 17714ff6a09STakashi Sakamoto /* 178*c1a36101STakashi Sakamoto * Some old firmware versions do not have the following global registers. 179*c1a36101STakashi Sakamoto * Windows drivers produced by TCAT lost backward compatibility in its 180*c1a36101STakashi Sakamoto * early release because they can handle firmware only which supports the 181*c1a36101STakashi Sakamoto * following registers. 182*c1a36101STakashi Sakamoto */ 183*c1a36101STakashi Sakamoto 184*c1a36101STakashi Sakamoto /* 18514ff6a09STakashi Sakamoto * The version of the DICE driver specification that this device conforms to; 18614ff6a09STakashi Sakamoto * read-only. 18714ff6a09STakashi Sakamoto */ 18814ff6a09STakashi Sakamoto #define GLOBAL_VERSION 0x060 18914ff6a09STakashi Sakamoto 19014ff6a09STakashi Sakamoto /* 19114ff6a09STakashi Sakamoto * Supported sample rates and clock sources; read-only. 19214ff6a09STakashi Sakamoto */ 19314ff6a09STakashi Sakamoto #define GLOBAL_CLOCK_CAPABILITIES 0x064 19414ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_32000 0x00000001 19514ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_44100 0x00000002 19614ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_48000 0x00000004 19714ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_88200 0x00000008 19814ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_96000 0x00000010 19914ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_176400 0x00000020 20014ff6a09STakashi Sakamoto #define CLOCK_CAP_RATE_192000 0x00000040 20114ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_AES1 0x00010000 20214ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_AES2 0x00020000 20314ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_AES3 0x00040000 20414ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_AES4 0x00080000 20514ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000 20614ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_ADAT 0x00200000 20714ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_TDIF 0x00400000 20814ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_WC 0x00800000 20914ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_ARX1 0x01000000 21014ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_ARX2 0x02000000 21114ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_ARX3 0x04000000 21214ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_ARX4 0x08000000 21314ff6a09STakashi Sakamoto #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000 21414ff6a09STakashi Sakamoto 21514ff6a09STakashi Sakamoto /* 21614ff6a09STakashi Sakamoto * Names of all clock sources; read-only. Quadlets are byte-swapped. Names 21714ff6a09STakashi Sakamoto * are separated with one backslash, the list is terminated with two 21814ff6a09STakashi Sakamoto * backslashes. Unused clock sources are included. 21914ff6a09STakashi Sakamoto */ 22014ff6a09STakashi Sakamoto #define GLOBAL_CLOCK_SOURCE_NAMES 0x068 22114ff6a09STakashi Sakamoto #define CLOCK_SOURCE_NAMES_SIZE 256 22214ff6a09STakashi Sakamoto 22314ff6a09STakashi Sakamoto /* 22414ff6a09STakashi Sakamoto * Capture stream settings. This section includes the number/size registers 22514ff6a09STakashi Sakamoto * and the registers of all streams. 22614ff6a09STakashi Sakamoto */ 22714ff6a09STakashi Sakamoto 22814ff6a09STakashi Sakamoto /* 22914ff6a09STakashi Sakamoto * The number of supported capture streams; read-only. 23014ff6a09STakashi Sakamoto */ 23114ff6a09STakashi Sakamoto #define TX_NUMBER 0x000 23214ff6a09STakashi Sakamoto 23314ff6a09STakashi Sakamoto /* 23414ff6a09STakashi Sakamoto * The size of one stream's register block, in quadlets; read-only. The 23514ff6a09STakashi Sakamoto * registers of the first stream follow immediately afterwards; the registers 23614ff6a09STakashi Sakamoto * of the following streams are offset by this register's value. 23714ff6a09STakashi Sakamoto */ 23814ff6a09STakashi Sakamoto #define TX_SIZE 0x004 23914ff6a09STakashi Sakamoto 24014ff6a09STakashi Sakamoto /* 24114ff6a09STakashi Sakamoto * The isochronous channel number on which packets are sent, or -1 if the 24214ff6a09STakashi Sakamoto * stream is not to be used; read/write. 24314ff6a09STakashi Sakamoto */ 24414ff6a09STakashi Sakamoto #define TX_ISOCHRONOUS 0x008 24514ff6a09STakashi Sakamoto 24614ff6a09STakashi Sakamoto /* 24714ff6a09STakashi Sakamoto * The number of audio channels; read-only. There will be one quadlet per 24814ff6a09STakashi Sakamoto * channel; the first channel is the first quadlet in a data block. 24914ff6a09STakashi Sakamoto */ 25014ff6a09STakashi Sakamoto #define TX_NUMBER_AUDIO 0x00c 25114ff6a09STakashi Sakamoto 25214ff6a09STakashi Sakamoto /* 25314ff6a09STakashi Sakamoto * The number of MIDI ports, 0-8; read-only. If > 0, there will be one 25414ff6a09STakashi Sakamoto * additional quadlet in each data block, following the audio quadlets. 25514ff6a09STakashi Sakamoto */ 25614ff6a09STakashi Sakamoto #define TX_NUMBER_MIDI 0x010 25714ff6a09STakashi Sakamoto 25814ff6a09STakashi Sakamoto /* 25914ff6a09STakashi Sakamoto * The speed at which the packets are sent, SCODE_100-_400; read/write. 260b0e159feSTakashi Sakamoto * SCODE_800 is only available in Dice III. 26114ff6a09STakashi Sakamoto */ 26214ff6a09STakashi Sakamoto #define TX_SPEED 0x014 26314ff6a09STakashi Sakamoto 26414ff6a09STakashi Sakamoto /* 26514ff6a09STakashi Sakamoto * Names of all audio channels; read-only. Quadlets are byte-swapped. Names 26614ff6a09STakashi Sakamoto * are separated with one backslash, the list is terminated with two 26714ff6a09STakashi Sakamoto * backslashes. 26814ff6a09STakashi Sakamoto */ 26914ff6a09STakashi Sakamoto #define TX_NAMES 0x018 27014ff6a09STakashi Sakamoto #define TX_NAMES_SIZE 256 27114ff6a09STakashi Sakamoto 27214ff6a09STakashi Sakamoto /* 27314ff6a09STakashi Sakamoto * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio 27414ff6a09STakashi Sakamoto * channel. 27514ff6a09STakashi Sakamoto */ 27614ff6a09STakashi Sakamoto #define TX_AC3_CAPABILITIES 0x118 27714ff6a09STakashi Sakamoto 27814ff6a09STakashi Sakamoto /* 27914ff6a09STakashi Sakamoto * Send audio data with IEC60958 label; read/write. Bitmask with one bit per 28014ff6a09STakashi Sakamoto * audio channel. This register can be changed even while the stream is 28114ff6a09STakashi Sakamoto * running. 28214ff6a09STakashi Sakamoto */ 28314ff6a09STakashi Sakamoto #define TX_AC3_ENABLE 0x11c 28414ff6a09STakashi Sakamoto 28514ff6a09STakashi Sakamoto /* 28614ff6a09STakashi Sakamoto * Playback stream settings. This section includes the number/size registers 28714ff6a09STakashi Sakamoto * and the registers of all streams. 28814ff6a09STakashi Sakamoto */ 28914ff6a09STakashi Sakamoto 29014ff6a09STakashi Sakamoto /* 29114ff6a09STakashi Sakamoto * The number of supported playback streams; read-only. 29214ff6a09STakashi Sakamoto */ 29314ff6a09STakashi Sakamoto #define RX_NUMBER 0x000 29414ff6a09STakashi Sakamoto 29514ff6a09STakashi Sakamoto /* 29614ff6a09STakashi Sakamoto * The size of one stream's register block, in quadlets; read-only. The 29714ff6a09STakashi Sakamoto * registers of the first stream follow immediately afterwards; the registers 29814ff6a09STakashi Sakamoto * of the following streams are offset by this register's value. 29914ff6a09STakashi Sakamoto */ 30014ff6a09STakashi Sakamoto #define RX_SIZE 0x004 30114ff6a09STakashi Sakamoto 30214ff6a09STakashi Sakamoto /* 30314ff6a09STakashi Sakamoto * The isochronous channel number on which packets are received, or -1 if the 30414ff6a09STakashi Sakamoto * stream is not to be used; read/write. 30514ff6a09STakashi Sakamoto */ 30614ff6a09STakashi Sakamoto #define RX_ISOCHRONOUS 0x008 30714ff6a09STakashi Sakamoto 30814ff6a09STakashi Sakamoto /* 3095b1274efSTakashi Sakamoto * Index of first quadlet to be interpreted; read/write. If > 0, that many 3105b1274efSTakashi Sakamoto * quadlets at the beginning of each data block will be ignored, and all the 3115b1274efSTakashi Sakamoto * audio and MIDI quadlets will follow. 3125b1274efSTakashi Sakamoto */ 3135b1274efSTakashi Sakamoto #define RX_SEQ_START 0x00c 3145b1274efSTakashi Sakamoto 3155b1274efSTakashi Sakamoto /* 31614ff6a09STakashi Sakamoto * The number of audio channels; read-only. There will be one quadlet per 31714ff6a09STakashi Sakamoto * channel. 31814ff6a09STakashi Sakamoto */ 3195b1274efSTakashi Sakamoto #define RX_NUMBER_AUDIO 0x010 32014ff6a09STakashi Sakamoto 32114ff6a09STakashi Sakamoto /* 32214ff6a09STakashi Sakamoto * The number of MIDI ports, 0-8; read-only. If > 0, there will be one 32314ff6a09STakashi Sakamoto * additional quadlet in each data block, following the audio quadlets. 32414ff6a09STakashi Sakamoto */ 3255b1274efSTakashi Sakamoto #define RX_NUMBER_MIDI 0x014 32614ff6a09STakashi Sakamoto 32714ff6a09STakashi Sakamoto /* 32814ff6a09STakashi Sakamoto * Names of all audio channels; read-only. Quadlets are byte-swapped. Names 32914ff6a09STakashi Sakamoto * are separated with one backslash, the list is terminated with two 33014ff6a09STakashi Sakamoto * backslashes. 33114ff6a09STakashi Sakamoto */ 33214ff6a09STakashi Sakamoto #define RX_NAMES 0x018 33314ff6a09STakashi Sakamoto #define RX_NAMES_SIZE 256 33414ff6a09STakashi Sakamoto 33514ff6a09STakashi Sakamoto /* 33614ff6a09STakashi Sakamoto * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio 33714ff6a09STakashi Sakamoto * channel. 33814ff6a09STakashi Sakamoto */ 33914ff6a09STakashi Sakamoto #define RX_AC3_CAPABILITIES 0x118 34014ff6a09STakashi Sakamoto 34114ff6a09STakashi Sakamoto /* 34214ff6a09STakashi Sakamoto * Receive audio data with IEC60958 label; read/write. Bitmask with one bit 34314ff6a09STakashi Sakamoto * per audio channel. This register can be changed even while the stream is 34414ff6a09STakashi Sakamoto * running. 34514ff6a09STakashi Sakamoto */ 34614ff6a09STakashi Sakamoto #define RX_AC3_ENABLE 0x11c 34714ff6a09STakashi Sakamoto 34814ff6a09STakashi Sakamoto /* 34914ff6a09STakashi Sakamoto * Extended synchronization information. 35014ff6a09STakashi Sakamoto * This section can be read completely with a block read request. 35114ff6a09STakashi Sakamoto */ 35214ff6a09STakashi Sakamoto 35314ff6a09STakashi Sakamoto /* 35414ff6a09STakashi Sakamoto * Current clock source; read-only. 35514ff6a09STakashi Sakamoto */ 35614ff6a09STakashi Sakamoto #define EXT_SYNC_CLOCK_SOURCE 0x000 35714ff6a09STakashi Sakamoto 35814ff6a09STakashi Sakamoto /* 35914ff6a09STakashi Sakamoto * Clock source is locked (boolean); read-only. 36014ff6a09STakashi Sakamoto */ 36114ff6a09STakashi Sakamoto #define EXT_SYNC_LOCKED 0x004 36214ff6a09STakashi Sakamoto 36314ff6a09STakashi Sakamoto /* 36414ff6a09STakashi Sakamoto * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or 36514ff6a09STakashi Sakamoto * _NONE; read-only. 36614ff6a09STakashi Sakamoto */ 36714ff6a09STakashi Sakamoto #define EXT_SYNC_RATE 0x008 36814ff6a09STakashi Sakamoto 36914ff6a09STakashi Sakamoto /* 37014ff6a09STakashi Sakamoto * ADAT user data bits; read-only. 37114ff6a09STakashi Sakamoto */ 37214ff6a09STakashi Sakamoto #define EXT_SYNC_ADAT_USER_DATA 0x00c 37314ff6a09STakashi Sakamoto /* The data bits, if available. */ 37414ff6a09STakashi Sakamoto #define ADAT_USER_DATA_MASK 0x0f 37514ff6a09STakashi Sakamoto /* The data bits are not available. */ 37614ff6a09STakashi Sakamoto #define ADAT_USER_DATA_NO_DATA 0x10 37714ff6a09STakashi Sakamoto 37814ff6a09STakashi Sakamoto #endif 379