1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 int quirk; 1138 1139 #ifdef ENABLE_TUNING_CONTROLS 1140 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1141 #endif 1142 /* 1143 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1144 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1145 * things. 1146 */ 1147 bool use_pci_mmio; 1148 void __iomem *mem_base; 1149 1150 /* 1151 * Whether or not to use the alt functions like alt_select_out, 1152 * alt_select_in, etc. Only used on desktop codecs for now, because of 1153 * surround sound support. 1154 */ 1155 bool use_alt_functions; 1156 1157 /* 1158 * Whether or not to use alt controls: volume effect sliders, EQ 1159 * presets, smart volume presets, and new control names with FX prefix. 1160 * Renames PlayEnhancement and CrystalVoice too. 1161 */ 1162 bool use_alt_controls; 1163 }; 1164 1165 /* 1166 * CA0132 quirks table 1167 */ 1168 enum { 1169 QUIRK_NONE, 1170 QUIRK_ALIENWARE, 1171 QUIRK_ALIENWARE_M17XR4, 1172 QUIRK_SBZ, 1173 QUIRK_ZXR, 1174 QUIRK_ZXR_DBPRO, 1175 QUIRK_R3DI, 1176 QUIRK_R3D, 1177 QUIRK_AE5, 1178 QUIRK_AE7, 1179 }; 1180 1181 #ifdef CONFIG_PCI 1182 #define ca0132_quirk(spec) ((spec)->quirk) 1183 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1184 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1185 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1186 #else 1187 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1188 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1190 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1191 #endif 1192 1193 static const struct hda_pintbl alienware_pincfgs[] = { 1194 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1195 { 0x0c, 0x411111f0 }, /* N/A */ 1196 { 0x0d, 0x411111f0 }, /* N/A */ 1197 { 0x0e, 0x411111f0 }, /* N/A */ 1198 { 0x0f, 0x0321101f }, /* HP */ 1199 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1200 { 0x11, 0x03a11021 }, /* Mic */ 1201 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1202 { 0x13, 0x411111f0 }, /* N/A */ 1203 { 0x18, 0x411111f0 }, /* N/A */ 1204 {} 1205 }; 1206 1207 /* Sound Blaster Z pin configs taken from Windows Driver */ 1208 static const struct hda_pintbl sbz_pincfgs[] = { 1209 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1210 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1211 { 0x0d, 0x014510f0 }, /* Digital Out */ 1212 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1213 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1214 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1215 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1216 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1217 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1218 { 0x18, 0x50d000f0 }, /* N/A */ 1219 {} 1220 }; 1221 1222 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1223 static const struct hda_pintbl zxr_pincfgs[] = { 1224 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1225 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1226 { 0x0d, 0x014510f0 }, /* Digital Out */ 1227 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1228 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1229 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1230 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1231 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1232 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1233 { 0x18, 0x50d000f0 }, /* N/A */ 1234 {} 1235 }; 1236 1237 /* Recon3D pin configs taken from Windows Driver */ 1238 static const struct hda_pintbl r3d_pincfgs[] = { 1239 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1240 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1241 { 0x0d, 0x014510f0 }, /* Digital Out */ 1242 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1243 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1244 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1245 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1246 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1247 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1248 { 0x18, 0x50d000f0 }, /* N/A */ 1249 {} 1250 }; 1251 1252 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1253 static const struct hda_pintbl ae5_pincfgs[] = { 1254 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1255 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1256 { 0x0d, 0x014510f0 }, /* Digital Out */ 1257 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1258 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1259 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1260 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1261 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1262 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1263 { 0x18, 0x50d000f0 }, /* N/A */ 1264 {} 1265 }; 1266 1267 /* Recon3D integrated pin configs taken from Windows Driver */ 1268 static const struct hda_pintbl r3di_pincfgs[] = { 1269 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1270 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1271 { 0x0d, 0x014510f0 }, /* Digital Out */ 1272 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1273 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1274 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1275 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1276 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1277 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1278 { 0x18, 0x500000f0 }, /* N/A */ 1279 {} 1280 }; 1281 1282 static const struct hda_pintbl ae7_pincfgs[] = { 1283 { 0x0b, 0x01017010 }, 1284 { 0x0c, 0x014510f0 }, 1285 { 0x0d, 0x414510f0 }, 1286 { 0x0e, 0x01c520f0 }, 1287 { 0x0f, 0x01017114 }, 1288 { 0x10, 0x01017011 }, 1289 { 0x11, 0x018170ff }, 1290 { 0x12, 0x01a170f0 }, 1291 { 0x13, 0x908700f0 }, 1292 { 0x18, 0x500000f0 }, 1293 {} 1294 }; 1295 1296 static const struct snd_pci_quirk ca0132_quirks[] = { 1297 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1298 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1301 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1305 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1315 {} 1316 }; 1317 1318 /* Output selection quirk info structures. */ 1319 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1320 #define MAX_QUIRK_SCP_SET_VALS 2 1321 struct ca0132_alt_out_set_info { 1322 unsigned int dac2port; /* ParamID 0x0d value. */ 1323 1324 bool has_hda_gpio; 1325 char hda_gpio_pin; 1326 char hda_gpio_set; 1327 1328 unsigned int mmio_gpio_count; 1329 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1330 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1331 1332 unsigned int scp_cmds_count; 1333 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1334 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1335 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1336 1337 bool has_chipio_write; 1338 unsigned int chipio_write_addr; 1339 unsigned int chipio_write_data; 1340 }; 1341 1342 struct ca0132_alt_out_set_quirk_data { 1343 int quirk_id; 1344 1345 bool has_headphone_gain; 1346 bool is_ae_series; 1347 1348 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1349 }; 1350 1351 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1352 { .quirk_id = QUIRK_R3DI, 1353 .has_headphone_gain = false, 1354 .is_ae_series = false, 1355 .out_set_info = { 1356 /* Speakers. */ 1357 { .dac2port = 0x24, 1358 .has_hda_gpio = true, 1359 .hda_gpio_pin = 2, 1360 .hda_gpio_set = 1, 1361 .mmio_gpio_count = 0, 1362 .scp_cmds_count = 0, 1363 .has_chipio_write = false, 1364 }, 1365 /* Headphones. */ 1366 { .dac2port = 0x21, 1367 .has_hda_gpio = true, 1368 .hda_gpio_pin = 2, 1369 .hda_gpio_set = 0, 1370 .mmio_gpio_count = 0, 1371 .scp_cmds_count = 0, 1372 .has_chipio_write = false, 1373 } }, 1374 }, 1375 { .quirk_id = QUIRK_R3D, 1376 .has_headphone_gain = false, 1377 .is_ae_series = false, 1378 .out_set_info = { 1379 /* Speakers. */ 1380 { .dac2port = 0x24, 1381 .has_hda_gpio = false, 1382 .mmio_gpio_count = 1, 1383 .mmio_gpio_pin = { 1 }, 1384 .mmio_gpio_set = { 1 }, 1385 .scp_cmds_count = 0, 1386 .has_chipio_write = false, 1387 }, 1388 /* Headphones. */ 1389 { .dac2port = 0x21, 1390 .has_hda_gpio = false, 1391 .mmio_gpio_count = 1, 1392 .mmio_gpio_pin = { 1 }, 1393 .mmio_gpio_set = { 0 }, 1394 .scp_cmds_count = 0, 1395 .has_chipio_write = false, 1396 } }, 1397 }, 1398 { .quirk_id = QUIRK_SBZ, 1399 .has_headphone_gain = false, 1400 .is_ae_series = false, 1401 .out_set_info = { 1402 /* Speakers. */ 1403 { .dac2port = 0x18, 1404 .has_hda_gpio = false, 1405 .mmio_gpio_count = 3, 1406 .mmio_gpio_pin = { 7, 4, 1 }, 1407 .mmio_gpio_set = { 0, 1, 1 }, 1408 .scp_cmds_count = 0, 1409 .has_chipio_write = false, }, 1410 /* Headphones. */ 1411 { .dac2port = 0x12, 1412 .has_hda_gpio = false, 1413 .mmio_gpio_count = 3, 1414 .mmio_gpio_pin = { 7, 4, 1 }, 1415 .mmio_gpio_set = { 1, 1, 0 }, 1416 .scp_cmds_count = 0, 1417 .has_chipio_write = false, 1418 } }, 1419 }, 1420 { .quirk_id = QUIRK_ZXR, 1421 .has_headphone_gain = true, 1422 .is_ae_series = false, 1423 .out_set_info = { 1424 /* Speakers. */ 1425 { .dac2port = 0x24, 1426 .has_hda_gpio = false, 1427 .mmio_gpio_count = 3, 1428 .mmio_gpio_pin = { 2, 3, 5 }, 1429 .mmio_gpio_set = { 1, 1, 0 }, 1430 .scp_cmds_count = 0, 1431 .has_chipio_write = false, 1432 }, 1433 /* Headphones. */ 1434 { .dac2port = 0x21, 1435 .has_hda_gpio = false, 1436 .mmio_gpio_count = 3, 1437 .mmio_gpio_pin = { 2, 3, 5 }, 1438 .mmio_gpio_set = { 0, 1, 1 }, 1439 .scp_cmds_count = 0, 1440 .has_chipio_write = false, 1441 } }, 1442 }, 1443 { .quirk_id = QUIRK_AE5, 1444 .has_headphone_gain = true, 1445 .is_ae_series = true, 1446 .out_set_info = { 1447 /* Speakers. */ 1448 { .dac2port = 0xa4, 1449 .has_hda_gpio = false, 1450 .mmio_gpio_count = 0, 1451 .scp_cmds_count = 2, 1452 .scp_cmd_mid = { 0x96, 0x96 }, 1453 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1454 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1455 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1456 .has_chipio_write = true, 1457 .chipio_write_addr = 0x0018b03c, 1458 .chipio_write_data = 0x00000012 1459 }, 1460 /* Headphones. */ 1461 { .dac2port = 0xa1, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 0, 1464 .scp_cmds_count = 2, 1465 .scp_cmd_mid = { 0x96, 0x96 }, 1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1468 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1469 .has_chipio_write = true, 1470 .chipio_write_addr = 0x0018b03c, 1471 .chipio_write_data = 0x00000012 1472 } }, 1473 }, 1474 { .quirk_id = QUIRK_AE7, 1475 .has_headphone_gain = true, 1476 .is_ae_series = true, 1477 .out_set_info = { 1478 /* Speakers. */ 1479 { .dac2port = 0x58, 1480 .has_hda_gpio = false, 1481 .mmio_gpio_count = 1, 1482 .mmio_gpio_pin = { 0 }, 1483 .mmio_gpio_set = { 1 }, 1484 .scp_cmds_count = 2, 1485 .scp_cmd_mid = { 0x96, 0x96 }, 1486 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1487 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1488 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1489 .has_chipio_write = true, 1490 .chipio_write_addr = 0x0018b03c, 1491 .chipio_write_data = 0x00000000 1492 }, 1493 /* Headphones. */ 1494 { .dac2port = 0x58, 1495 .has_hda_gpio = false, 1496 .mmio_gpio_count = 1, 1497 .mmio_gpio_pin = { 0 }, 1498 .mmio_gpio_set = { 1 }, 1499 .scp_cmds_count = 2, 1500 .scp_cmd_mid = { 0x96, 0x96 }, 1501 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1502 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1503 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1504 .has_chipio_write = true, 1505 .chipio_write_addr = 0x0018b03c, 1506 .chipio_write_data = 0x00000010 1507 } }, 1508 } 1509 }; 1510 1511 /* 1512 * CA0132 codec access 1513 */ 1514 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1515 unsigned int verb, unsigned int parm, unsigned int *res) 1516 { 1517 unsigned int response; 1518 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1519 *res = response; 1520 1521 return ((response == -1) ? -1 : 0); 1522 } 1523 1524 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1525 unsigned short converter_format, unsigned int *res) 1526 { 1527 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1528 converter_format & 0xffff, res); 1529 } 1530 1531 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1532 hda_nid_t nid, unsigned char stream, 1533 unsigned char channel, unsigned int *res) 1534 { 1535 unsigned char converter_stream_channel = 0; 1536 1537 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1538 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1539 converter_stream_channel, res); 1540 } 1541 1542 /* Chip access helper function */ 1543 static int chipio_send(struct hda_codec *codec, 1544 unsigned int reg, 1545 unsigned int data) 1546 { 1547 unsigned int res; 1548 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1549 1550 /* send bits of data specified by reg */ 1551 do { 1552 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1553 reg, data); 1554 if (res == VENDOR_STATUS_CHIPIO_OK) 1555 return 0; 1556 msleep(20); 1557 } while (time_before(jiffies, timeout)); 1558 1559 return -EIO; 1560 } 1561 1562 /* 1563 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1564 */ 1565 static int chipio_write_address(struct hda_codec *codec, 1566 unsigned int chip_addx) 1567 { 1568 struct ca0132_spec *spec = codec->spec; 1569 int res; 1570 1571 if (spec->curr_chip_addx == chip_addx) 1572 return 0; 1573 1574 /* send low 16 bits of the address */ 1575 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1576 chip_addx & 0xffff); 1577 1578 if (res != -EIO) { 1579 /* send high 16 bits of the address */ 1580 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1581 chip_addx >> 16); 1582 } 1583 1584 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1585 1586 return res; 1587 } 1588 1589 /* 1590 * Write data through the vendor widget -- NOT protected by the Mutex! 1591 */ 1592 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1593 { 1594 struct ca0132_spec *spec = codec->spec; 1595 int res; 1596 1597 /* send low 16 bits of the data */ 1598 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1599 1600 if (res != -EIO) { 1601 /* send high 16 bits of the data */ 1602 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1603 data >> 16); 1604 } 1605 1606 /*If no error encountered, automatically increment the address 1607 as per chip behaviour*/ 1608 spec->curr_chip_addx = (res != -EIO) ? 1609 (spec->curr_chip_addx + 4) : ~0U; 1610 return res; 1611 } 1612 1613 /* 1614 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1615 */ 1616 static int chipio_write_data_multiple(struct hda_codec *codec, 1617 const u32 *data, 1618 unsigned int count) 1619 { 1620 int status = 0; 1621 1622 if (data == NULL) { 1623 codec_dbg(codec, "chipio_write_data null ptr\n"); 1624 return -EINVAL; 1625 } 1626 1627 while ((count-- != 0) && (status == 0)) 1628 status = chipio_write_data(codec, *data++); 1629 1630 return status; 1631 } 1632 1633 1634 /* 1635 * Read data through the vendor widget -- NOT protected by the Mutex! 1636 */ 1637 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1638 { 1639 struct ca0132_spec *spec = codec->spec; 1640 int res; 1641 1642 /* post read */ 1643 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1644 1645 if (res != -EIO) { 1646 /* read status */ 1647 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1648 } 1649 1650 if (res != -EIO) { 1651 /* read data */ 1652 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1653 VENDOR_CHIPIO_HIC_READ_DATA, 1654 0); 1655 } 1656 1657 /*If no error encountered, automatically increment the address 1658 as per chip behaviour*/ 1659 spec->curr_chip_addx = (res != -EIO) ? 1660 (spec->curr_chip_addx + 4) : ~0U; 1661 return res; 1662 } 1663 1664 /* 1665 * Write given value to the given address through the chip I/O widget. 1666 * protected by the Mutex 1667 */ 1668 static int chipio_write(struct hda_codec *codec, 1669 unsigned int chip_addx, const unsigned int data) 1670 { 1671 struct ca0132_spec *spec = codec->spec; 1672 int err; 1673 1674 mutex_lock(&spec->chipio_mutex); 1675 1676 /* write the address, and if successful proceed to write data */ 1677 err = chipio_write_address(codec, chip_addx); 1678 if (err < 0) 1679 goto exit; 1680 1681 err = chipio_write_data(codec, data); 1682 if (err < 0) 1683 goto exit; 1684 1685 exit: 1686 mutex_unlock(&spec->chipio_mutex); 1687 return err; 1688 } 1689 1690 /* 1691 * Write given value to the given address through the chip I/O widget. 1692 * not protected by the Mutex 1693 */ 1694 static int chipio_write_no_mutex(struct hda_codec *codec, 1695 unsigned int chip_addx, const unsigned int data) 1696 { 1697 int err; 1698 1699 1700 /* write the address, and if successful proceed to write data */ 1701 err = chipio_write_address(codec, chip_addx); 1702 if (err < 0) 1703 goto exit; 1704 1705 err = chipio_write_data(codec, data); 1706 if (err < 0) 1707 goto exit; 1708 1709 exit: 1710 return err; 1711 } 1712 1713 /* 1714 * Write multiple values to the given address through the chip I/O widget. 1715 * protected by the Mutex 1716 */ 1717 static int chipio_write_multiple(struct hda_codec *codec, 1718 u32 chip_addx, 1719 const u32 *data, 1720 unsigned int count) 1721 { 1722 struct ca0132_spec *spec = codec->spec; 1723 int status; 1724 1725 mutex_lock(&spec->chipio_mutex); 1726 status = chipio_write_address(codec, chip_addx); 1727 if (status < 0) 1728 goto error; 1729 1730 status = chipio_write_data_multiple(codec, data, count); 1731 error: 1732 mutex_unlock(&spec->chipio_mutex); 1733 1734 return status; 1735 } 1736 1737 /* 1738 * Read the given address through the chip I/O widget 1739 * protected by the Mutex 1740 */ 1741 static int chipio_read(struct hda_codec *codec, 1742 unsigned int chip_addx, unsigned int *data) 1743 { 1744 struct ca0132_spec *spec = codec->spec; 1745 int err; 1746 1747 mutex_lock(&spec->chipio_mutex); 1748 1749 /* write the address, and if successful proceed to write data */ 1750 err = chipio_write_address(codec, chip_addx); 1751 if (err < 0) 1752 goto exit; 1753 1754 err = chipio_read_data(codec, data); 1755 if (err < 0) 1756 goto exit; 1757 1758 exit: 1759 mutex_unlock(&spec->chipio_mutex); 1760 return err; 1761 } 1762 1763 /* 1764 * Set chip control flags through the chip I/O widget. 1765 */ 1766 static void chipio_set_control_flag(struct hda_codec *codec, 1767 enum control_flag_id flag_id, 1768 bool flag_state) 1769 { 1770 unsigned int val; 1771 unsigned int flag_bit; 1772 1773 flag_bit = (flag_state ? 1 : 0); 1774 val = (flag_bit << 7) | (flag_id); 1775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1776 VENDOR_CHIPIO_FLAG_SET, val); 1777 } 1778 1779 /* 1780 * Set chip parameters through the chip I/O widget. 1781 */ 1782 static void chipio_set_control_param(struct hda_codec *codec, 1783 enum control_param_id param_id, int param_val) 1784 { 1785 struct ca0132_spec *spec = codec->spec; 1786 int val; 1787 1788 if ((param_id < 32) && (param_val < 8)) { 1789 val = (param_val << 5) | (param_id); 1790 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1791 VENDOR_CHIPIO_PARAM_SET, val); 1792 } else { 1793 mutex_lock(&spec->chipio_mutex); 1794 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1796 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1797 param_id); 1798 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1799 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1800 param_val); 1801 } 1802 mutex_unlock(&spec->chipio_mutex); 1803 } 1804 } 1805 1806 /* 1807 * Set chip parameters through the chip I/O widget. NO MUTEX. 1808 */ 1809 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1810 enum control_param_id param_id, int param_val) 1811 { 1812 int val; 1813 1814 if ((param_id < 32) && (param_val < 8)) { 1815 val = (param_val << 5) | (param_id); 1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1817 VENDOR_CHIPIO_PARAM_SET, val); 1818 } else { 1819 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1820 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1821 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1822 param_id); 1823 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1824 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1825 param_val); 1826 } 1827 } 1828 } 1829 /* 1830 * Connect stream to a source point, and then connect 1831 * that source point to a destination point. 1832 */ 1833 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1834 int streamid, int source_point, int dest_point) 1835 { 1836 chipio_set_control_param_no_mutex(codec, 1837 CONTROL_PARAM_STREAM_ID, streamid); 1838 chipio_set_control_param_no_mutex(codec, 1839 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1840 chipio_set_control_param_no_mutex(codec, 1841 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1842 } 1843 1844 /* 1845 * Set number of channels in the selected stream. 1846 */ 1847 static void chipio_set_stream_channels(struct hda_codec *codec, 1848 int streamid, unsigned int channels) 1849 { 1850 chipio_set_control_param_no_mutex(codec, 1851 CONTROL_PARAM_STREAM_ID, streamid); 1852 chipio_set_control_param_no_mutex(codec, 1853 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1854 } 1855 1856 /* 1857 * Enable/Disable audio stream. 1858 */ 1859 static void chipio_set_stream_control(struct hda_codec *codec, 1860 int streamid, int enable) 1861 { 1862 chipio_set_control_param_no_mutex(codec, 1863 CONTROL_PARAM_STREAM_ID, streamid); 1864 chipio_set_control_param_no_mutex(codec, 1865 CONTROL_PARAM_STREAM_CONTROL, enable); 1866 } 1867 1868 /* 1869 * Get ChipIO audio stream's status. 1870 */ 1871 static void chipio_get_stream_control(struct hda_codec *codec, 1872 int streamid, unsigned int *enable) 1873 { 1874 chipio_set_control_param_no_mutex(codec, 1875 CONTROL_PARAM_STREAM_ID, streamid); 1876 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1877 VENDOR_CHIPIO_PARAM_GET, 1878 CONTROL_PARAM_STREAM_CONTROL); 1879 } 1880 1881 /* 1882 * Set sampling rate of the connection point. NO MUTEX. 1883 */ 1884 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1885 int connid, enum ca0132_sample_rate rate) 1886 { 1887 chipio_set_control_param_no_mutex(codec, 1888 CONTROL_PARAM_CONN_POINT_ID, connid); 1889 chipio_set_control_param_no_mutex(codec, 1890 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1891 } 1892 1893 /* 1894 * Set sampling rate of the connection point. 1895 */ 1896 static void chipio_set_conn_rate(struct hda_codec *codec, 1897 int connid, enum ca0132_sample_rate rate) 1898 { 1899 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1900 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1901 rate); 1902 } 1903 1904 /* 1905 * Writes to the 8051's internal address space directly instead of indirectly, 1906 * giving access to the special function registers located at addresses 1907 * 0x80-0xFF. 1908 */ 1909 static void chipio_8051_write_direct(struct hda_codec *codec, 1910 unsigned int addr, unsigned int data) 1911 { 1912 unsigned int verb; 1913 1914 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1916 } 1917 1918 /* 1919 * Writes to the 8051's exram, which has 16-bits of address space. 1920 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1921 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1922 * setting the pmem bank selection SFR. 1923 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1924 * being writable. 1925 */ 1926 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1927 { 1928 unsigned int tmp; 1929 1930 /* Lower 8-bits. */ 1931 tmp = addr & 0xff; 1932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1933 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1934 1935 /* Upper 8-bits. */ 1936 tmp = (addr >> 8) & 0xff; 1937 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1938 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1939 } 1940 1941 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1942 { 1943 /* 8-bits of data. */ 1944 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1945 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1946 } 1947 1948 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1949 { 1950 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1951 VENDOR_CHIPIO_8051_DATA_READ, 0); 1952 } 1953 1954 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1955 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1956 { 1957 /* 8-bits of data. */ 1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1959 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1960 } 1961 1962 static void chipio_8051_write_exram(struct hda_codec *codec, 1963 unsigned int addr, unsigned int data) 1964 { 1965 struct ca0132_spec *spec = codec->spec; 1966 1967 mutex_lock(&spec->chipio_mutex); 1968 1969 chipio_8051_set_address(codec, addr); 1970 chipio_8051_set_data(codec, data); 1971 1972 mutex_unlock(&spec->chipio_mutex); 1973 } 1974 1975 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1976 unsigned int addr, unsigned int data) 1977 { 1978 chipio_8051_set_address(codec, addr); 1979 chipio_8051_set_data(codec, data); 1980 } 1981 1982 /* Readback data from the 8051's exram. No mutex. */ 1983 static void chipio_8051_read_exram(struct hda_codec *codec, 1984 unsigned int addr, unsigned int *data) 1985 { 1986 chipio_8051_set_address(codec, addr); 1987 *data = chipio_8051_get_data(codec); 1988 } 1989 1990 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 1991 unsigned int addr, unsigned int data) 1992 { 1993 struct ca0132_spec *spec = codec->spec; 1994 1995 mutex_lock(&spec->chipio_mutex); 1996 1997 chipio_8051_set_address(codec, addr & 0xff); 1998 chipio_8051_set_data_pll(codec, data); 1999 2000 mutex_unlock(&spec->chipio_mutex); 2001 } 2002 2003 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2004 unsigned int addr, unsigned int data) 2005 { 2006 chipio_8051_set_address(codec, addr & 0xff); 2007 chipio_8051_set_data_pll(codec, data); 2008 } 2009 2010 /* 2011 * Enable clocks. 2012 */ 2013 static void chipio_enable_clocks(struct hda_codec *codec) 2014 { 2015 struct ca0132_spec *spec = codec->spec; 2016 2017 mutex_lock(&spec->chipio_mutex); 2018 2019 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2020 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2021 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2022 2023 mutex_unlock(&spec->chipio_mutex); 2024 } 2025 2026 /* 2027 * CA0132 DSP IO stuffs 2028 */ 2029 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2030 unsigned int data) 2031 { 2032 int res; 2033 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2034 2035 /* send bits of data specified by reg to dsp */ 2036 do { 2037 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2038 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2039 return res; 2040 msleep(20); 2041 } while (time_before(jiffies, timeout)); 2042 2043 return -EIO; 2044 } 2045 2046 /* 2047 * Wait for DSP to be ready for commands 2048 */ 2049 static void dspio_write_wait(struct hda_codec *codec) 2050 { 2051 int status; 2052 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2053 2054 do { 2055 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2056 VENDOR_DSPIO_STATUS, 0); 2057 if ((status == VENDOR_STATUS_DSPIO_OK) || 2058 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2059 break; 2060 msleep(1); 2061 } while (time_before(jiffies, timeout)); 2062 } 2063 2064 /* 2065 * Write SCP data to DSP 2066 */ 2067 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2068 { 2069 struct ca0132_spec *spec = codec->spec; 2070 int status; 2071 2072 dspio_write_wait(codec); 2073 2074 mutex_lock(&spec->chipio_mutex); 2075 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2076 scp_data & 0xffff); 2077 if (status < 0) 2078 goto error; 2079 2080 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2081 scp_data >> 16); 2082 if (status < 0) 2083 goto error; 2084 2085 /* OK, now check if the write itself has executed*/ 2086 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2087 VENDOR_DSPIO_STATUS, 0); 2088 error: 2089 mutex_unlock(&spec->chipio_mutex); 2090 2091 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2092 -EIO : 0; 2093 } 2094 2095 /* 2096 * Write multiple SCP data to DSP 2097 */ 2098 static int dspio_write_multiple(struct hda_codec *codec, 2099 unsigned int *buffer, unsigned int size) 2100 { 2101 int status = 0; 2102 unsigned int count; 2103 2104 if (buffer == NULL) 2105 return -EINVAL; 2106 2107 count = 0; 2108 while (count < size) { 2109 status = dspio_write(codec, *buffer++); 2110 if (status != 0) 2111 break; 2112 count++; 2113 } 2114 2115 return status; 2116 } 2117 2118 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2119 { 2120 int status; 2121 2122 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2123 if (status == -EIO) 2124 return status; 2125 2126 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2127 if (status == -EIO || 2128 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2129 return -EIO; 2130 2131 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2132 VENDOR_DSPIO_SCP_READ_DATA, 0); 2133 2134 return 0; 2135 } 2136 2137 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2138 unsigned int *buf_size, unsigned int size_count) 2139 { 2140 int status = 0; 2141 unsigned int size = *buf_size; 2142 unsigned int count; 2143 unsigned int skip_count; 2144 unsigned int dummy; 2145 2146 if (buffer == NULL) 2147 return -1; 2148 2149 count = 0; 2150 while (count < size && count < size_count) { 2151 status = dspio_read(codec, buffer++); 2152 if (status != 0) 2153 break; 2154 count++; 2155 } 2156 2157 skip_count = count; 2158 if (status == 0) { 2159 while (skip_count < size) { 2160 status = dspio_read(codec, &dummy); 2161 if (status != 0) 2162 break; 2163 skip_count++; 2164 } 2165 } 2166 *buf_size = count; 2167 2168 return status; 2169 } 2170 2171 /* 2172 * Construct the SCP header using corresponding fields 2173 */ 2174 static inline unsigned int 2175 make_scp_header(unsigned int target_id, unsigned int source_id, 2176 unsigned int get_flag, unsigned int req, 2177 unsigned int device_flag, unsigned int resp_flag, 2178 unsigned int error_flag, unsigned int data_size) 2179 { 2180 unsigned int header = 0; 2181 2182 header = (data_size & 0x1f) << 27; 2183 header |= (error_flag & 0x01) << 26; 2184 header |= (resp_flag & 0x01) << 25; 2185 header |= (device_flag & 0x01) << 24; 2186 header |= (req & 0x7f) << 17; 2187 header |= (get_flag & 0x01) << 16; 2188 header |= (source_id & 0xff) << 8; 2189 header |= target_id & 0xff; 2190 2191 return header; 2192 } 2193 2194 /* 2195 * Extract corresponding fields from SCP header 2196 */ 2197 static inline void 2198 extract_scp_header(unsigned int header, 2199 unsigned int *target_id, unsigned int *source_id, 2200 unsigned int *get_flag, unsigned int *req, 2201 unsigned int *device_flag, unsigned int *resp_flag, 2202 unsigned int *error_flag, unsigned int *data_size) 2203 { 2204 if (data_size) 2205 *data_size = (header >> 27) & 0x1f; 2206 if (error_flag) 2207 *error_flag = (header >> 26) & 0x01; 2208 if (resp_flag) 2209 *resp_flag = (header >> 25) & 0x01; 2210 if (device_flag) 2211 *device_flag = (header >> 24) & 0x01; 2212 if (req) 2213 *req = (header >> 17) & 0x7f; 2214 if (get_flag) 2215 *get_flag = (header >> 16) & 0x01; 2216 if (source_id) 2217 *source_id = (header >> 8) & 0xff; 2218 if (target_id) 2219 *target_id = header & 0xff; 2220 } 2221 2222 #define SCP_MAX_DATA_WORDS (16) 2223 2224 /* Structure to contain any SCP message */ 2225 struct scp_msg { 2226 unsigned int hdr; 2227 unsigned int data[SCP_MAX_DATA_WORDS]; 2228 }; 2229 2230 static void dspio_clear_response_queue(struct hda_codec *codec) 2231 { 2232 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2233 unsigned int dummy = 0; 2234 int status; 2235 2236 /* clear all from the response queue */ 2237 do { 2238 status = dspio_read(codec, &dummy); 2239 } while (status == 0 && time_before(jiffies, timeout)); 2240 } 2241 2242 static int dspio_get_response_data(struct hda_codec *codec) 2243 { 2244 struct ca0132_spec *spec = codec->spec; 2245 unsigned int data = 0; 2246 unsigned int count; 2247 2248 if (dspio_read(codec, &data) < 0) 2249 return -EIO; 2250 2251 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2252 spec->scp_resp_header = data; 2253 spec->scp_resp_count = data >> 27; 2254 count = spec->wait_num_data; 2255 dspio_read_multiple(codec, spec->scp_resp_data, 2256 &spec->scp_resp_count, count); 2257 return 0; 2258 } 2259 2260 return -EIO; 2261 } 2262 2263 /* 2264 * Send SCP message to DSP 2265 */ 2266 static int dspio_send_scp_message(struct hda_codec *codec, 2267 unsigned char *send_buf, 2268 unsigned int send_buf_size, 2269 unsigned char *return_buf, 2270 unsigned int return_buf_size, 2271 unsigned int *bytes_returned) 2272 { 2273 struct ca0132_spec *spec = codec->spec; 2274 int status; 2275 unsigned int scp_send_size = 0; 2276 unsigned int total_size; 2277 bool waiting_for_resp = false; 2278 unsigned int header; 2279 struct scp_msg *ret_msg; 2280 unsigned int resp_src_id, resp_target_id; 2281 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2282 2283 if (bytes_returned) 2284 *bytes_returned = 0; 2285 2286 /* get scp header from buffer */ 2287 header = *((unsigned int *)send_buf); 2288 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2289 &device_flag, NULL, NULL, &data_size); 2290 scp_send_size = data_size + 1; 2291 total_size = (scp_send_size * 4); 2292 2293 if (send_buf_size < total_size) 2294 return -EINVAL; 2295 2296 if (get_flag || device_flag) { 2297 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2298 return -EINVAL; 2299 2300 spec->wait_scp_header = *((unsigned int *)send_buf); 2301 2302 /* swap source id with target id */ 2303 resp_target_id = src_id; 2304 resp_src_id = target_id; 2305 spec->wait_scp_header &= 0xffff0000; 2306 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2307 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2308 spec->wait_scp = 1; 2309 waiting_for_resp = true; 2310 } 2311 2312 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2313 scp_send_size); 2314 if (status < 0) { 2315 spec->wait_scp = 0; 2316 return status; 2317 } 2318 2319 if (waiting_for_resp) { 2320 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2321 memset(return_buf, 0, return_buf_size); 2322 do { 2323 msleep(20); 2324 } while (spec->wait_scp && time_before(jiffies, timeout)); 2325 waiting_for_resp = false; 2326 if (!spec->wait_scp) { 2327 ret_msg = (struct scp_msg *)return_buf; 2328 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2329 memcpy(&ret_msg->data, spec->scp_resp_data, 2330 spec->wait_num_data); 2331 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2332 status = 0; 2333 } else { 2334 status = -EIO; 2335 } 2336 spec->wait_scp = 0; 2337 } 2338 2339 return status; 2340 } 2341 2342 /** 2343 * dspio_scp - Prepare and send the SCP message to DSP 2344 * @codec: the HDA codec 2345 * @mod_id: ID of the DSP module to send the command 2346 * @src_id: ID of the source 2347 * @req: ID of request to send to the DSP module 2348 * @dir: SET or GET 2349 * @data: pointer to the data to send with the request, request specific 2350 * @len: length of the data, in bytes 2351 * @reply: point to the buffer to hold data returned for a reply 2352 * @reply_len: length of the reply buffer returned from GET 2353 * 2354 * Returns zero or a negative error code. 2355 */ 2356 static int dspio_scp(struct hda_codec *codec, 2357 int mod_id, int src_id, int req, int dir, const void *data, 2358 unsigned int len, void *reply, unsigned int *reply_len) 2359 { 2360 int status = 0; 2361 struct scp_msg scp_send, scp_reply; 2362 unsigned int ret_bytes, send_size, ret_size; 2363 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2364 unsigned int reply_data_size; 2365 2366 memset(&scp_send, 0, sizeof(scp_send)); 2367 memset(&scp_reply, 0, sizeof(scp_reply)); 2368 2369 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2370 return -EINVAL; 2371 2372 if (dir == SCP_GET && reply == NULL) { 2373 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2374 return -EINVAL; 2375 } 2376 2377 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2378 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2379 return -EINVAL; 2380 } 2381 2382 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2383 0, 0, 0, len/sizeof(unsigned int)); 2384 if (data != NULL && len > 0) { 2385 len = min((unsigned int)(sizeof(scp_send.data)), len); 2386 memcpy(scp_send.data, data, len); 2387 } 2388 2389 ret_bytes = 0; 2390 send_size = sizeof(unsigned int) + len; 2391 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2392 send_size, (unsigned char *)&scp_reply, 2393 sizeof(scp_reply), &ret_bytes); 2394 2395 if (status < 0) { 2396 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2397 return status; 2398 } 2399 2400 /* extract send and reply headers members */ 2401 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2402 NULL, NULL, NULL, NULL, NULL); 2403 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2404 &reply_resp_flag, &reply_error_flag, 2405 &reply_data_size); 2406 2407 if (!send_get_flag) 2408 return 0; 2409 2410 if (reply_resp_flag && !reply_error_flag) { 2411 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2412 / sizeof(unsigned int); 2413 2414 if (*reply_len < ret_size*sizeof(unsigned int)) { 2415 codec_dbg(codec, "reply too long for buf\n"); 2416 return -EINVAL; 2417 } else if (ret_size != reply_data_size) { 2418 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2419 return -EINVAL; 2420 } else if (!reply) { 2421 codec_dbg(codec, "NULL reply\n"); 2422 return -EINVAL; 2423 } else { 2424 *reply_len = ret_size*sizeof(unsigned int); 2425 memcpy(reply, scp_reply.data, *reply_len); 2426 } 2427 } else { 2428 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2429 return -EIO; 2430 } 2431 2432 return status; 2433 } 2434 2435 /* 2436 * Set DSP parameters 2437 */ 2438 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2439 int src_id, int req, const void *data, unsigned int len) 2440 { 2441 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2442 NULL); 2443 } 2444 2445 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2446 int req, const unsigned int data) 2447 { 2448 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2449 sizeof(unsigned int)); 2450 } 2451 2452 /* 2453 * Allocate a DSP DMA channel via an SCP message 2454 */ 2455 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2456 { 2457 int status = 0; 2458 unsigned int size = sizeof(dma_chan); 2459 2460 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2461 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2462 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2463 dma_chan, &size); 2464 2465 if (status < 0) { 2466 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2467 return status; 2468 } 2469 2470 if ((*dma_chan + 1) == 0) { 2471 codec_dbg(codec, "no free dma channels to allocate\n"); 2472 return -EBUSY; 2473 } 2474 2475 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2476 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2477 2478 return status; 2479 } 2480 2481 /* 2482 * Free a DSP DMA via an SCP message 2483 */ 2484 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2485 { 2486 int status = 0; 2487 unsigned int dummy = 0; 2488 2489 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2490 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2491 2492 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2493 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2494 sizeof(dma_chan), NULL, &dummy); 2495 2496 if (status < 0) { 2497 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2498 return status; 2499 } 2500 2501 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2502 2503 return status; 2504 } 2505 2506 /* 2507 * (Re)start the DSP 2508 */ 2509 static int dsp_set_run_state(struct hda_codec *codec) 2510 { 2511 unsigned int dbg_ctrl_reg; 2512 unsigned int halt_state; 2513 int err; 2514 2515 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2516 if (err < 0) 2517 return err; 2518 2519 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2520 DSP_DBGCNTL_STATE_LOBIT; 2521 2522 if (halt_state != 0) { 2523 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2524 DSP_DBGCNTL_SS_MASK); 2525 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2526 dbg_ctrl_reg); 2527 if (err < 0) 2528 return err; 2529 2530 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2531 DSP_DBGCNTL_EXEC_MASK; 2532 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2533 dbg_ctrl_reg); 2534 if (err < 0) 2535 return err; 2536 } 2537 2538 return 0; 2539 } 2540 2541 /* 2542 * Reset the DSP 2543 */ 2544 static int dsp_reset(struct hda_codec *codec) 2545 { 2546 unsigned int res; 2547 int retry = 20; 2548 2549 codec_dbg(codec, "dsp_reset\n"); 2550 do { 2551 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2552 retry--; 2553 } while (res == -EIO && retry); 2554 2555 if (!retry) { 2556 codec_dbg(codec, "dsp_reset timeout\n"); 2557 return -EIO; 2558 } 2559 2560 return 0; 2561 } 2562 2563 /* 2564 * Convert chip address to DSP address 2565 */ 2566 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2567 bool *code, bool *yram) 2568 { 2569 *code = *yram = false; 2570 2571 if (UC_RANGE(chip_addx, 1)) { 2572 *code = true; 2573 return UC_OFF(chip_addx); 2574 } else if (X_RANGE_ALL(chip_addx, 1)) { 2575 return X_OFF(chip_addx); 2576 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2577 *yram = true; 2578 return Y_OFF(chip_addx); 2579 } 2580 2581 return INVALID_CHIP_ADDRESS; 2582 } 2583 2584 /* 2585 * Check if the DSP DMA is active 2586 */ 2587 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2588 { 2589 unsigned int dma_chnlstart_reg; 2590 2591 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2592 2593 return ((dma_chnlstart_reg & (1 << 2594 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2595 } 2596 2597 static int dsp_dma_setup_common(struct hda_codec *codec, 2598 unsigned int chip_addx, 2599 unsigned int dma_chan, 2600 unsigned int port_map_mask, 2601 bool ovly) 2602 { 2603 int status = 0; 2604 unsigned int chnl_prop; 2605 unsigned int dsp_addx; 2606 unsigned int active; 2607 bool code, yram; 2608 2609 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2610 2611 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2612 codec_dbg(codec, "dma chan num invalid\n"); 2613 return -EINVAL; 2614 } 2615 2616 if (dsp_is_dma_active(codec, dma_chan)) { 2617 codec_dbg(codec, "dma already active\n"); 2618 return -EBUSY; 2619 } 2620 2621 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2622 2623 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2624 codec_dbg(codec, "invalid chip addr\n"); 2625 return -ENXIO; 2626 } 2627 2628 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2629 active = 0; 2630 2631 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2632 2633 if (ovly) { 2634 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2635 &chnl_prop); 2636 2637 if (status < 0) { 2638 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2639 return status; 2640 } 2641 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2642 } 2643 2644 if (!code) 2645 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2646 else 2647 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2648 2649 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2650 2651 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2652 if (status < 0) { 2653 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2654 return status; 2655 } 2656 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2657 2658 if (ovly) { 2659 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2660 &active); 2661 2662 if (status < 0) { 2663 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2664 return status; 2665 } 2666 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2667 } 2668 2669 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2670 DSPDMAC_ACTIVE_AAR_MASK; 2671 2672 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2673 if (status < 0) { 2674 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2675 return status; 2676 } 2677 2678 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2679 2680 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2681 port_map_mask); 2682 if (status < 0) { 2683 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2684 return status; 2685 } 2686 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2687 2688 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2689 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2690 if (status < 0) { 2691 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2692 return status; 2693 } 2694 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2695 2696 codec_dbg(codec, 2697 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2698 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2699 chip_addx, dsp_addx, dma_chan, 2700 port_map_mask, chnl_prop, active); 2701 2702 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2703 2704 return 0; 2705 } 2706 2707 /* 2708 * Setup the DSP DMA per-transfer-specific registers 2709 */ 2710 static int dsp_dma_setup(struct hda_codec *codec, 2711 unsigned int chip_addx, 2712 unsigned int count, 2713 unsigned int dma_chan) 2714 { 2715 int status = 0; 2716 bool code, yram; 2717 unsigned int dsp_addx; 2718 unsigned int addr_field; 2719 unsigned int incr_field; 2720 unsigned int base_cnt; 2721 unsigned int cur_cnt; 2722 unsigned int dma_cfg = 0; 2723 unsigned int adr_ofs = 0; 2724 unsigned int xfr_cnt = 0; 2725 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2726 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2727 2728 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2729 2730 if (count > max_dma_count) { 2731 codec_dbg(codec, "count too big\n"); 2732 return -EINVAL; 2733 } 2734 2735 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2736 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2737 codec_dbg(codec, "invalid chip addr\n"); 2738 return -ENXIO; 2739 } 2740 2741 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2742 2743 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2744 incr_field = 0; 2745 2746 if (!code) { 2747 addr_field <<= 1; 2748 if (yram) 2749 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2750 2751 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2752 } 2753 2754 dma_cfg = addr_field + incr_field; 2755 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2756 dma_cfg); 2757 if (status < 0) { 2758 codec_dbg(codec, "write DMACFG Reg fail\n"); 2759 return status; 2760 } 2761 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2762 2763 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2764 (code ? 0 : 1)); 2765 2766 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2767 adr_ofs); 2768 if (status < 0) { 2769 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2770 return status; 2771 } 2772 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2773 2774 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2775 2776 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2777 2778 xfr_cnt = base_cnt | cur_cnt; 2779 2780 status = chipio_write(codec, 2781 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2782 if (status < 0) { 2783 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2784 return status; 2785 } 2786 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2787 2788 codec_dbg(codec, 2789 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2790 "ADROFS=0x%x, XFRCNT=0x%x\n", 2791 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2792 2793 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2794 2795 return 0; 2796 } 2797 2798 /* 2799 * Start the DSP DMA 2800 */ 2801 static int dsp_dma_start(struct hda_codec *codec, 2802 unsigned int dma_chan, bool ovly) 2803 { 2804 unsigned int reg = 0; 2805 int status = 0; 2806 2807 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2808 2809 if (ovly) { 2810 status = chipio_read(codec, 2811 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2812 2813 if (status < 0) { 2814 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2815 return status; 2816 } 2817 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2818 2819 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2820 DSPDMAC_CHNLSTART_DIS_MASK); 2821 } 2822 2823 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2824 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2825 if (status < 0) { 2826 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2827 return status; 2828 } 2829 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2830 2831 return status; 2832 } 2833 2834 /* 2835 * Stop the DSP DMA 2836 */ 2837 static int dsp_dma_stop(struct hda_codec *codec, 2838 unsigned int dma_chan, bool ovly) 2839 { 2840 unsigned int reg = 0; 2841 int status = 0; 2842 2843 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2844 2845 if (ovly) { 2846 status = chipio_read(codec, 2847 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2848 2849 if (status < 0) { 2850 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2851 return status; 2852 } 2853 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2854 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2855 DSPDMAC_CHNLSTART_DIS_MASK); 2856 } 2857 2858 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2859 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2860 if (status < 0) { 2861 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2862 return status; 2863 } 2864 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2865 2866 return status; 2867 } 2868 2869 /** 2870 * dsp_allocate_router_ports - Allocate router ports 2871 * 2872 * @codec: the HDA codec 2873 * @num_chans: number of channels in the stream 2874 * @ports_per_channel: number of ports per channel 2875 * @start_device: start device 2876 * @port_map: pointer to the port list to hold the allocated ports 2877 * 2878 * Returns zero or a negative error code. 2879 */ 2880 static int dsp_allocate_router_ports(struct hda_codec *codec, 2881 unsigned int num_chans, 2882 unsigned int ports_per_channel, 2883 unsigned int start_device, 2884 unsigned int *port_map) 2885 { 2886 int status = 0; 2887 int res; 2888 u8 val; 2889 2890 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2891 if (status < 0) 2892 return status; 2893 2894 val = start_device << 6; 2895 val |= (ports_per_channel - 1) << 4; 2896 val |= num_chans - 1; 2897 2898 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2899 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2900 val); 2901 2902 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2903 VENDOR_CHIPIO_PORT_ALLOC_SET, 2904 MEM_CONNID_DSP); 2905 2906 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2907 if (status < 0) 2908 return status; 2909 2910 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2911 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2912 2913 *port_map = res; 2914 2915 return (res < 0) ? res : 0; 2916 } 2917 2918 /* 2919 * Free router ports 2920 */ 2921 static int dsp_free_router_ports(struct hda_codec *codec) 2922 { 2923 int status = 0; 2924 2925 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2926 if (status < 0) 2927 return status; 2928 2929 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2930 VENDOR_CHIPIO_PORT_FREE_SET, 2931 MEM_CONNID_DSP); 2932 2933 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2934 2935 return status; 2936 } 2937 2938 /* 2939 * Allocate DSP ports for the download stream 2940 */ 2941 static int dsp_allocate_ports(struct hda_codec *codec, 2942 unsigned int num_chans, 2943 unsigned int rate_multi, unsigned int *port_map) 2944 { 2945 int status; 2946 2947 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2948 2949 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2950 codec_dbg(codec, "bad rate multiple\n"); 2951 return -EINVAL; 2952 } 2953 2954 status = dsp_allocate_router_ports(codec, num_chans, 2955 rate_multi, 0, port_map); 2956 2957 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2958 2959 return status; 2960 } 2961 2962 static int dsp_allocate_ports_format(struct hda_codec *codec, 2963 const unsigned short fmt, 2964 unsigned int *port_map) 2965 { 2966 unsigned int num_chans; 2967 2968 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2969 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2970 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2971 2972 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2973 codec_dbg(codec, "bad rate multiple\n"); 2974 return -EINVAL; 2975 } 2976 2977 num_chans = get_hdafmt_chs(fmt) + 1; 2978 2979 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2980 } 2981 2982 /* 2983 * free DSP ports 2984 */ 2985 static int dsp_free_ports(struct hda_codec *codec) 2986 { 2987 int status; 2988 2989 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2990 2991 status = dsp_free_router_ports(codec); 2992 if (status < 0) { 2993 codec_dbg(codec, "free router ports fail\n"); 2994 return status; 2995 } 2996 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2997 2998 return status; 2999 } 3000 3001 /* 3002 * HDA DMA engine stuffs for DSP code download 3003 */ 3004 struct dma_engine { 3005 struct hda_codec *codec; 3006 unsigned short m_converter_format; 3007 struct snd_dma_buffer *dmab; 3008 unsigned int buf_size; 3009 }; 3010 3011 3012 enum dma_state { 3013 DMA_STATE_STOP = 0, 3014 DMA_STATE_RUN = 1 3015 }; 3016 3017 static int dma_convert_to_hda_format(struct hda_codec *codec, 3018 unsigned int sample_rate, 3019 unsigned short channels, 3020 unsigned short *hda_format) 3021 { 3022 unsigned int format_val; 3023 3024 format_val = snd_hdac_calc_stream_format(sample_rate, 3025 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 3026 3027 if (hda_format) 3028 *hda_format = (unsigned short)format_val; 3029 3030 return 0; 3031 } 3032 3033 /* 3034 * Reset DMA for DSP download 3035 */ 3036 static int dma_reset(struct dma_engine *dma) 3037 { 3038 struct hda_codec *codec = dma->codec; 3039 struct ca0132_spec *spec = codec->spec; 3040 int status; 3041 3042 if (dma->dmab->area) 3043 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3044 3045 status = snd_hda_codec_load_dsp_prepare(codec, 3046 dma->m_converter_format, 3047 dma->buf_size, 3048 dma->dmab); 3049 if (status < 0) 3050 return status; 3051 spec->dsp_stream_id = status; 3052 return 0; 3053 } 3054 3055 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3056 { 3057 bool cmd; 3058 3059 switch (state) { 3060 case DMA_STATE_STOP: 3061 cmd = false; 3062 break; 3063 case DMA_STATE_RUN: 3064 cmd = true; 3065 break; 3066 default: 3067 return 0; 3068 } 3069 3070 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3071 return 0; 3072 } 3073 3074 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3075 { 3076 return dma->dmab->bytes; 3077 } 3078 3079 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3080 { 3081 return dma->dmab->area; 3082 } 3083 3084 static int dma_xfer(struct dma_engine *dma, 3085 const unsigned int *data, 3086 unsigned int count) 3087 { 3088 memcpy(dma->dmab->area, data, count); 3089 return 0; 3090 } 3091 3092 static void dma_get_converter_format( 3093 struct dma_engine *dma, 3094 unsigned short *format) 3095 { 3096 if (format) 3097 *format = dma->m_converter_format; 3098 } 3099 3100 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3101 { 3102 struct ca0132_spec *spec = dma->codec->spec; 3103 3104 return spec->dsp_stream_id; 3105 } 3106 3107 struct dsp_image_seg { 3108 u32 magic; 3109 u32 chip_addr; 3110 u32 count; 3111 u32 data[]; 3112 }; 3113 3114 static const u32 g_magic_value = 0x4c46584d; 3115 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3116 3117 static bool is_valid(const struct dsp_image_seg *p) 3118 { 3119 return p->magic == g_magic_value; 3120 } 3121 3122 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3123 { 3124 return g_chip_addr_magic_value == p->chip_addr; 3125 } 3126 3127 static bool is_last(const struct dsp_image_seg *p) 3128 { 3129 return p->count == 0; 3130 } 3131 3132 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3133 { 3134 return struct_size(p, data, p->count); 3135 } 3136 3137 static const struct dsp_image_seg *get_next_seg_ptr( 3138 const struct dsp_image_seg *p) 3139 { 3140 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3141 } 3142 3143 /* 3144 * CA0132 chip DSP transfer stuffs. For DSP download. 3145 */ 3146 #define INVALID_DMA_CHANNEL (~0U) 3147 3148 /* 3149 * Program a list of address/data pairs via the ChipIO widget. 3150 * The segment data is in the format of successive pairs of words. 3151 * These are repeated as indicated by the segment's count field. 3152 */ 3153 static int dspxfr_hci_write(struct hda_codec *codec, 3154 const struct dsp_image_seg *fls) 3155 { 3156 int status; 3157 const u32 *data; 3158 unsigned int count; 3159 3160 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3161 codec_dbg(codec, "hci_write invalid params\n"); 3162 return -EINVAL; 3163 } 3164 3165 count = fls->count; 3166 data = (u32 *)(fls->data); 3167 while (count >= 2) { 3168 status = chipio_write(codec, data[0], data[1]); 3169 if (status < 0) { 3170 codec_dbg(codec, "hci_write chipio failed\n"); 3171 return status; 3172 } 3173 count -= 2; 3174 data += 2; 3175 } 3176 return 0; 3177 } 3178 3179 /** 3180 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3181 * 3182 * @codec: the HDA codec 3183 * @fls: pointer to a fast load image 3184 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3185 * no relocation 3186 * @dma_engine: pointer to DMA engine to be used for DSP download 3187 * @dma_chan: The number of DMA channels used for DSP download 3188 * @port_map_mask: port mapping 3189 * @ovly: TRUE if overlay format is required 3190 * 3191 * Returns zero or a negative error code. 3192 */ 3193 static int dspxfr_one_seg(struct hda_codec *codec, 3194 const struct dsp_image_seg *fls, 3195 unsigned int reloc, 3196 struct dma_engine *dma_engine, 3197 unsigned int dma_chan, 3198 unsigned int port_map_mask, 3199 bool ovly) 3200 { 3201 int status = 0; 3202 bool comm_dma_setup_done = false; 3203 const unsigned int *data; 3204 unsigned int chip_addx; 3205 unsigned int words_to_write; 3206 unsigned int buffer_size_words; 3207 unsigned char *buffer_addx; 3208 unsigned short hda_format; 3209 unsigned int sample_rate_div; 3210 unsigned int sample_rate_mul; 3211 unsigned int num_chans; 3212 unsigned int hda_frame_size_words; 3213 unsigned int remainder_words; 3214 const u32 *data_remainder; 3215 u32 chip_addx_remainder; 3216 unsigned int run_size_words; 3217 const struct dsp_image_seg *hci_write = NULL; 3218 unsigned long timeout; 3219 bool dma_active; 3220 3221 if (fls == NULL) 3222 return -EINVAL; 3223 if (is_hci_prog_list_seg(fls)) { 3224 hci_write = fls; 3225 fls = get_next_seg_ptr(fls); 3226 } 3227 3228 if (hci_write && (!fls || is_last(fls))) { 3229 codec_dbg(codec, "hci_write\n"); 3230 return dspxfr_hci_write(codec, hci_write); 3231 } 3232 3233 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3234 codec_dbg(codec, "Invalid Params\n"); 3235 return -EINVAL; 3236 } 3237 3238 data = fls->data; 3239 chip_addx = fls->chip_addr; 3240 words_to_write = fls->count; 3241 3242 if (!words_to_write) 3243 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3244 if (reloc) 3245 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3246 3247 if (!UC_RANGE(chip_addx, words_to_write) && 3248 !X_RANGE_ALL(chip_addx, words_to_write) && 3249 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3250 codec_dbg(codec, "Invalid chip_addx Params\n"); 3251 return -EINVAL; 3252 } 3253 3254 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3255 sizeof(u32); 3256 3257 buffer_addx = dma_get_buffer_addr(dma_engine); 3258 3259 if (buffer_addx == NULL) { 3260 codec_dbg(codec, "dma_engine buffer NULL\n"); 3261 return -EINVAL; 3262 } 3263 3264 dma_get_converter_format(dma_engine, &hda_format); 3265 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3266 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3267 num_chans = get_hdafmt_chs(hda_format) + 1; 3268 3269 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3270 (num_chans * sample_rate_mul / sample_rate_div)); 3271 3272 if (hda_frame_size_words == 0) { 3273 codec_dbg(codec, "frmsz zero\n"); 3274 return -EINVAL; 3275 } 3276 3277 buffer_size_words = min(buffer_size_words, 3278 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3279 65536 : 32768)); 3280 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3281 codec_dbg(codec, 3282 "chpadr=0x%08x frmsz=%u nchan=%u " 3283 "rate_mul=%u div=%u bufsz=%u\n", 3284 chip_addx, hda_frame_size_words, num_chans, 3285 sample_rate_mul, sample_rate_div, buffer_size_words); 3286 3287 if (buffer_size_words < hda_frame_size_words) { 3288 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3289 return -EINVAL; 3290 } 3291 3292 remainder_words = words_to_write % hda_frame_size_words; 3293 data_remainder = data; 3294 chip_addx_remainder = chip_addx; 3295 3296 data += remainder_words; 3297 chip_addx += remainder_words*sizeof(u32); 3298 words_to_write -= remainder_words; 3299 3300 while (words_to_write != 0) { 3301 run_size_words = min(buffer_size_words, words_to_write); 3302 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3303 words_to_write, run_size_words, remainder_words); 3304 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3305 if (!comm_dma_setup_done) { 3306 status = dsp_dma_stop(codec, dma_chan, ovly); 3307 if (status < 0) 3308 return status; 3309 status = dsp_dma_setup_common(codec, chip_addx, 3310 dma_chan, port_map_mask, ovly); 3311 if (status < 0) 3312 return status; 3313 comm_dma_setup_done = true; 3314 } 3315 3316 status = dsp_dma_setup(codec, chip_addx, 3317 run_size_words, dma_chan); 3318 if (status < 0) 3319 return status; 3320 status = dsp_dma_start(codec, dma_chan, ovly); 3321 if (status < 0) 3322 return status; 3323 if (!dsp_is_dma_active(codec, dma_chan)) { 3324 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3325 return -EIO; 3326 } 3327 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3328 if (status < 0) 3329 return status; 3330 if (remainder_words != 0) { 3331 status = chipio_write_multiple(codec, 3332 chip_addx_remainder, 3333 data_remainder, 3334 remainder_words); 3335 if (status < 0) 3336 return status; 3337 remainder_words = 0; 3338 } 3339 if (hci_write) { 3340 status = dspxfr_hci_write(codec, hci_write); 3341 if (status < 0) 3342 return status; 3343 hci_write = NULL; 3344 } 3345 3346 timeout = jiffies + msecs_to_jiffies(2000); 3347 do { 3348 dma_active = dsp_is_dma_active(codec, dma_chan); 3349 if (!dma_active) 3350 break; 3351 msleep(20); 3352 } while (time_before(jiffies, timeout)); 3353 if (dma_active) 3354 break; 3355 3356 codec_dbg(codec, "+++++ DMA complete\n"); 3357 dma_set_state(dma_engine, DMA_STATE_STOP); 3358 status = dma_reset(dma_engine); 3359 3360 if (status < 0) 3361 return status; 3362 3363 data += run_size_words; 3364 chip_addx += run_size_words*sizeof(u32); 3365 words_to_write -= run_size_words; 3366 } 3367 3368 if (remainder_words != 0) { 3369 status = chipio_write_multiple(codec, chip_addx_remainder, 3370 data_remainder, remainder_words); 3371 } 3372 3373 return status; 3374 } 3375 3376 /** 3377 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3378 * 3379 * @codec: the HDA codec 3380 * @fls_data: pointer to a fast load image 3381 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3382 * no relocation 3383 * @sample_rate: sampling rate of the stream used for DSP download 3384 * @channels: channels of the stream used for DSP download 3385 * @ovly: TRUE if overlay format is required 3386 * 3387 * Returns zero or a negative error code. 3388 */ 3389 static int dspxfr_image(struct hda_codec *codec, 3390 const struct dsp_image_seg *fls_data, 3391 unsigned int reloc, 3392 unsigned int sample_rate, 3393 unsigned short channels, 3394 bool ovly) 3395 { 3396 struct ca0132_spec *spec = codec->spec; 3397 int status; 3398 unsigned short hda_format = 0; 3399 unsigned int response; 3400 unsigned char stream_id = 0; 3401 struct dma_engine *dma_engine; 3402 unsigned int dma_chan; 3403 unsigned int port_map_mask; 3404 3405 if (fls_data == NULL) 3406 return -EINVAL; 3407 3408 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3409 if (!dma_engine) 3410 return -ENOMEM; 3411 3412 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3413 if (!dma_engine->dmab) { 3414 kfree(dma_engine); 3415 return -ENOMEM; 3416 } 3417 3418 dma_engine->codec = codec; 3419 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3420 dma_engine->m_converter_format = hda_format; 3421 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3422 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3423 3424 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3425 3426 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3427 hda_format, &response); 3428 3429 if (status < 0) { 3430 codec_dbg(codec, "set converter format fail\n"); 3431 goto exit; 3432 } 3433 3434 status = snd_hda_codec_load_dsp_prepare(codec, 3435 dma_engine->m_converter_format, 3436 dma_engine->buf_size, 3437 dma_engine->dmab); 3438 if (status < 0) 3439 goto exit; 3440 spec->dsp_stream_id = status; 3441 3442 if (ovly) { 3443 status = dspio_alloc_dma_chan(codec, &dma_chan); 3444 if (status < 0) { 3445 codec_dbg(codec, "alloc dmachan fail\n"); 3446 dma_chan = INVALID_DMA_CHANNEL; 3447 goto exit; 3448 } 3449 } 3450 3451 port_map_mask = 0; 3452 status = dsp_allocate_ports_format(codec, hda_format, 3453 &port_map_mask); 3454 if (status < 0) { 3455 codec_dbg(codec, "alloc ports fail\n"); 3456 goto exit; 3457 } 3458 3459 stream_id = dma_get_stream_id(dma_engine); 3460 status = codec_set_converter_stream_channel(codec, 3461 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3462 if (status < 0) { 3463 codec_dbg(codec, "set stream chan fail\n"); 3464 goto exit; 3465 } 3466 3467 while ((fls_data != NULL) && !is_last(fls_data)) { 3468 if (!is_valid(fls_data)) { 3469 codec_dbg(codec, "FLS check fail\n"); 3470 status = -EINVAL; 3471 goto exit; 3472 } 3473 status = dspxfr_one_seg(codec, fls_data, reloc, 3474 dma_engine, dma_chan, 3475 port_map_mask, ovly); 3476 if (status < 0) 3477 break; 3478 3479 if (is_hci_prog_list_seg(fls_data)) 3480 fls_data = get_next_seg_ptr(fls_data); 3481 3482 if ((fls_data != NULL) && !is_last(fls_data)) 3483 fls_data = get_next_seg_ptr(fls_data); 3484 } 3485 3486 if (port_map_mask != 0) 3487 status = dsp_free_ports(codec); 3488 3489 if (status < 0) 3490 goto exit; 3491 3492 status = codec_set_converter_stream_channel(codec, 3493 WIDGET_CHIP_CTRL, 0, 0, &response); 3494 3495 exit: 3496 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3497 dspio_free_dma_chan(codec, dma_chan); 3498 3499 if (dma_engine->dmab->area) 3500 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3501 kfree(dma_engine->dmab); 3502 kfree(dma_engine); 3503 3504 return status; 3505 } 3506 3507 /* 3508 * CA0132 DSP download stuffs. 3509 */ 3510 static void dspload_post_setup(struct hda_codec *codec) 3511 { 3512 struct ca0132_spec *spec = codec->spec; 3513 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3514 if (!ca0132_use_alt_functions(spec)) { 3515 /*set DSP speaker to 2.0 configuration*/ 3516 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3517 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3518 3519 /*update write pointer*/ 3520 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3521 } 3522 } 3523 3524 /** 3525 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3526 * 3527 * @codec: the HDA codec 3528 * @fls: pointer to a fast load image 3529 * @ovly: TRUE if overlay format is required 3530 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3531 * no relocation 3532 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3533 * @router_chans: number of audio router channels to be allocated (0 means use 3534 * internal defaults; max is 32) 3535 * 3536 * Download DSP from a DSP Image Fast Load structure. This structure is a 3537 * linear, non-constant sized element array of structures, each of which 3538 * contain the count of the data to be loaded, the data itself, and the 3539 * corresponding starting chip address of the starting data location. 3540 * Returns zero or a negative error code. 3541 */ 3542 static int dspload_image(struct hda_codec *codec, 3543 const struct dsp_image_seg *fls, 3544 bool ovly, 3545 unsigned int reloc, 3546 bool autostart, 3547 int router_chans) 3548 { 3549 int status = 0; 3550 unsigned int sample_rate; 3551 unsigned short channels; 3552 3553 codec_dbg(codec, "---- dspload_image begin ------\n"); 3554 if (router_chans == 0) { 3555 if (!ovly) 3556 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3557 else 3558 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3559 } 3560 3561 sample_rate = 48000; 3562 channels = (unsigned short)router_chans; 3563 3564 while (channels > 16) { 3565 sample_rate *= 2; 3566 channels /= 2; 3567 } 3568 3569 do { 3570 codec_dbg(codec, "Ready to program DMA\n"); 3571 if (!ovly) 3572 status = dsp_reset(codec); 3573 3574 if (status < 0) 3575 break; 3576 3577 codec_dbg(codec, "dsp_reset() complete\n"); 3578 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3579 ovly); 3580 3581 if (status < 0) 3582 break; 3583 3584 codec_dbg(codec, "dspxfr_image() complete\n"); 3585 if (autostart && !ovly) { 3586 dspload_post_setup(codec); 3587 status = dsp_set_run_state(codec); 3588 } 3589 3590 codec_dbg(codec, "LOAD FINISHED\n"); 3591 } while (0); 3592 3593 return status; 3594 } 3595 3596 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3597 static bool dspload_is_loaded(struct hda_codec *codec) 3598 { 3599 unsigned int data = 0; 3600 int status = 0; 3601 3602 status = chipio_read(codec, 0x40004, &data); 3603 if ((status < 0) || (data != 1)) 3604 return false; 3605 3606 return true; 3607 } 3608 #else 3609 #define dspload_is_loaded(codec) false 3610 #endif 3611 3612 static bool dspload_wait_loaded(struct hda_codec *codec) 3613 { 3614 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3615 3616 do { 3617 if (dspload_is_loaded(codec)) { 3618 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3619 return true; 3620 } 3621 msleep(20); 3622 } while (time_before(jiffies, timeout)); 3623 3624 codec_err(codec, "ca0132 failed to download DSP\n"); 3625 return false; 3626 } 3627 3628 /* 3629 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3630 * based cards, and has a second mmio region, region2, that's used for special 3631 * commands. 3632 */ 3633 3634 /* 3635 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3636 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3637 * The first eight bits are just the number of the pin. So far, I've only seen 3638 * this number go to 7. 3639 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3640 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3641 * then off to send that bit. 3642 */ 3643 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3644 bool enable) 3645 { 3646 struct ca0132_spec *spec = codec->spec; 3647 unsigned short gpio_data; 3648 3649 gpio_data = gpio_pin & 0xF; 3650 gpio_data |= ((enable << 8) & 0x100); 3651 3652 writew(gpio_data, spec->mem_base + 0x320); 3653 } 3654 3655 /* 3656 * Special pci region2 commands that are only used by the AE-5. They follow 3657 * a set format, and require reads at certain points to seemingly 'clear' 3658 * the response data. My first tests didn't do these reads, and would cause 3659 * the card to get locked up until the memory was read. These commands 3660 * seem to work with three distinct values that I've taken to calling group, 3661 * target-id, and value. 3662 */ 3663 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3664 unsigned int target, unsigned int value) 3665 { 3666 struct ca0132_spec *spec = codec->spec; 3667 unsigned int write_val; 3668 3669 writel(0x0000007e, spec->mem_base + 0x210); 3670 readl(spec->mem_base + 0x210); 3671 writel(0x0000005a, spec->mem_base + 0x210); 3672 readl(spec->mem_base + 0x210); 3673 readl(spec->mem_base + 0x210); 3674 3675 writel(0x00800005, spec->mem_base + 0x20c); 3676 writel(group, spec->mem_base + 0x804); 3677 3678 writel(0x00800005, spec->mem_base + 0x20c); 3679 write_val = (target & 0xff); 3680 write_val |= (value << 8); 3681 3682 3683 writel(write_val, spec->mem_base + 0x204); 3684 /* 3685 * Need delay here or else it goes too fast and works inconsistently. 3686 */ 3687 msleep(20); 3688 3689 readl(spec->mem_base + 0x860); 3690 readl(spec->mem_base + 0x854); 3691 readl(spec->mem_base + 0x840); 3692 3693 writel(0x00800004, spec->mem_base + 0x20c); 3694 writel(0x00000000, spec->mem_base + 0x210); 3695 readl(spec->mem_base + 0x210); 3696 readl(spec->mem_base + 0x210); 3697 } 3698 3699 /* 3700 * This second type of command is used for setting the sound filter type. 3701 */ 3702 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3703 unsigned int group, unsigned int target, unsigned int value) 3704 { 3705 struct ca0132_spec *spec = codec->spec; 3706 unsigned int write_val; 3707 3708 writel(0x0000007e, spec->mem_base + 0x210); 3709 readl(spec->mem_base + 0x210); 3710 writel(0x0000005a, spec->mem_base + 0x210); 3711 readl(spec->mem_base + 0x210); 3712 readl(spec->mem_base + 0x210); 3713 3714 writel(0x00800003, spec->mem_base + 0x20c); 3715 writel(group, spec->mem_base + 0x804); 3716 3717 writel(0x00800005, spec->mem_base + 0x20c); 3718 write_val = (target & 0xff); 3719 write_val |= (value << 8); 3720 3721 3722 writel(write_val, spec->mem_base + 0x204); 3723 msleep(20); 3724 readl(spec->mem_base + 0x860); 3725 readl(spec->mem_base + 0x854); 3726 readl(spec->mem_base + 0x840); 3727 3728 writel(0x00800004, spec->mem_base + 0x20c); 3729 writel(0x00000000, spec->mem_base + 0x210); 3730 readl(spec->mem_base + 0x210); 3731 readl(spec->mem_base + 0x210); 3732 } 3733 3734 /* 3735 * Setup GPIO for the other variants of Core3D. 3736 */ 3737 3738 /* 3739 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3740 * the card shows as having no GPIO pins. 3741 */ 3742 static void ca0132_gpio_init(struct hda_codec *codec) 3743 { 3744 struct ca0132_spec *spec = codec->spec; 3745 3746 switch (ca0132_quirk(spec)) { 3747 case QUIRK_SBZ: 3748 case QUIRK_AE5: 3749 case QUIRK_AE7: 3750 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3751 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3752 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3753 break; 3754 case QUIRK_R3DI: 3755 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3756 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3757 break; 3758 default: 3759 break; 3760 } 3761 3762 } 3763 3764 /* Sets the GPIO for audio output. */ 3765 static void ca0132_gpio_setup(struct hda_codec *codec) 3766 { 3767 struct ca0132_spec *spec = codec->spec; 3768 3769 switch (ca0132_quirk(spec)) { 3770 case QUIRK_SBZ: 3771 snd_hda_codec_write(codec, 0x01, 0, 3772 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3773 snd_hda_codec_write(codec, 0x01, 0, 3774 AC_VERB_SET_GPIO_MASK, 0x07); 3775 snd_hda_codec_write(codec, 0x01, 0, 3776 AC_VERB_SET_GPIO_DATA, 0x04); 3777 snd_hda_codec_write(codec, 0x01, 0, 3778 AC_VERB_SET_GPIO_DATA, 0x06); 3779 break; 3780 case QUIRK_R3DI: 3781 snd_hda_codec_write(codec, 0x01, 0, 3782 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3783 snd_hda_codec_write(codec, 0x01, 0, 3784 AC_VERB_SET_GPIO_MASK, 0x1F); 3785 snd_hda_codec_write(codec, 0x01, 0, 3786 AC_VERB_SET_GPIO_DATA, 0x0C); 3787 break; 3788 default: 3789 break; 3790 } 3791 } 3792 3793 /* 3794 * GPIO control functions for the Recon3D integrated. 3795 */ 3796 3797 enum r3di_gpio_bit { 3798 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3799 R3DI_MIC_SELECT_BIT = 1, 3800 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3801 R3DI_OUT_SELECT_BIT = 2, 3802 /* 3803 * I dunno what this actually does, but it stays on until the dsp 3804 * is downloaded. 3805 */ 3806 R3DI_GPIO_DSP_DOWNLOADING = 3, 3807 /* 3808 * Same as above, no clue what it does, but it comes on after the dsp 3809 * is downloaded. 3810 */ 3811 R3DI_GPIO_DSP_DOWNLOADED = 4 3812 }; 3813 3814 enum r3di_mic_select { 3815 /* Set GPIO bit 1 to 0 for rear mic */ 3816 R3DI_REAR_MIC = 0, 3817 /* Set GPIO bit 1 to 1 for front microphone*/ 3818 R3DI_FRONT_MIC = 1 3819 }; 3820 3821 enum r3di_out_select { 3822 /* Set GPIO bit 2 to 0 for headphone */ 3823 R3DI_HEADPHONE_OUT = 0, 3824 /* Set GPIO bit 2 to 1 for speaker */ 3825 R3DI_LINE_OUT = 1 3826 }; 3827 enum r3di_dsp_status { 3828 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3829 R3DI_DSP_DOWNLOADING = 0, 3830 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3831 R3DI_DSP_DOWNLOADED = 1 3832 }; 3833 3834 3835 static void r3di_gpio_mic_set(struct hda_codec *codec, 3836 enum r3di_mic_select cur_mic) 3837 { 3838 unsigned int cur_gpio; 3839 3840 /* Get the current GPIO Data setup */ 3841 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3842 3843 switch (cur_mic) { 3844 case R3DI_REAR_MIC: 3845 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3846 break; 3847 case R3DI_FRONT_MIC: 3848 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3849 break; 3850 } 3851 snd_hda_codec_write(codec, codec->core.afg, 0, 3852 AC_VERB_SET_GPIO_DATA, cur_gpio); 3853 } 3854 3855 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3856 enum r3di_dsp_status dsp_status) 3857 { 3858 unsigned int cur_gpio; 3859 3860 /* Get the current GPIO Data setup */ 3861 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3862 3863 switch (dsp_status) { 3864 case R3DI_DSP_DOWNLOADING: 3865 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3866 snd_hda_codec_write(codec, codec->core.afg, 0, 3867 AC_VERB_SET_GPIO_DATA, cur_gpio); 3868 break; 3869 case R3DI_DSP_DOWNLOADED: 3870 /* Set DOWNLOADING bit to 0. */ 3871 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3872 3873 snd_hda_codec_write(codec, codec->core.afg, 0, 3874 AC_VERB_SET_GPIO_DATA, cur_gpio); 3875 3876 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3877 break; 3878 } 3879 3880 snd_hda_codec_write(codec, codec->core.afg, 0, 3881 AC_VERB_SET_GPIO_DATA, cur_gpio); 3882 } 3883 3884 /* 3885 * PCM callbacks 3886 */ 3887 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3888 struct hda_codec *codec, 3889 unsigned int stream_tag, 3890 unsigned int format, 3891 struct snd_pcm_substream *substream) 3892 { 3893 struct ca0132_spec *spec = codec->spec; 3894 3895 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3896 3897 return 0; 3898 } 3899 3900 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3901 struct hda_codec *codec, 3902 struct snd_pcm_substream *substream) 3903 { 3904 struct ca0132_spec *spec = codec->spec; 3905 3906 if (spec->dsp_state == DSP_DOWNLOADING) 3907 return 0; 3908 3909 /*If Playback effects are on, allow stream some time to flush 3910 *effects tail*/ 3911 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3912 msleep(50); 3913 3914 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3915 3916 return 0; 3917 } 3918 3919 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3920 struct hda_codec *codec, 3921 struct snd_pcm_substream *substream) 3922 { 3923 struct ca0132_spec *spec = codec->spec; 3924 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3925 struct snd_pcm_runtime *runtime = substream->runtime; 3926 3927 if (spec->dsp_state != DSP_DOWNLOADED) 3928 return 0; 3929 3930 /* Add latency if playback enhancement and either effect is enabled. */ 3931 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3932 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3933 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3934 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3935 } 3936 3937 /* Applying Speaker EQ adds latency as well. */ 3938 if (spec->cur_out_type == SPEAKER_OUT) 3939 latency += DSP_SPEAKER_OUT_LATENCY; 3940 3941 return (latency * runtime->rate) / 1000; 3942 } 3943 3944 /* 3945 * Digital out 3946 */ 3947 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3948 struct hda_codec *codec, 3949 struct snd_pcm_substream *substream) 3950 { 3951 struct ca0132_spec *spec = codec->spec; 3952 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3953 } 3954 3955 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3956 struct hda_codec *codec, 3957 unsigned int stream_tag, 3958 unsigned int format, 3959 struct snd_pcm_substream *substream) 3960 { 3961 struct ca0132_spec *spec = codec->spec; 3962 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3963 stream_tag, format, substream); 3964 } 3965 3966 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3967 struct hda_codec *codec, 3968 struct snd_pcm_substream *substream) 3969 { 3970 struct ca0132_spec *spec = codec->spec; 3971 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3972 } 3973 3974 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3975 struct hda_codec *codec, 3976 struct snd_pcm_substream *substream) 3977 { 3978 struct ca0132_spec *spec = codec->spec; 3979 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3980 } 3981 3982 /* 3983 * Analog capture 3984 */ 3985 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3986 struct hda_codec *codec, 3987 unsigned int stream_tag, 3988 unsigned int format, 3989 struct snd_pcm_substream *substream) 3990 { 3991 snd_hda_codec_setup_stream(codec, hinfo->nid, 3992 stream_tag, 0, format); 3993 3994 return 0; 3995 } 3996 3997 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3998 struct hda_codec *codec, 3999 struct snd_pcm_substream *substream) 4000 { 4001 struct ca0132_spec *spec = codec->spec; 4002 4003 if (spec->dsp_state == DSP_DOWNLOADING) 4004 return 0; 4005 4006 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4007 return 0; 4008 } 4009 4010 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4011 struct hda_codec *codec, 4012 struct snd_pcm_substream *substream) 4013 { 4014 struct ca0132_spec *spec = codec->spec; 4015 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4016 struct snd_pcm_runtime *runtime = substream->runtime; 4017 4018 if (spec->dsp_state != DSP_DOWNLOADED) 4019 return 0; 4020 4021 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4022 latency += DSP_CRYSTAL_VOICE_LATENCY; 4023 4024 return (latency * runtime->rate) / 1000; 4025 } 4026 4027 /* 4028 * Controls stuffs. 4029 */ 4030 4031 /* 4032 * Mixer controls helpers. 4033 */ 4034 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4035 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4036 .name = xname, \ 4037 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4038 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4039 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4040 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4041 .info = ca0132_volume_info, \ 4042 .get = ca0132_volume_get, \ 4043 .put = ca0132_volume_put, \ 4044 .tlv = { .c = ca0132_volume_tlv }, \ 4045 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4046 4047 /* 4048 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4049 * volume put, which is used for setting the DSP volume. This was done because 4050 * the ca0132 functions were taking too much time and causing lag. 4051 */ 4052 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4053 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4054 .name = xname, \ 4055 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4056 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4057 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4058 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4059 .info = snd_hda_mixer_amp_volume_info, \ 4060 .get = snd_hda_mixer_amp_volume_get, \ 4061 .put = ca0132_alt_volume_put, \ 4062 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4063 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4064 4065 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4066 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4067 .name = xname, \ 4068 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4069 .info = snd_hda_mixer_amp_switch_info, \ 4070 .get = ca0132_switch_get, \ 4071 .put = ca0132_switch_put, \ 4072 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4073 4074 /* stereo */ 4075 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4076 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4077 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4078 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4079 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4080 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4081 4082 /* lookup tables */ 4083 /* 4084 * Lookup table with decibel values for the DSP. When volume is changed in 4085 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4086 * these values have decimal points, probably because the Windows driver 4087 * actually uses floating point. We can't here, so I made a lookup table of 4088 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4089 * DAC's, and 9 is the maximum. 4090 */ 4091 static const unsigned int float_vol_db_lookup[] = { 4092 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4093 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4094 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4095 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4096 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4097 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4098 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4099 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4100 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4101 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4102 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4103 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4104 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4105 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4106 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4107 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4108 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4109 }; 4110 4111 /* 4112 * This table counts from float 0 to 1 in increments of .01, which is 4113 * useful for a few different sliders. 4114 */ 4115 static const unsigned int float_zero_to_one_lookup[] = { 4116 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4117 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4118 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4119 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4120 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4121 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4122 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4123 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4124 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4125 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4126 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4127 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4128 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4129 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4130 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4131 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4132 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4133 }; 4134 4135 /* 4136 * This table counts from float 10 to 1000, which is the range of the x-bass 4137 * crossover slider in Windows. 4138 */ 4139 static const unsigned int float_xbass_xover_lookup[] = { 4140 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4141 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4142 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4143 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4144 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4145 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4146 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4147 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4148 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4149 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4150 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4151 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4152 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4153 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4154 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4155 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4156 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4157 }; 4158 4159 /* The following are for tuning of products */ 4160 #ifdef ENABLE_TUNING_CONTROLS 4161 4162 static const unsigned int voice_focus_vals_lookup[] = { 4163 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4164 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4165 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4166 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4167 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4168 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4169 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4170 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4171 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4172 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4173 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4174 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4175 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4176 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4177 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4178 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4179 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4180 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4181 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4182 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4183 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4184 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4185 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4186 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4187 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4188 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4189 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4190 }; 4191 4192 static const unsigned int mic_svm_vals_lookup[] = { 4193 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4194 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4195 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4196 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4197 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4198 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4199 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4200 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4201 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4202 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4203 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4204 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4205 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4206 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4207 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4208 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4209 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4210 }; 4211 4212 static const unsigned int equalizer_vals_lookup[] = { 4213 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4214 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4215 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4216 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4217 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4218 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4219 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4220 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4221 0x41C00000 4222 }; 4223 4224 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4225 const unsigned int *lookup, int idx) 4226 { 4227 int i = 0; 4228 4229 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4230 if (nid == ca0132_tuning_ctls[i].nid) 4231 break; 4232 4233 snd_hda_power_up(codec); 4234 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4235 ca0132_tuning_ctls[i].req, 4236 &(lookup[idx]), sizeof(unsigned int)); 4237 snd_hda_power_down(codec); 4238 4239 return 1; 4240 } 4241 4242 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4243 struct snd_ctl_elem_value *ucontrol) 4244 { 4245 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4246 struct ca0132_spec *spec = codec->spec; 4247 hda_nid_t nid = get_amp_nid(kcontrol); 4248 long *valp = ucontrol->value.integer.value; 4249 int idx = nid - TUNING_CTL_START_NID; 4250 4251 *valp = spec->cur_ctl_vals[idx]; 4252 return 0; 4253 } 4254 4255 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4256 struct snd_ctl_elem_info *uinfo) 4257 { 4258 int chs = get_amp_channels(kcontrol); 4259 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4260 uinfo->count = chs == 3 ? 2 : 1; 4261 uinfo->value.integer.min = 20; 4262 uinfo->value.integer.max = 180; 4263 uinfo->value.integer.step = 1; 4264 4265 return 0; 4266 } 4267 4268 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4269 struct snd_ctl_elem_value *ucontrol) 4270 { 4271 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4272 struct ca0132_spec *spec = codec->spec; 4273 hda_nid_t nid = get_amp_nid(kcontrol); 4274 long *valp = ucontrol->value.integer.value; 4275 int idx; 4276 4277 idx = nid - TUNING_CTL_START_NID; 4278 /* any change? */ 4279 if (spec->cur_ctl_vals[idx] == *valp) 4280 return 0; 4281 4282 spec->cur_ctl_vals[idx] = *valp; 4283 4284 idx = *valp - 20; 4285 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4286 4287 return 1; 4288 } 4289 4290 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4291 struct snd_ctl_elem_info *uinfo) 4292 { 4293 int chs = get_amp_channels(kcontrol); 4294 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4295 uinfo->count = chs == 3 ? 2 : 1; 4296 uinfo->value.integer.min = 0; 4297 uinfo->value.integer.max = 100; 4298 uinfo->value.integer.step = 1; 4299 4300 return 0; 4301 } 4302 4303 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4304 struct snd_ctl_elem_value *ucontrol) 4305 { 4306 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4307 struct ca0132_spec *spec = codec->spec; 4308 hda_nid_t nid = get_amp_nid(kcontrol); 4309 long *valp = ucontrol->value.integer.value; 4310 int idx; 4311 4312 idx = nid - TUNING_CTL_START_NID; 4313 /* any change? */ 4314 if (spec->cur_ctl_vals[idx] == *valp) 4315 return 0; 4316 4317 spec->cur_ctl_vals[idx] = *valp; 4318 4319 idx = *valp; 4320 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4321 4322 return 0; 4323 } 4324 4325 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4326 struct snd_ctl_elem_info *uinfo) 4327 { 4328 int chs = get_amp_channels(kcontrol); 4329 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4330 uinfo->count = chs == 3 ? 2 : 1; 4331 uinfo->value.integer.min = 0; 4332 uinfo->value.integer.max = 48; 4333 uinfo->value.integer.step = 1; 4334 4335 return 0; 4336 } 4337 4338 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4339 struct snd_ctl_elem_value *ucontrol) 4340 { 4341 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4342 struct ca0132_spec *spec = codec->spec; 4343 hda_nid_t nid = get_amp_nid(kcontrol); 4344 long *valp = ucontrol->value.integer.value; 4345 int idx; 4346 4347 idx = nid - TUNING_CTL_START_NID; 4348 /* any change? */ 4349 if (spec->cur_ctl_vals[idx] == *valp) 4350 return 0; 4351 4352 spec->cur_ctl_vals[idx] = *valp; 4353 4354 idx = *valp; 4355 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4356 4357 return 1; 4358 } 4359 4360 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4361 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4362 4363 static int add_tuning_control(struct hda_codec *codec, 4364 hda_nid_t pnid, hda_nid_t nid, 4365 const char *name, int dir) 4366 { 4367 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4368 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4369 struct snd_kcontrol_new knew = 4370 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4371 4372 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4373 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4374 knew.tlv.c = 0; 4375 knew.tlv.p = 0; 4376 switch (pnid) { 4377 case VOICE_FOCUS: 4378 knew.info = voice_focus_ctl_info; 4379 knew.get = tuning_ctl_get; 4380 knew.put = voice_focus_ctl_put; 4381 knew.tlv.p = voice_focus_db_scale; 4382 break; 4383 case MIC_SVM: 4384 knew.info = mic_svm_ctl_info; 4385 knew.get = tuning_ctl_get; 4386 knew.put = mic_svm_ctl_put; 4387 break; 4388 case EQUALIZER: 4389 knew.info = equalizer_ctl_info; 4390 knew.get = tuning_ctl_get; 4391 knew.put = equalizer_ctl_put; 4392 knew.tlv.p = eq_db_scale; 4393 break; 4394 default: 4395 return 0; 4396 } 4397 knew.private_value = 4398 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4399 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4400 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4401 } 4402 4403 static int add_tuning_ctls(struct hda_codec *codec) 4404 { 4405 int i; 4406 int err; 4407 4408 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4409 err = add_tuning_control(codec, 4410 ca0132_tuning_ctls[i].parent_nid, 4411 ca0132_tuning_ctls[i].nid, 4412 ca0132_tuning_ctls[i].name, 4413 ca0132_tuning_ctls[i].direct); 4414 if (err < 0) 4415 return err; 4416 } 4417 4418 return 0; 4419 } 4420 4421 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4422 { 4423 struct ca0132_spec *spec = codec->spec; 4424 int i; 4425 4426 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4427 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4428 /* SVM level defaults to 0.74. */ 4429 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4430 4431 /* EQ defaults to 0dB. */ 4432 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4433 spec->cur_ctl_vals[i] = 24; 4434 } 4435 #endif /*ENABLE_TUNING_CONTROLS*/ 4436 4437 /* 4438 * Select the active output. 4439 * If autodetect is enabled, output will be selected based on jack detection. 4440 * If jack inserted, headphone will be selected, else built-in speakers 4441 * If autodetect is disabled, output will be selected based on selection. 4442 */ 4443 static int ca0132_select_out(struct hda_codec *codec) 4444 { 4445 struct ca0132_spec *spec = codec->spec; 4446 unsigned int pin_ctl; 4447 int jack_present; 4448 int auto_jack; 4449 unsigned int tmp; 4450 int err; 4451 4452 codec_dbg(codec, "ca0132_select_out\n"); 4453 4454 snd_hda_power_up_pm(codec); 4455 4456 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4457 4458 if (auto_jack) 4459 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4460 else 4461 jack_present = 4462 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4463 4464 if (jack_present) 4465 spec->cur_out_type = HEADPHONE_OUT; 4466 else 4467 spec->cur_out_type = SPEAKER_OUT; 4468 4469 if (spec->cur_out_type == SPEAKER_OUT) { 4470 codec_dbg(codec, "ca0132_select_out speaker\n"); 4471 /*speaker out config*/ 4472 tmp = FLOAT_ONE; 4473 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4474 if (err < 0) 4475 goto exit; 4476 /*enable speaker EQ*/ 4477 tmp = FLOAT_ONE; 4478 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4479 if (err < 0) 4480 goto exit; 4481 4482 /* Setup EAPD */ 4483 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4484 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4485 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4486 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4487 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4488 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4489 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4490 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4491 4492 /* disable headphone node */ 4493 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4494 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4495 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4496 pin_ctl & ~PIN_HP); 4497 /* enable speaker node */ 4498 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4499 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4500 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4501 pin_ctl | PIN_OUT); 4502 } else { 4503 codec_dbg(codec, "ca0132_select_out hp\n"); 4504 /*headphone out config*/ 4505 tmp = FLOAT_ZERO; 4506 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4507 if (err < 0) 4508 goto exit; 4509 /*disable speaker EQ*/ 4510 tmp = FLOAT_ZERO; 4511 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4512 if (err < 0) 4513 goto exit; 4514 4515 /* Setup EAPD */ 4516 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4517 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4518 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4519 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4520 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4521 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4522 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4523 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4524 4525 /* disable speaker*/ 4526 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4527 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4528 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4529 pin_ctl & ~PIN_HP); 4530 /* enable headphone*/ 4531 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4532 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4533 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4534 pin_ctl | PIN_HP); 4535 } 4536 4537 exit: 4538 snd_hda_power_down_pm(codec); 4539 4540 return err < 0 ? err : 0; 4541 } 4542 4543 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4544 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4545 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4546 4547 static void ae5_mmio_select_out(struct hda_codec *codec) 4548 { 4549 struct ca0132_spec *spec = codec->spec; 4550 const struct ae_ca0113_output_set *out_cmds; 4551 unsigned int i; 4552 4553 if (ca0132_quirk(spec) == QUIRK_AE5) 4554 out_cmds = &ae5_ca0113_output_presets; 4555 else 4556 out_cmds = &ae7_ca0113_output_presets; 4557 4558 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4559 ca0113_mmio_command_set(codec, out_cmds->group[i], 4560 out_cmds->target[i], 4561 out_cmds->vals[spec->cur_out_type][i]); 4562 } 4563 4564 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4565 { 4566 struct ca0132_spec *spec = codec->spec; 4567 int quirk = ca0132_quirk(spec); 4568 unsigned int tmp; 4569 int err; 4570 4571 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4572 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4573 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4574 return 0; 4575 4576 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4577 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4578 err = dspio_set_uint_param(codec, 0x96, 4579 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4580 if (err < 0) 4581 return err; 4582 4583 /* When setting full-range rear, both rear and center/lfe are set. */ 4584 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4585 err = dspio_set_uint_param(codec, 0x96, 4586 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4587 if (err < 0) 4588 return err; 4589 4590 err = dspio_set_uint_param(codec, 0x96, 4591 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4592 if (err < 0) 4593 return err; 4594 4595 /* 4596 * Only the AE series cards set this value when setting full-range, 4597 * and it's always 1.0f. 4598 */ 4599 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4600 err = dspio_set_uint_param(codec, 0x96, 4601 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4602 if (err < 0) 4603 return err; 4604 } 4605 4606 return 0; 4607 } 4608 4609 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4610 bool val) 4611 { 4612 struct ca0132_spec *spec = codec->spec; 4613 unsigned int tmp; 4614 int err; 4615 4616 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4617 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4618 tmp = FLOAT_ONE; 4619 else 4620 tmp = FLOAT_ZERO; 4621 4622 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4623 if (err < 0) 4624 return err; 4625 4626 /* If it is enabled, make sure to set the crossover frequency. */ 4627 if (tmp) { 4628 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4629 err = dspio_set_uint_param(codec, 0x96, 4630 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4631 if (err < 0) 4632 return err; 4633 } 4634 4635 return 0; 4636 } 4637 4638 /* 4639 * These are the commands needed to setup output on each of the different card 4640 * types. 4641 */ 4642 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4643 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4644 { 4645 struct ca0132_spec *spec = codec->spec; 4646 int quirk = ca0132_quirk(spec); 4647 unsigned int i; 4648 4649 *quirk_data = NULL; 4650 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4651 if (quirk_out_set_data[i].quirk_id == quirk) { 4652 *quirk_data = &quirk_out_set_data[i]; 4653 return; 4654 } 4655 } 4656 } 4657 4658 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4659 { 4660 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4661 const struct ca0132_alt_out_set_info *out_info; 4662 struct ca0132_spec *spec = codec->spec; 4663 unsigned int i, gpio_data; 4664 int err; 4665 4666 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4667 if (!quirk_data) 4668 return 0; 4669 4670 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4671 if (quirk_data->is_ae_series) 4672 ae5_mmio_select_out(codec); 4673 4674 if (out_info->has_hda_gpio) { 4675 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4676 AC_VERB_GET_GPIO_DATA, 0); 4677 4678 if (out_info->hda_gpio_set) 4679 gpio_data |= (1 << out_info->hda_gpio_pin); 4680 else 4681 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4682 4683 snd_hda_codec_write(codec, codec->core.afg, 0, 4684 AC_VERB_SET_GPIO_DATA, gpio_data); 4685 } 4686 4687 if (out_info->mmio_gpio_count) { 4688 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4689 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4690 out_info->mmio_gpio_set[i]); 4691 } 4692 } 4693 4694 if (out_info->scp_cmds_count) { 4695 for (i = 0; i < out_info->scp_cmds_count; i++) { 4696 err = dspio_set_uint_param(codec, 4697 out_info->scp_cmd_mid[i], 4698 out_info->scp_cmd_req[i], 4699 out_info->scp_cmd_val[i]); 4700 if (err < 0) 4701 return err; 4702 } 4703 } 4704 4705 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4706 4707 if (out_info->has_chipio_write) { 4708 chipio_write(codec, out_info->chipio_write_addr, 4709 out_info->chipio_write_data); 4710 } 4711 4712 if (quirk_data->has_headphone_gain) { 4713 if (spec->cur_out_type != HEADPHONE_OUT) { 4714 if (quirk_data->is_ae_series) 4715 ae5_headphone_gain_set(codec, 2); 4716 else 4717 zxr_headphone_gain_set(codec, 0); 4718 } else { 4719 if (quirk_data->is_ae_series) 4720 ae5_headphone_gain_set(codec, 4721 spec->ae5_headphone_gain_val); 4722 else 4723 zxr_headphone_gain_set(codec, 4724 spec->zxr_gain_set); 4725 } 4726 } 4727 4728 return 0; 4729 } 4730 4731 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4732 bool out_enable, bool hp_enable) 4733 { 4734 unsigned int pin_ctl; 4735 4736 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4737 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4738 4739 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4740 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4741 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4742 } 4743 4744 /* 4745 * This function behaves similarly to the ca0132_select_out funciton above, 4746 * except with a few differences. It adds the ability to select the current 4747 * output with an enumerated control "output source" if the auto detect 4748 * mute switch is set to off. If the auto detect mute switch is enabled, it 4749 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4750 * It also adds the ability to auto-detect the front headphone port. 4751 */ 4752 static int ca0132_alt_select_out(struct hda_codec *codec) 4753 { 4754 struct ca0132_spec *spec = codec->spec; 4755 unsigned int tmp, outfx_set; 4756 int jack_present; 4757 int auto_jack; 4758 int err; 4759 /* Default Headphone is rear headphone */ 4760 hda_nid_t headphone_nid = spec->out_pins[1]; 4761 4762 codec_dbg(codec, "%s\n", __func__); 4763 4764 snd_hda_power_up_pm(codec); 4765 4766 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4767 4768 /* 4769 * If headphone rear or front is plugged in, set to headphone. 4770 * If neither is plugged in, set to rear line out. Only if 4771 * hp/speaker auto detect is enabled. 4772 */ 4773 if (auto_jack) { 4774 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4775 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4776 4777 if (jack_present) 4778 spec->cur_out_type = HEADPHONE_OUT; 4779 else 4780 spec->cur_out_type = SPEAKER_OUT; 4781 } else 4782 spec->cur_out_type = spec->out_enum_val; 4783 4784 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4785 4786 /* Begin DSP output switch, mute DSP volume. */ 4787 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4788 if (err < 0) 4789 goto exit; 4790 4791 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4792 goto exit; 4793 4794 switch (spec->cur_out_type) { 4795 case SPEAKER_OUT: 4796 codec_dbg(codec, "%s speaker\n", __func__); 4797 4798 /* Enable EAPD */ 4799 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4800 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4801 4802 /* Disable headphone node. */ 4803 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4804 /* Set front L-R to output. */ 4805 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4806 /* Set Center/LFE to output. */ 4807 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4808 /* Set rear surround to output. */ 4809 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4810 4811 /* 4812 * Without PlayEnhancement being enabled, if we've got a 2.0 4813 * setup, set it to floating point eight to disable any DSP 4814 * processing effects. 4815 */ 4816 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4817 tmp = FLOAT_EIGHT; 4818 else 4819 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4820 4821 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4822 if (err < 0) 4823 goto exit; 4824 4825 break; 4826 case HEADPHONE_OUT: 4827 codec_dbg(codec, "%s hp\n", __func__); 4828 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4829 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4830 4831 /* Disable all speaker nodes. */ 4832 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4833 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4834 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4835 4836 /* enable headphone, either front or rear */ 4837 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4838 headphone_nid = spec->out_pins[2]; 4839 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4840 headphone_nid = spec->out_pins[1]; 4841 4842 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4843 4844 if (outfx_set) 4845 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4846 else 4847 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4848 4849 if (err < 0) 4850 goto exit; 4851 break; 4852 } 4853 /* 4854 * If output effects are enabled, set the X-Bass effect value again to 4855 * make sure that it's properly enabled/disabled for speaker 4856 * configurations with an LFE channel. 4857 */ 4858 if (outfx_set) 4859 ca0132_effects_set(codec, X_BASS, 4860 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4861 4862 /* Set speaker EQ bypass attenuation to 0. */ 4863 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4864 if (err < 0) 4865 goto exit; 4866 4867 /* 4868 * Although unused on all cards but the AE series, this is always set 4869 * to zero when setting the output. 4870 */ 4871 err = dspio_set_uint_param(codec, 0x96, 4872 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4873 if (err < 0) 4874 goto exit; 4875 4876 if (spec->cur_out_type == SPEAKER_OUT) 4877 err = ca0132_alt_surround_set_bass_redirection(codec, 4878 spec->bass_redirection_val); 4879 else 4880 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4881 4882 /* Unmute DSP now that we're done with output selection. */ 4883 err = dspio_set_uint_param(codec, 0x96, 4884 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4885 if (err < 0) 4886 goto exit; 4887 4888 if (spec->cur_out_type == SPEAKER_OUT) { 4889 err = ca0132_alt_set_full_range_speaker(codec); 4890 if (err < 0) 4891 goto exit; 4892 } 4893 4894 exit: 4895 snd_hda_power_down_pm(codec); 4896 4897 return err < 0 ? err : 0; 4898 } 4899 4900 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4901 { 4902 struct ca0132_spec *spec = container_of( 4903 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4904 struct hda_jack_tbl *jack; 4905 4906 if (ca0132_use_alt_functions(spec)) 4907 ca0132_alt_select_out(spec->codec); 4908 else 4909 ca0132_select_out(spec->codec); 4910 4911 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4912 if (jack) { 4913 jack->block_report = 0; 4914 snd_hda_jack_report_sync(spec->codec); 4915 } 4916 } 4917 4918 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4919 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4920 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4921 static int stop_mic1(struct hda_codec *codec); 4922 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4923 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4924 4925 /* 4926 * Select the active VIP source 4927 */ 4928 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4929 { 4930 struct ca0132_spec *spec = codec->spec; 4931 unsigned int tmp; 4932 4933 if (spec->dsp_state != DSP_DOWNLOADED) 4934 return 0; 4935 4936 /* if CrystalVoice if off, vipsource should be 0 */ 4937 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4938 (val == 0)) { 4939 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4940 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4941 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4942 if (spec->cur_mic_type == DIGITAL_MIC) 4943 tmp = FLOAT_TWO; 4944 else 4945 tmp = FLOAT_ONE; 4946 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4947 tmp = FLOAT_ZERO; 4948 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4949 } else { 4950 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4951 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4952 if (spec->cur_mic_type == DIGITAL_MIC) 4953 tmp = FLOAT_TWO; 4954 else 4955 tmp = FLOAT_ONE; 4956 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4957 tmp = FLOAT_ONE; 4958 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4959 msleep(20); 4960 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4961 } 4962 4963 return 1; 4964 } 4965 4966 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4967 { 4968 struct ca0132_spec *spec = codec->spec; 4969 unsigned int tmp; 4970 4971 if (spec->dsp_state != DSP_DOWNLOADED) 4972 return 0; 4973 4974 codec_dbg(codec, "%s\n", __func__); 4975 4976 chipio_set_stream_control(codec, 0x03, 0); 4977 chipio_set_stream_control(codec, 0x04, 0); 4978 4979 /* if CrystalVoice is off, vipsource should be 0 */ 4980 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4981 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4982 codec_dbg(codec, "%s: off.", __func__); 4983 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4984 4985 tmp = FLOAT_ZERO; 4986 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4987 4988 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4989 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4990 if (ca0132_quirk(spec) == QUIRK_R3DI) 4991 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4992 4993 4994 if (spec->in_enum_val == REAR_LINE_IN) 4995 tmp = FLOAT_ZERO; 4996 else { 4997 if (ca0132_quirk(spec) == QUIRK_SBZ) 4998 tmp = FLOAT_THREE; 4999 else 5000 tmp = FLOAT_ONE; 5001 } 5002 5003 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5004 5005 } else { 5006 codec_dbg(codec, "%s: on.", __func__); 5007 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5008 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5009 if (ca0132_quirk(spec) == QUIRK_R3DI) 5010 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5011 5012 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5013 tmp = FLOAT_TWO; 5014 else 5015 tmp = FLOAT_ONE; 5016 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5017 5018 tmp = FLOAT_ONE; 5019 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5020 5021 msleep(20); 5022 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5023 } 5024 5025 chipio_set_stream_control(codec, 0x03, 1); 5026 chipio_set_stream_control(codec, 0x04, 1); 5027 5028 return 1; 5029 } 5030 5031 /* 5032 * Select the active microphone. 5033 * If autodetect is enabled, mic will be selected based on jack detection. 5034 * If jack inserted, ext.mic will be selected, else built-in mic 5035 * If autodetect is disabled, mic will be selected based on selection. 5036 */ 5037 static int ca0132_select_mic(struct hda_codec *codec) 5038 { 5039 struct ca0132_spec *spec = codec->spec; 5040 int jack_present; 5041 int auto_jack; 5042 5043 codec_dbg(codec, "ca0132_select_mic\n"); 5044 5045 snd_hda_power_up_pm(codec); 5046 5047 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5048 5049 if (auto_jack) 5050 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5051 else 5052 jack_present = 5053 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5054 5055 if (jack_present) 5056 spec->cur_mic_type = LINE_MIC_IN; 5057 else 5058 spec->cur_mic_type = DIGITAL_MIC; 5059 5060 if (spec->cur_mic_type == DIGITAL_MIC) { 5061 /* enable digital Mic */ 5062 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5063 ca0132_set_dmic(codec, 1); 5064 ca0132_mic_boost_set(codec, 0); 5065 /* set voice focus */ 5066 ca0132_effects_set(codec, VOICE_FOCUS, 5067 spec->effects_switch 5068 [VOICE_FOCUS - EFFECT_START_NID]); 5069 } else { 5070 /* disable digital Mic */ 5071 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5072 ca0132_set_dmic(codec, 0); 5073 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5074 /* disable voice focus */ 5075 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5076 } 5077 5078 snd_hda_power_down_pm(codec); 5079 5080 return 0; 5081 } 5082 5083 /* 5084 * Select the active input. 5085 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5086 * The front mic has no jack-detection, so the only way to switch to it 5087 * is to do it manually in alsamixer. 5088 */ 5089 static int ca0132_alt_select_in(struct hda_codec *codec) 5090 { 5091 struct ca0132_spec *spec = codec->spec; 5092 unsigned int tmp; 5093 5094 codec_dbg(codec, "%s\n", __func__); 5095 5096 snd_hda_power_up_pm(codec); 5097 5098 chipio_set_stream_control(codec, 0x03, 0); 5099 chipio_set_stream_control(codec, 0x04, 0); 5100 5101 spec->cur_mic_type = spec->in_enum_val; 5102 5103 switch (spec->cur_mic_type) { 5104 case REAR_MIC: 5105 switch (ca0132_quirk(spec)) { 5106 case QUIRK_SBZ: 5107 case QUIRK_R3D: 5108 ca0113_mmio_gpio_set(codec, 0, false); 5109 tmp = FLOAT_THREE; 5110 break; 5111 case QUIRK_ZXR: 5112 tmp = FLOAT_THREE; 5113 break; 5114 case QUIRK_R3DI: 5115 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5116 tmp = FLOAT_ONE; 5117 break; 5118 case QUIRK_AE5: 5119 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5120 tmp = FLOAT_THREE; 5121 break; 5122 case QUIRK_AE7: 5123 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5124 tmp = FLOAT_THREE; 5125 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5126 SR_96_000); 5127 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5128 SR_96_000); 5129 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5130 break; 5131 default: 5132 tmp = FLOAT_ONE; 5133 break; 5134 } 5135 5136 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5137 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5138 if (ca0132_quirk(spec) == QUIRK_R3DI) 5139 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5140 5141 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5142 5143 chipio_set_stream_control(codec, 0x03, 1); 5144 chipio_set_stream_control(codec, 0x04, 1); 5145 switch (ca0132_quirk(spec)) { 5146 case QUIRK_SBZ: 5147 chipio_write(codec, 0x18B098, 0x0000000C); 5148 chipio_write(codec, 0x18B09C, 0x0000000C); 5149 break; 5150 case QUIRK_ZXR: 5151 chipio_write(codec, 0x18B098, 0x0000000C); 5152 chipio_write(codec, 0x18B09C, 0x000000CC); 5153 break; 5154 case QUIRK_AE5: 5155 chipio_write(codec, 0x18B098, 0x0000000C); 5156 chipio_write(codec, 0x18B09C, 0x0000004C); 5157 break; 5158 default: 5159 break; 5160 } 5161 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5162 break; 5163 case REAR_LINE_IN: 5164 ca0132_mic_boost_set(codec, 0); 5165 switch (ca0132_quirk(spec)) { 5166 case QUIRK_SBZ: 5167 case QUIRK_R3D: 5168 ca0113_mmio_gpio_set(codec, 0, false); 5169 break; 5170 case QUIRK_R3DI: 5171 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5172 break; 5173 case QUIRK_AE5: 5174 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5175 break; 5176 case QUIRK_AE7: 5177 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5178 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5179 SR_96_000); 5180 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5181 SR_96_000); 5182 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5183 break; 5184 default: 5185 break; 5186 } 5187 5188 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5189 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5190 if (ca0132_quirk(spec) == QUIRK_R3DI) 5191 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5192 5193 if (ca0132_quirk(spec) == QUIRK_AE7) 5194 tmp = FLOAT_THREE; 5195 else 5196 tmp = FLOAT_ZERO; 5197 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5198 5199 switch (ca0132_quirk(spec)) { 5200 case QUIRK_SBZ: 5201 case QUIRK_AE5: 5202 chipio_write(codec, 0x18B098, 0x00000000); 5203 chipio_write(codec, 0x18B09C, 0x00000000); 5204 break; 5205 default: 5206 break; 5207 } 5208 chipio_set_stream_control(codec, 0x03, 1); 5209 chipio_set_stream_control(codec, 0x04, 1); 5210 break; 5211 case FRONT_MIC: 5212 switch (ca0132_quirk(spec)) { 5213 case QUIRK_SBZ: 5214 case QUIRK_R3D: 5215 ca0113_mmio_gpio_set(codec, 0, true); 5216 ca0113_mmio_gpio_set(codec, 5, false); 5217 tmp = FLOAT_THREE; 5218 break; 5219 case QUIRK_R3DI: 5220 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5221 tmp = FLOAT_ONE; 5222 break; 5223 case QUIRK_AE5: 5224 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5225 tmp = FLOAT_THREE; 5226 break; 5227 default: 5228 tmp = FLOAT_ONE; 5229 break; 5230 } 5231 5232 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5233 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5234 if (ca0132_quirk(spec) == QUIRK_R3DI) 5235 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5236 5237 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5238 5239 chipio_set_stream_control(codec, 0x03, 1); 5240 chipio_set_stream_control(codec, 0x04, 1); 5241 5242 switch (ca0132_quirk(spec)) { 5243 case QUIRK_SBZ: 5244 chipio_write(codec, 0x18B098, 0x0000000C); 5245 chipio_write(codec, 0x18B09C, 0x000000CC); 5246 break; 5247 case QUIRK_AE5: 5248 chipio_write(codec, 0x18B098, 0x0000000C); 5249 chipio_write(codec, 0x18B09C, 0x0000004C); 5250 break; 5251 default: 5252 break; 5253 } 5254 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5255 break; 5256 } 5257 ca0132_cvoice_switch_set(codec); 5258 5259 snd_hda_power_down_pm(codec); 5260 return 0; 5261 } 5262 5263 /* 5264 * Check if VNODE settings take effect immediately. 5265 */ 5266 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5267 hda_nid_t vnid, 5268 hda_nid_t *shared_nid) 5269 { 5270 struct ca0132_spec *spec = codec->spec; 5271 hda_nid_t nid; 5272 5273 switch (vnid) { 5274 case VNID_SPK: 5275 nid = spec->shared_out_nid; 5276 break; 5277 case VNID_MIC: 5278 nid = spec->shared_mic_nid; 5279 break; 5280 default: 5281 return false; 5282 } 5283 5284 if (shared_nid) 5285 *shared_nid = nid; 5286 5287 return true; 5288 } 5289 5290 /* 5291 * The following functions are control change helpers. 5292 * They return 0 if no changed. Return 1 if changed. 5293 */ 5294 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5295 { 5296 struct ca0132_spec *spec = codec->spec; 5297 unsigned int tmp; 5298 5299 /* based on CrystalVoice state to enable VoiceFX. */ 5300 if (enable) { 5301 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5302 FLOAT_ONE : FLOAT_ZERO; 5303 } else { 5304 tmp = FLOAT_ZERO; 5305 } 5306 5307 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5308 ca0132_voicefx.reqs[0], tmp); 5309 5310 return 1; 5311 } 5312 5313 /* 5314 * Set the effects parameters 5315 */ 5316 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5317 { 5318 struct ca0132_spec *spec = codec->spec; 5319 unsigned int on, tmp, channel_cfg; 5320 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5321 int err = 0; 5322 int idx = nid - EFFECT_START_NID; 5323 5324 if ((idx < 0) || (idx >= num_fx)) 5325 return 0; /* no changed */ 5326 5327 /* for out effect, qualify with PE */ 5328 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5329 /* if PE if off, turn off out effects. */ 5330 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5331 val = 0; 5332 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5333 channel_cfg = spec->channel_cfg_val; 5334 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5335 channel_cfg != SPEAKER_CHANNELS_4_0) 5336 val = 0; 5337 } 5338 } 5339 5340 /* for in effect, qualify with CrystalVoice */ 5341 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5342 /* if CrystalVoice if off, turn off in effects. */ 5343 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5344 val = 0; 5345 5346 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5347 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5348 val = 0; 5349 5350 /* If Voice Focus on SBZ, set to two channel. */ 5351 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5352 && (spec->cur_mic_type != REAR_LINE_IN)) { 5353 if (spec->effects_switch[CRYSTAL_VOICE - 5354 EFFECT_START_NID]) { 5355 5356 if (spec->effects_switch[VOICE_FOCUS - 5357 EFFECT_START_NID]) { 5358 tmp = FLOAT_TWO; 5359 val = 1; 5360 } else 5361 tmp = FLOAT_ONE; 5362 5363 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5364 } 5365 } 5366 /* 5367 * For SBZ noise reduction, there's an extra command 5368 * to module ID 0x47. No clue why. 5369 */ 5370 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5371 && (spec->cur_mic_type != REAR_LINE_IN)) { 5372 if (spec->effects_switch[CRYSTAL_VOICE - 5373 EFFECT_START_NID]) { 5374 if (spec->effects_switch[NOISE_REDUCTION - 5375 EFFECT_START_NID]) 5376 tmp = FLOAT_ONE; 5377 else 5378 tmp = FLOAT_ZERO; 5379 } else 5380 tmp = FLOAT_ZERO; 5381 5382 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5383 } 5384 5385 /* If rear line in disable effects. */ 5386 if (ca0132_use_alt_functions(spec) && 5387 spec->in_enum_val == REAR_LINE_IN) 5388 val = 0; 5389 } 5390 5391 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5392 nid, val); 5393 5394 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5395 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5396 ca0132_effects[idx].reqs[0], on); 5397 5398 if (err < 0) 5399 return 0; /* no changed */ 5400 5401 return 1; 5402 } 5403 5404 /* 5405 * Turn on/off Playback Enhancements 5406 */ 5407 static int ca0132_pe_switch_set(struct hda_codec *codec) 5408 { 5409 struct ca0132_spec *spec = codec->spec; 5410 hda_nid_t nid; 5411 int i, ret = 0; 5412 5413 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5414 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5415 5416 if (ca0132_use_alt_functions(spec)) 5417 ca0132_alt_select_out(codec); 5418 5419 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5420 nid = OUT_EFFECT_START_NID; 5421 /* PE affects all out effects */ 5422 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5423 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5424 5425 return ret; 5426 } 5427 5428 /* Check if Mic1 is streaming, if so, stop streaming */ 5429 static int stop_mic1(struct hda_codec *codec) 5430 { 5431 struct ca0132_spec *spec = codec->spec; 5432 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5433 AC_VERB_GET_CONV, 0); 5434 if (oldval != 0) 5435 snd_hda_codec_write(codec, spec->adcs[0], 0, 5436 AC_VERB_SET_CHANNEL_STREAMID, 5437 0); 5438 return oldval; 5439 } 5440 5441 /* Resume Mic1 streaming if it was stopped. */ 5442 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5443 { 5444 struct ca0132_spec *spec = codec->spec; 5445 /* Restore the previous stream and channel */ 5446 if (oldval != 0) 5447 snd_hda_codec_write(codec, spec->adcs[0], 0, 5448 AC_VERB_SET_CHANNEL_STREAMID, 5449 oldval); 5450 } 5451 5452 /* 5453 * Turn on/off CrystalVoice 5454 */ 5455 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5456 { 5457 struct ca0132_spec *spec = codec->spec; 5458 hda_nid_t nid; 5459 int i, ret = 0; 5460 unsigned int oldval; 5461 5462 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5463 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5464 5465 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5466 nid = IN_EFFECT_START_NID; 5467 /* CrystalVoice affects all in effects */ 5468 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5469 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5470 5471 /* including VoiceFX */ 5472 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5473 5474 /* set correct vipsource */ 5475 oldval = stop_mic1(codec); 5476 if (ca0132_use_alt_functions(spec)) 5477 ret |= ca0132_alt_set_vipsource(codec, 1); 5478 else 5479 ret |= ca0132_set_vipsource(codec, 1); 5480 resume_mic1(codec, oldval); 5481 return ret; 5482 } 5483 5484 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5485 { 5486 struct ca0132_spec *spec = codec->spec; 5487 int ret = 0; 5488 5489 if (val) /* on */ 5490 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5491 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5492 else /* off */ 5493 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5494 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5495 5496 return ret; 5497 } 5498 5499 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5500 { 5501 struct ca0132_spec *spec = codec->spec; 5502 int ret = 0; 5503 5504 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5505 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5506 return ret; 5507 } 5508 5509 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5510 { 5511 unsigned int i; 5512 5513 for (i = 0; i < 4; i++) 5514 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5515 ae5_headphone_gain_presets[val].vals[i]); 5516 return 0; 5517 } 5518 5519 /* 5520 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5521 * amplifier to handle a 600 ohm load. 5522 */ 5523 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5524 { 5525 ca0113_mmio_gpio_set(codec, 1, val); 5526 5527 return 0; 5528 } 5529 5530 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5531 struct snd_ctl_elem_value *ucontrol) 5532 { 5533 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5534 hda_nid_t nid = get_amp_nid(kcontrol); 5535 hda_nid_t shared_nid = 0; 5536 bool effective; 5537 int ret = 0; 5538 struct ca0132_spec *spec = codec->spec; 5539 int auto_jack; 5540 5541 if (nid == VNID_HP_SEL) { 5542 auto_jack = 5543 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5544 if (!auto_jack) { 5545 if (ca0132_use_alt_functions(spec)) 5546 ca0132_alt_select_out(codec); 5547 else 5548 ca0132_select_out(codec); 5549 } 5550 return 1; 5551 } 5552 5553 if (nid == VNID_AMIC1_SEL) { 5554 auto_jack = 5555 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5556 if (!auto_jack) 5557 ca0132_select_mic(codec); 5558 return 1; 5559 } 5560 5561 if (nid == VNID_HP_ASEL) { 5562 if (ca0132_use_alt_functions(spec)) 5563 ca0132_alt_select_out(codec); 5564 else 5565 ca0132_select_out(codec); 5566 return 1; 5567 } 5568 5569 if (nid == VNID_AMIC1_ASEL) { 5570 ca0132_select_mic(codec); 5571 return 1; 5572 } 5573 5574 /* if effective conditions, then update hw immediately. */ 5575 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5576 if (effective) { 5577 int dir = get_amp_direction(kcontrol); 5578 int ch = get_amp_channels(kcontrol); 5579 unsigned long pval; 5580 5581 mutex_lock(&codec->control_mutex); 5582 pval = kcontrol->private_value; 5583 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5584 0, dir); 5585 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5586 kcontrol->private_value = pval; 5587 mutex_unlock(&codec->control_mutex); 5588 } 5589 5590 return ret; 5591 } 5592 /* End of control change helpers. */ 5593 5594 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5595 long idx) 5596 { 5597 snd_hda_power_up(codec); 5598 5599 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5600 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5601 5602 snd_hda_power_down(codec); 5603 } 5604 5605 /* 5606 * Below I've added controls to mess with the effect levels, I've only enabled 5607 * them on the Sound Blaster Z, but they would probably also work on the 5608 * Chromebook. I figured they were probably tuned specifically for it, and left 5609 * out for a reason. 5610 */ 5611 5612 /* Sets DSP effect level from the sliders above the controls */ 5613 5614 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5615 const unsigned int *lookup, int idx) 5616 { 5617 int i = 0; 5618 unsigned int y; 5619 /* 5620 * For X_BASS, req 2 is actually crossover freq instead of 5621 * effect level 5622 */ 5623 if (nid == X_BASS) 5624 y = 2; 5625 else 5626 y = 1; 5627 5628 snd_hda_power_up(codec); 5629 if (nid == XBASS_XOVER) { 5630 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5631 if (ca0132_effects[i].nid == X_BASS) 5632 break; 5633 5634 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5635 ca0132_effects[i].reqs[1], 5636 &(lookup[idx - 1]), sizeof(unsigned int)); 5637 } else { 5638 /* Find the actual effect structure */ 5639 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5640 if (nid == ca0132_effects[i].nid) 5641 break; 5642 5643 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5644 ca0132_effects[i].reqs[y], 5645 &(lookup[idx]), sizeof(unsigned int)); 5646 } 5647 5648 snd_hda_power_down(codec); 5649 5650 return 0; 5651 } 5652 5653 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5654 struct snd_ctl_elem_value *ucontrol) 5655 { 5656 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5657 struct ca0132_spec *spec = codec->spec; 5658 long *valp = ucontrol->value.integer.value; 5659 hda_nid_t nid = get_amp_nid(kcontrol); 5660 5661 if (nid == BASS_REDIRECTION_XOVER) 5662 *valp = spec->bass_redirect_xover_freq; 5663 else 5664 *valp = spec->xbass_xover_freq; 5665 5666 return 0; 5667 } 5668 5669 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5670 struct snd_ctl_elem_value *ucontrol) 5671 { 5672 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5673 struct ca0132_spec *spec = codec->spec; 5674 hda_nid_t nid = get_amp_nid(kcontrol); 5675 long *valp = ucontrol->value.integer.value; 5676 int idx = nid - OUT_EFFECT_START_NID; 5677 5678 *valp = spec->fx_ctl_val[idx]; 5679 return 0; 5680 } 5681 5682 /* 5683 * The X-bass crossover starts at 10hz, so the min is 1. The 5684 * frequency is set in multiples of 10. 5685 */ 5686 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5687 struct snd_ctl_elem_info *uinfo) 5688 { 5689 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5690 uinfo->count = 1; 5691 uinfo->value.integer.min = 1; 5692 uinfo->value.integer.max = 100; 5693 uinfo->value.integer.step = 1; 5694 5695 return 0; 5696 } 5697 5698 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5699 struct snd_ctl_elem_info *uinfo) 5700 { 5701 int chs = get_amp_channels(kcontrol); 5702 5703 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5704 uinfo->count = chs == 3 ? 2 : 1; 5705 uinfo->value.integer.min = 0; 5706 uinfo->value.integer.max = 100; 5707 uinfo->value.integer.step = 1; 5708 5709 return 0; 5710 } 5711 5712 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5713 struct snd_ctl_elem_value *ucontrol) 5714 { 5715 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5716 struct ca0132_spec *spec = codec->spec; 5717 hda_nid_t nid = get_amp_nid(kcontrol); 5718 long *valp = ucontrol->value.integer.value; 5719 long *cur_val; 5720 int idx; 5721 5722 if (nid == BASS_REDIRECTION_XOVER) 5723 cur_val = &spec->bass_redirect_xover_freq; 5724 else 5725 cur_val = &spec->xbass_xover_freq; 5726 5727 /* any change? */ 5728 if (*cur_val == *valp) 5729 return 0; 5730 5731 *cur_val = *valp; 5732 5733 idx = *valp; 5734 if (nid == BASS_REDIRECTION_XOVER) 5735 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5736 else 5737 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5738 5739 return 0; 5740 } 5741 5742 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5743 struct snd_ctl_elem_value *ucontrol) 5744 { 5745 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5746 struct ca0132_spec *spec = codec->spec; 5747 hda_nid_t nid = get_amp_nid(kcontrol); 5748 long *valp = ucontrol->value.integer.value; 5749 int idx; 5750 5751 idx = nid - EFFECT_START_NID; 5752 /* any change? */ 5753 if (spec->fx_ctl_val[idx] == *valp) 5754 return 0; 5755 5756 spec->fx_ctl_val[idx] = *valp; 5757 5758 idx = *valp; 5759 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5760 5761 return 0; 5762 } 5763 5764 5765 /* 5766 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5767 * only has off or full 30 dB, and didn't like making a volume slider that has 5768 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5769 */ 5770 #define MIC_BOOST_NUM_OF_STEPS 4 5771 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5772 5773 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5774 struct snd_ctl_elem_info *uinfo) 5775 { 5776 char *sfx = "dB"; 5777 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5778 5779 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5780 uinfo->count = 1; 5781 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5782 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5783 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5784 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5785 strcpy(uinfo->value.enumerated.name, namestr); 5786 return 0; 5787 } 5788 5789 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5790 struct snd_ctl_elem_value *ucontrol) 5791 { 5792 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5793 struct ca0132_spec *spec = codec->spec; 5794 5795 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5796 return 0; 5797 } 5798 5799 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5800 struct snd_ctl_elem_value *ucontrol) 5801 { 5802 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5803 struct ca0132_spec *spec = codec->spec; 5804 int sel = ucontrol->value.enumerated.item[0]; 5805 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5806 5807 if (sel >= items) 5808 return 0; 5809 5810 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5811 sel); 5812 5813 spec->mic_boost_enum_val = sel; 5814 5815 if (spec->in_enum_val != REAR_LINE_IN) 5816 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5817 5818 return 1; 5819 } 5820 5821 /* 5822 * Sound BlasterX AE-5 Headphone Gain Controls. 5823 */ 5824 #define AE5_HEADPHONE_GAIN_MAX 3 5825 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5826 struct snd_ctl_elem_info *uinfo) 5827 { 5828 char *sfx = " Ohms)"; 5829 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5830 5831 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5832 uinfo->count = 1; 5833 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5834 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5835 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5836 sprintf(namestr, "%s %s", 5837 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5838 sfx); 5839 strcpy(uinfo->value.enumerated.name, namestr); 5840 return 0; 5841 } 5842 5843 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5844 struct snd_ctl_elem_value *ucontrol) 5845 { 5846 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5847 struct ca0132_spec *spec = codec->spec; 5848 5849 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5850 return 0; 5851 } 5852 5853 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5854 struct snd_ctl_elem_value *ucontrol) 5855 { 5856 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5857 struct ca0132_spec *spec = codec->spec; 5858 int sel = ucontrol->value.enumerated.item[0]; 5859 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5860 5861 if (sel >= items) 5862 return 0; 5863 5864 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5865 sel); 5866 5867 spec->ae5_headphone_gain_val = sel; 5868 5869 if (spec->out_enum_val == HEADPHONE_OUT) 5870 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5871 5872 return 1; 5873 } 5874 5875 /* 5876 * Sound BlasterX AE-5 sound filter enumerated control. 5877 */ 5878 #define AE5_SOUND_FILTER_MAX 3 5879 5880 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5881 struct snd_ctl_elem_info *uinfo) 5882 { 5883 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5884 5885 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5886 uinfo->count = 1; 5887 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5888 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5889 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5890 sprintf(namestr, "%s", 5891 ae5_filter_presets[uinfo->value.enumerated.item].name); 5892 strcpy(uinfo->value.enumerated.name, namestr); 5893 return 0; 5894 } 5895 5896 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5897 struct snd_ctl_elem_value *ucontrol) 5898 { 5899 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5900 struct ca0132_spec *spec = codec->spec; 5901 5902 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5903 return 0; 5904 } 5905 5906 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5907 struct snd_ctl_elem_value *ucontrol) 5908 { 5909 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5910 struct ca0132_spec *spec = codec->spec; 5911 int sel = ucontrol->value.enumerated.item[0]; 5912 unsigned int items = AE5_SOUND_FILTER_MAX; 5913 5914 if (sel >= items) 5915 return 0; 5916 5917 codec_dbg(codec, "ae5_sound_filter: %s\n", 5918 ae5_filter_presets[sel].name); 5919 5920 spec->ae5_filter_val = sel; 5921 5922 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5923 ae5_filter_presets[sel].val); 5924 5925 return 1; 5926 } 5927 5928 /* 5929 * Input Select Control for alternative ca0132 codecs. This exists because 5930 * front microphone has no auto-detect, and we need a way to set the rear 5931 * as line-in 5932 */ 5933 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5934 struct snd_ctl_elem_info *uinfo) 5935 { 5936 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5937 uinfo->count = 1; 5938 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5939 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5940 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5941 strcpy(uinfo->value.enumerated.name, 5942 in_src_str[uinfo->value.enumerated.item]); 5943 return 0; 5944 } 5945 5946 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5947 struct snd_ctl_elem_value *ucontrol) 5948 { 5949 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5950 struct ca0132_spec *spec = codec->spec; 5951 5952 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5953 return 0; 5954 } 5955 5956 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5957 struct snd_ctl_elem_value *ucontrol) 5958 { 5959 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5960 struct ca0132_spec *spec = codec->spec; 5961 int sel = ucontrol->value.enumerated.item[0]; 5962 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5963 5964 /* 5965 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5966 * line-in. 5967 */ 5968 if (ca0132_quirk(spec) == QUIRK_AE7) 5969 items = 2; 5970 5971 if (sel >= items) 5972 return 0; 5973 5974 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5975 sel, in_src_str[sel]); 5976 5977 spec->in_enum_val = sel; 5978 5979 ca0132_alt_select_in(codec); 5980 5981 return 1; 5982 } 5983 5984 /* Sound Blaster Z Output Select Control */ 5985 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5986 struct snd_ctl_elem_info *uinfo) 5987 { 5988 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5989 uinfo->count = 1; 5990 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5991 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5992 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5993 strcpy(uinfo->value.enumerated.name, 5994 out_type_str[uinfo->value.enumerated.item]); 5995 return 0; 5996 } 5997 5998 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5999 struct snd_ctl_elem_value *ucontrol) 6000 { 6001 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6002 struct ca0132_spec *spec = codec->spec; 6003 6004 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6005 return 0; 6006 } 6007 6008 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6009 struct snd_ctl_elem_value *ucontrol) 6010 { 6011 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6012 struct ca0132_spec *spec = codec->spec; 6013 int sel = ucontrol->value.enumerated.item[0]; 6014 unsigned int items = NUM_OF_OUTPUTS; 6015 unsigned int auto_jack; 6016 6017 if (sel >= items) 6018 return 0; 6019 6020 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6021 sel, out_type_str[sel]); 6022 6023 spec->out_enum_val = sel; 6024 6025 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 6026 6027 if (!auto_jack) 6028 ca0132_alt_select_out(codec); 6029 6030 return 1; 6031 } 6032 6033 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6034 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6035 struct snd_ctl_elem_info *uinfo) 6036 { 6037 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6038 6039 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6040 uinfo->count = 1; 6041 uinfo->value.enumerated.items = items; 6042 if (uinfo->value.enumerated.item >= items) 6043 uinfo->value.enumerated.item = items - 1; 6044 strcpy(uinfo->value.enumerated.name, 6045 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6046 return 0; 6047 } 6048 6049 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6050 struct snd_ctl_elem_value *ucontrol) 6051 { 6052 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6053 struct ca0132_spec *spec = codec->spec; 6054 6055 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6056 return 0; 6057 } 6058 6059 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6060 struct snd_ctl_elem_value *ucontrol) 6061 { 6062 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6063 struct ca0132_spec *spec = codec->spec; 6064 int sel = ucontrol->value.enumerated.item[0]; 6065 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6066 6067 if (sel >= items) 6068 return 0; 6069 6070 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6071 sel, speaker_channel_cfgs[sel].name); 6072 6073 spec->channel_cfg_val = sel; 6074 6075 if (spec->out_enum_val == SPEAKER_OUT) 6076 ca0132_alt_select_out(codec); 6077 6078 return 1; 6079 } 6080 6081 /* 6082 * Smart Volume output setting control. Three different settings, Normal, 6083 * which takes the value from the smart volume slider. The two others, loud 6084 * and night, disregard the slider value and have uneditable values. 6085 */ 6086 #define NUM_OF_SVM_SETTINGS 3 6087 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6088 6089 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6090 struct snd_ctl_elem_info *uinfo) 6091 { 6092 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6093 uinfo->count = 1; 6094 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6095 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6096 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6097 strcpy(uinfo->value.enumerated.name, 6098 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6099 return 0; 6100 } 6101 6102 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6103 struct snd_ctl_elem_value *ucontrol) 6104 { 6105 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6106 struct ca0132_spec *spec = codec->spec; 6107 6108 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6109 return 0; 6110 } 6111 6112 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6113 struct snd_ctl_elem_value *ucontrol) 6114 { 6115 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6116 struct ca0132_spec *spec = codec->spec; 6117 int sel = ucontrol->value.enumerated.item[0]; 6118 unsigned int items = NUM_OF_SVM_SETTINGS; 6119 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6120 unsigned int tmp; 6121 6122 if (sel >= items) 6123 return 0; 6124 6125 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6126 sel, out_svm_set_enum_str[sel]); 6127 6128 spec->smart_volume_setting = sel; 6129 6130 switch (sel) { 6131 case 0: 6132 tmp = FLOAT_ZERO; 6133 break; 6134 case 1: 6135 tmp = FLOAT_ONE; 6136 break; 6137 case 2: 6138 tmp = FLOAT_TWO; 6139 break; 6140 default: 6141 tmp = FLOAT_ZERO; 6142 break; 6143 } 6144 /* Req 2 is the Smart Volume Setting req. */ 6145 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6146 ca0132_effects[idx].reqs[2], tmp); 6147 return 1; 6148 } 6149 6150 /* Sound Blaster Z EQ preset controls */ 6151 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6152 struct snd_ctl_elem_info *uinfo) 6153 { 6154 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6155 6156 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6157 uinfo->count = 1; 6158 uinfo->value.enumerated.items = items; 6159 if (uinfo->value.enumerated.item >= items) 6160 uinfo->value.enumerated.item = items - 1; 6161 strcpy(uinfo->value.enumerated.name, 6162 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6163 return 0; 6164 } 6165 6166 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6167 struct snd_ctl_elem_value *ucontrol) 6168 { 6169 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6170 struct ca0132_spec *spec = codec->spec; 6171 6172 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6173 return 0; 6174 } 6175 6176 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6177 struct snd_ctl_elem_value *ucontrol) 6178 { 6179 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6180 struct ca0132_spec *spec = codec->spec; 6181 int i, err = 0; 6182 int sel = ucontrol->value.enumerated.item[0]; 6183 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6184 6185 if (sel >= items) 6186 return 0; 6187 6188 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6189 ca0132_alt_eq_presets[sel].name); 6190 /* 6191 * Idx 0 is default. 6192 * Default needs to qualify with CrystalVoice state. 6193 */ 6194 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6195 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6196 ca0132_alt_eq_enum.reqs[i], 6197 ca0132_alt_eq_presets[sel].vals[i]); 6198 if (err < 0) 6199 break; 6200 } 6201 6202 if (err >= 0) 6203 spec->eq_preset_val = sel; 6204 6205 return 1; 6206 } 6207 6208 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6209 struct snd_ctl_elem_info *uinfo) 6210 { 6211 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6212 6213 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6214 uinfo->count = 1; 6215 uinfo->value.enumerated.items = items; 6216 if (uinfo->value.enumerated.item >= items) 6217 uinfo->value.enumerated.item = items - 1; 6218 strcpy(uinfo->value.enumerated.name, 6219 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6220 return 0; 6221 } 6222 6223 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6224 struct snd_ctl_elem_value *ucontrol) 6225 { 6226 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6227 struct ca0132_spec *spec = codec->spec; 6228 6229 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6230 return 0; 6231 } 6232 6233 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6234 struct snd_ctl_elem_value *ucontrol) 6235 { 6236 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6237 struct ca0132_spec *spec = codec->spec; 6238 int i, err = 0; 6239 int sel = ucontrol->value.enumerated.item[0]; 6240 6241 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6242 return 0; 6243 6244 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6245 sel, ca0132_voicefx_presets[sel].name); 6246 6247 /* 6248 * Idx 0 is default. 6249 * Default needs to qualify with CrystalVoice state. 6250 */ 6251 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6252 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6253 ca0132_voicefx.reqs[i], 6254 ca0132_voicefx_presets[sel].vals[i]); 6255 if (err < 0) 6256 break; 6257 } 6258 6259 if (err >= 0) { 6260 spec->voicefx_val = sel; 6261 /* enable voice fx */ 6262 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6263 } 6264 6265 return 1; 6266 } 6267 6268 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6269 struct snd_ctl_elem_value *ucontrol) 6270 { 6271 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6272 struct ca0132_spec *spec = codec->spec; 6273 hda_nid_t nid = get_amp_nid(kcontrol); 6274 int ch = get_amp_channels(kcontrol); 6275 long *valp = ucontrol->value.integer.value; 6276 6277 /* vnode */ 6278 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6279 if (ch & 1) { 6280 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6281 valp++; 6282 } 6283 if (ch & 2) { 6284 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6285 valp++; 6286 } 6287 return 0; 6288 } 6289 6290 /* effects, include PE and CrystalVoice */ 6291 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6292 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6293 return 0; 6294 } 6295 6296 /* mic boost */ 6297 if (nid == spec->input_pins[0]) { 6298 *valp = spec->cur_mic_boost; 6299 return 0; 6300 } 6301 6302 if (nid == ZXR_HEADPHONE_GAIN) { 6303 *valp = spec->zxr_gain_set; 6304 return 0; 6305 } 6306 6307 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6308 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6309 return 0; 6310 } 6311 6312 if (nid == BASS_REDIRECTION) { 6313 *valp = spec->bass_redirection_val; 6314 return 0; 6315 } 6316 6317 return 0; 6318 } 6319 6320 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6321 struct snd_ctl_elem_value *ucontrol) 6322 { 6323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6324 struct ca0132_spec *spec = codec->spec; 6325 hda_nid_t nid = get_amp_nid(kcontrol); 6326 int ch = get_amp_channels(kcontrol); 6327 long *valp = ucontrol->value.integer.value; 6328 int changed = 1; 6329 6330 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6331 nid, *valp); 6332 6333 snd_hda_power_up(codec); 6334 /* vnode */ 6335 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6336 if (ch & 1) { 6337 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6338 valp++; 6339 } 6340 if (ch & 2) { 6341 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6342 valp++; 6343 } 6344 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6345 goto exit; 6346 } 6347 6348 /* PE */ 6349 if (nid == PLAY_ENHANCEMENT) { 6350 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6351 changed = ca0132_pe_switch_set(codec); 6352 goto exit; 6353 } 6354 6355 /* CrystalVoice */ 6356 if (nid == CRYSTAL_VOICE) { 6357 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6358 changed = ca0132_cvoice_switch_set(codec); 6359 goto exit; 6360 } 6361 6362 /* out and in effects */ 6363 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6364 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6365 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6366 changed = ca0132_effects_set(codec, nid, *valp); 6367 goto exit; 6368 } 6369 6370 /* mic boost */ 6371 if (nid == spec->input_pins[0]) { 6372 spec->cur_mic_boost = *valp; 6373 if (ca0132_use_alt_functions(spec)) { 6374 if (spec->in_enum_val != REAR_LINE_IN) 6375 changed = ca0132_mic_boost_set(codec, *valp); 6376 } else { 6377 /* Mic boost does not apply to Digital Mic */ 6378 if (spec->cur_mic_type != DIGITAL_MIC) 6379 changed = ca0132_mic_boost_set(codec, *valp); 6380 } 6381 6382 goto exit; 6383 } 6384 6385 if (nid == ZXR_HEADPHONE_GAIN) { 6386 spec->zxr_gain_set = *valp; 6387 if (spec->cur_out_type == HEADPHONE_OUT) 6388 changed = zxr_headphone_gain_set(codec, *valp); 6389 else 6390 changed = 0; 6391 6392 goto exit; 6393 } 6394 6395 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6396 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6397 if (spec->cur_out_type == SPEAKER_OUT) 6398 ca0132_alt_set_full_range_speaker(codec); 6399 6400 changed = 0; 6401 } 6402 6403 if (nid == BASS_REDIRECTION) { 6404 spec->bass_redirection_val = *valp; 6405 if (spec->cur_out_type == SPEAKER_OUT) 6406 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6407 6408 changed = 0; 6409 } 6410 6411 exit: 6412 snd_hda_power_down(codec); 6413 return changed; 6414 } 6415 6416 /* 6417 * Volume related 6418 */ 6419 /* 6420 * Sets the internal DSP decibel level to match the DAC for output, and the 6421 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6422 * all alternative codecs set DSP playback volume. 6423 */ 6424 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6425 { 6426 struct ca0132_spec *spec = codec->spec; 6427 unsigned int dsp_dir; 6428 unsigned int lookup_val; 6429 6430 if (nid == VNID_SPK) 6431 dsp_dir = DSP_VOL_OUT; 6432 else 6433 dsp_dir = DSP_VOL_IN; 6434 6435 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6436 6437 dspio_set_uint_param(codec, 6438 ca0132_alt_vol_ctls[dsp_dir].mid, 6439 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6440 float_vol_db_lookup[lookup_val]); 6441 6442 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6443 6444 dspio_set_uint_param(codec, 6445 ca0132_alt_vol_ctls[dsp_dir].mid, 6446 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6447 float_vol_db_lookup[lookup_val]); 6448 6449 dspio_set_uint_param(codec, 6450 ca0132_alt_vol_ctls[dsp_dir].mid, 6451 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6452 } 6453 6454 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6455 struct snd_ctl_elem_info *uinfo) 6456 { 6457 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6458 struct ca0132_spec *spec = codec->spec; 6459 hda_nid_t nid = get_amp_nid(kcontrol); 6460 int ch = get_amp_channels(kcontrol); 6461 int dir = get_amp_direction(kcontrol); 6462 unsigned long pval; 6463 int err; 6464 6465 switch (nid) { 6466 case VNID_SPK: 6467 /* follow shared_out info */ 6468 nid = spec->shared_out_nid; 6469 mutex_lock(&codec->control_mutex); 6470 pval = kcontrol->private_value; 6471 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6472 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6473 kcontrol->private_value = pval; 6474 mutex_unlock(&codec->control_mutex); 6475 break; 6476 case VNID_MIC: 6477 /* follow shared_mic info */ 6478 nid = spec->shared_mic_nid; 6479 mutex_lock(&codec->control_mutex); 6480 pval = kcontrol->private_value; 6481 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6482 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6483 kcontrol->private_value = pval; 6484 mutex_unlock(&codec->control_mutex); 6485 break; 6486 default: 6487 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6488 } 6489 return err; 6490 } 6491 6492 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6493 struct snd_ctl_elem_value *ucontrol) 6494 { 6495 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6496 struct ca0132_spec *spec = codec->spec; 6497 hda_nid_t nid = get_amp_nid(kcontrol); 6498 int ch = get_amp_channels(kcontrol); 6499 long *valp = ucontrol->value.integer.value; 6500 6501 /* store the left and right volume */ 6502 if (ch & 1) { 6503 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6504 valp++; 6505 } 6506 if (ch & 2) { 6507 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6508 valp++; 6509 } 6510 return 0; 6511 } 6512 6513 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6514 struct snd_ctl_elem_value *ucontrol) 6515 { 6516 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6517 struct ca0132_spec *spec = codec->spec; 6518 hda_nid_t nid = get_amp_nid(kcontrol); 6519 int ch = get_amp_channels(kcontrol); 6520 long *valp = ucontrol->value.integer.value; 6521 hda_nid_t shared_nid = 0; 6522 bool effective; 6523 int changed = 1; 6524 6525 /* store the left and right volume */ 6526 if (ch & 1) { 6527 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6528 valp++; 6529 } 6530 if (ch & 2) { 6531 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6532 valp++; 6533 } 6534 6535 /* if effective conditions, then update hw immediately. */ 6536 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6537 if (effective) { 6538 int dir = get_amp_direction(kcontrol); 6539 unsigned long pval; 6540 6541 snd_hda_power_up(codec); 6542 mutex_lock(&codec->control_mutex); 6543 pval = kcontrol->private_value; 6544 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6545 0, dir); 6546 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6547 kcontrol->private_value = pval; 6548 mutex_unlock(&codec->control_mutex); 6549 snd_hda_power_down(codec); 6550 } 6551 6552 return changed; 6553 } 6554 6555 /* 6556 * This function is the same as the one above, because using an if statement 6557 * inside of the above volume control for the DSP volume would cause too much 6558 * lag. This is a lot more smooth. 6559 */ 6560 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6561 struct snd_ctl_elem_value *ucontrol) 6562 { 6563 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6564 struct ca0132_spec *spec = codec->spec; 6565 hda_nid_t nid = get_amp_nid(kcontrol); 6566 int ch = get_amp_channels(kcontrol); 6567 long *valp = ucontrol->value.integer.value; 6568 hda_nid_t vnid = 0; 6569 int changed; 6570 6571 switch (nid) { 6572 case 0x02: 6573 vnid = VNID_SPK; 6574 break; 6575 case 0x07: 6576 vnid = VNID_MIC; 6577 break; 6578 } 6579 6580 /* store the left and right volume */ 6581 if (ch & 1) { 6582 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6583 valp++; 6584 } 6585 if (ch & 2) { 6586 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6587 valp++; 6588 } 6589 6590 snd_hda_power_up(codec); 6591 ca0132_alt_dsp_volume_put(codec, vnid); 6592 mutex_lock(&codec->control_mutex); 6593 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6594 mutex_unlock(&codec->control_mutex); 6595 snd_hda_power_down(codec); 6596 6597 return changed; 6598 } 6599 6600 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6601 unsigned int size, unsigned int __user *tlv) 6602 { 6603 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6604 struct ca0132_spec *spec = codec->spec; 6605 hda_nid_t nid = get_amp_nid(kcontrol); 6606 int ch = get_amp_channels(kcontrol); 6607 int dir = get_amp_direction(kcontrol); 6608 unsigned long pval; 6609 int err; 6610 6611 switch (nid) { 6612 case VNID_SPK: 6613 /* follow shared_out tlv */ 6614 nid = spec->shared_out_nid; 6615 mutex_lock(&codec->control_mutex); 6616 pval = kcontrol->private_value; 6617 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6618 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6619 kcontrol->private_value = pval; 6620 mutex_unlock(&codec->control_mutex); 6621 break; 6622 case VNID_MIC: 6623 /* follow shared_mic tlv */ 6624 nid = spec->shared_mic_nid; 6625 mutex_lock(&codec->control_mutex); 6626 pval = kcontrol->private_value; 6627 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6628 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6629 kcontrol->private_value = pval; 6630 mutex_unlock(&codec->control_mutex); 6631 break; 6632 default: 6633 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6634 } 6635 return err; 6636 } 6637 6638 /* Add volume slider control for effect level */ 6639 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6640 const char *pfx, int dir) 6641 { 6642 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6643 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6644 struct snd_kcontrol_new knew = 6645 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6646 6647 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6648 6649 knew.tlv.c = NULL; 6650 6651 switch (nid) { 6652 case XBASS_XOVER: 6653 knew.info = ca0132_alt_xbass_xover_slider_info; 6654 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6655 knew.put = ca0132_alt_xbass_xover_slider_put; 6656 break; 6657 default: 6658 knew.info = ca0132_alt_effect_slider_info; 6659 knew.get = ca0132_alt_slider_ctl_get; 6660 knew.put = ca0132_alt_effect_slider_put; 6661 knew.private_value = 6662 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6663 break; 6664 } 6665 6666 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6667 } 6668 6669 /* 6670 * Added FX: prefix for the alternative codecs, because otherwise the surround 6671 * effect would conflict with the Surround sound volume control. Also seems more 6672 * clear as to what the switches do. Left alone for others. 6673 */ 6674 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6675 const char *pfx, int dir) 6676 { 6677 struct ca0132_spec *spec = codec->spec; 6678 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6679 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6680 struct snd_kcontrol_new knew = 6681 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6682 /* If using alt_controls, add FX: prefix. But, don't add FX: 6683 * prefix to OutFX or InFX enable controls. 6684 */ 6685 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6686 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6687 else 6688 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6689 6690 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6691 } 6692 6693 static int add_voicefx(struct hda_codec *codec) 6694 { 6695 struct snd_kcontrol_new knew = 6696 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6697 VOICEFX, 1, 0, HDA_INPUT); 6698 knew.info = ca0132_voicefx_info; 6699 knew.get = ca0132_voicefx_get; 6700 knew.put = ca0132_voicefx_put; 6701 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6702 } 6703 6704 /* Create the EQ Preset control */ 6705 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6706 { 6707 struct snd_kcontrol_new knew = 6708 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6709 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6710 knew.info = ca0132_alt_eq_preset_info; 6711 knew.get = ca0132_alt_eq_preset_get; 6712 knew.put = ca0132_alt_eq_preset_put; 6713 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6714 snd_ctl_new1(&knew, codec)); 6715 } 6716 6717 /* 6718 * Add enumerated control for the three different settings of the smart volume 6719 * output effect. Normal just uses the slider value, and loud and night are 6720 * their own things that ignore that value. 6721 */ 6722 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6723 { 6724 struct snd_kcontrol_new knew = 6725 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6726 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6727 knew.info = ca0132_alt_svm_setting_info; 6728 knew.get = ca0132_alt_svm_setting_get; 6729 knew.put = ca0132_alt_svm_setting_put; 6730 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6731 snd_ctl_new1(&knew, codec)); 6732 6733 } 6734 6735 /* 6736 * Create an Output Select enumerated control for codecs with surround 6737 * out capabilities. 6738 */ 6739 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6740 { 6741 struct snd_kcontrol_new knew = 6742 HDA_CODEC_MUTE_MONO("Output Select", 6743 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6744 knew.info = ca0132_alt_output_select_get_info; 6745 knew.get = ca0132_alt_output_select_get; 6746 knew.put = ca0132_alt_output_select_put; 6747 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6748 snd_ctl_new1(&knew, codec)); 6749 } 6750 6751 /* 6752 * Add a control for selecting channel count on speaker output. Setting this 6753 * allows the DSP to do bass redirection and channel upmixing on surround 6754 * configurations. 6755 */ 6756 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6757 { 6758 struct snd_kcontrol_new knew = 6759 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6760 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6761 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6762 knew.get = ca0132_alt_speaker_channel_cfg_get; 6763 knew.put = ca0132_alt_speaker_channel_cfg_put; 6764 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6765 snd_ctl_new1(&knew, codec)); 6766 } 6767 6768 /* 6769 * Full range front stereo and rear surround switches. When these are set to 6770 * full range, the lower frequencies from these channels are no longer 6771 * redirected to the LFE channel. 6772 */ 6773 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6774 { 6775 struct snd_kcontrol_new knew = 6776 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6777 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6778 6779 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6780 snd_ctl_new1(&knew, codec)); 6781 } 6782 6783 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6784 { 6785 struct snd_kcontrol_new knew = 6786 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6787 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6788 6789 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6790 snd_ctl_new1(&knew, codec)); 6791 } 6792 6793 /* 6794 * Bass redirection redirects audio below the crossover frequency to the LFE 6795 * channel on speakers that are set as not being full-range. On configurations 6796 * without an LFE channel, it does nothing. Bass redirection seems to be the 6797 * replacement for X-Bass on configurations with an LFE channel. 6798 */ 6799 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6800 { 6801 const char *namestr = "Bass Redirection Crossover"; 6802 struct snd_kcontrol_new knew = 6803 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6804 HDA_OUTPUT); 6805 6806 knew.tlv.c = NULL; 6807 knew.info = ca0132_alt_xbass_xover_slider_info; 6808 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6809 knew.put = ca0132_alt_xbass_xover_slider_put; 6810 6811 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6812 snd_ctl_new1(&knew, codec)); 6813 } 6814 6815 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6816 { 6817 const char *namestr = "Bass Redirection"; 6818 struct snd_kcontrol_new knew = 6819 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6820 HDA_OUTPUT); 6821 6822 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6823 snd_ctl_new1(&knew, codec)); 6824 } 6825 6826 /* 6827 * Create an Input Source enumerated control for the alternate ca0132 codecs 6828 * because the front microphone has no auto-detect, and Line-in has to be set 6829 * somehow. 6830 */ 6831 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6832 { 6833 struct snd_kcontrol_new knew = 6834 HDA_CODEC_MUTE_MONO("Input Source", 6835 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6836 knew.info = ca0132_alt_input_source_info; 6837 knew.get = ca0132_alt_input_source_get; 6838 knew.put = ca0132_alt_input_source_put; 6839 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6840 snd_ctl_new1(&knew, codec)); 6841 } 6842 6843 /* 6844 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6845 * more control than the original mic boost, which is either full 30dB or off. 6846 */ 6847 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6848 { 6849 struct snd_kcontrol_new knew = 6850 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6851 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6852 knew.info = ca0132_alt_mic_boost_info; 6853 knew.get = ca0132_alt_mic_boost_get; 6854 knew.put = ca0132_alt_mic_boost_put; 6855 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6856 snd_ctl_new1(&knew, codec)); 6857 6858 } 6859 6860 /* 6861 * Add headphone gain enumerated control for the AE-5. This switches between 6862 * three modes, low, medium, and high. When non-headphone outputs are selected, 6863 * it is automatically set to high. This is the same behavior as Windows. 6864 */ 6865 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6866 { 6867 struct snd_kcontrol_new knew = 6868 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6869 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6870 knew.info = ae5_headphone_gain_info; 6871 knew.get = ae5_headphone_gain_get; 6872 knew.put = ae5_headphone_gain_put; 6873 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6874 snd_ctl_new1(&knew, codec)); 6875 } 6876 6877 /* 6878 * Add sound filter enumerated control for the AE-5. This adds three different 6879 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6880 * read into it, it changes the DAC's interpolation filter. 6881 */ 6882 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6883 { 6884 struct snd_kcontrol_new knew = 6885 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6886 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6887 knew.info = ae5_sound_filter_info; 6888 knew.get = ae5_sound_filter_get; 6889 knew.put = ae5_sound_filter_put; 6890 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6891 snd_ctl_new1(&knew, codec)); 6892 } 6893 6894 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6895 { 6896 struct snd_kcontrol_new knew = 6897 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6898 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6899 6900 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6901 snd_ctl_new1(&knew, codec)); 6902 } 6903 6904 /* 6905 * Need to create follower controls for the alternate codecs that have surround 6906 * capabilities. 6907 */ 6908 static const char * const ca0132_alt_follower_pfxs[] = { 6909 "Front", "Surround", "Center", "LFE", NULL, 6910 }; 6911 6912 /* 6913 * Also need special channel map, because the default one is incorrect. 6914 * I think this has to do with the pin for rear surround being 0x11, 6915 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6916 */ 6917 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6918 { .channels = 2, 6919 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6920 { .channels = 4, 6921 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6922 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6923 { .channels = 6, 6924 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6925 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6926 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6927 { } 6928 }; 6929 6930 /* Add the correct chmap for streams with 6 channels. */ 6931 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6932 { 6933 int err = 0; 6934 struct hda_pcm *pcm; 6935 6936 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6937 struct hda_pcm_stream *hinfo = 6938 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6939 struct snd_pcm_chmap *chmap; 6940 const struct snd_pcm_chmap_elem *elem; 6941 6942 elem = ca0132_alt_chmaps; 6943 if (hinfo->channels_max == 6) { 6944 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6945 SNDRV_PCM_STREAM_PLAYBACK, 6946 elem, hinfo->channels_max, 0, &chmap); 6947 if (err < 0) 6948 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6949 } 6950 } 6951 } 6952 6953 /* 6954 * When changing Node IDs for Mixer Controls below, make sure to update 6955 * Node IDs in ca0132_config() as well. 6956 */ 6957 static const struct snd_kcontrol_new ca0132_mixer[] = { 6958 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6959 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6960 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6961 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6962 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6963 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6964 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6965 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6966 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6967 0x12, 1, HDA_INPUT), 6968 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6969 VNID_HP_SEL, 1, HDA_OUTPUT), 6970 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6971 VNID_AMIC1_SEL, 1, HDA_INPUT), 6972 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6973 VNID_HP_ASEL, 1, HDA_OUTPUT), 6974 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6975 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6976 { } /* end */ 6977 }; 6978 6979 /* 6980 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6981 * surround controls. Also sets both the Front Playback and Capture Volume 6982 * controls to alt so they set the DSP's decibel level. 6983 */ 6984 static const struct snd_kcontrol_new desktop_mixer[] = { 6985 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6986 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6987 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6988 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6989 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6990 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6991 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6992 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6993 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6994 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6995 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6996 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6997 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6998 VNID_HP_ASEL, 1, HDA_OUTPUT), 6999 { } /* end */ 7000 }; 7001 7002 /* 7003 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7004 * because it doesn't set decibel levels for the DSP for capture. 7005 */ 7006 static const struct snd_kcontrol_new r3di_mixer[] = { 7007 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7008 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7009 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7010 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7011 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7012 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7013 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7014 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7015 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7016 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7017 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7018 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7019 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7020 VNID_HP_ASEL, 1, HDA_OUTPUT), 7021 { } /* end */ 7022 }; 7023 7024 static int ca0132_build_controls(struct hda_codec *codec) 7025 { 7026 struct ca0132_spec *spec = codec->spec; 7027 int i, num_fx, num_sliders; 7028 int err = 0; 7029 7030 /* Add Mixer controls */ 7031 for (i = 0; i < spec->num_mixers; i++) { 7032 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7033 if (err < 0) 7034 return err; 7035 } 7036 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7037 if (ca0132_use_alt_functions(spec)) { 7038 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7039 spec->tlv); 7040 snd_hda_add_vmaster(codec, "Master Playback Volume", 7041 spec->tlv, ca0132_alt_follower_pfxs, 7042 "Playback Volume", 0); 7043 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7044 NULL, ca0132_alt_follower_pfxs, 7045 "Playback Switch", 7046 true, 0, &spec->vmaster_mute.sw_kctl); 7047 if (err < 0) 7048 return err; 7049 } 7050 7051 /* Add in and out effects controls. 7052 * VoiceFX, PE and CrystalVoice are added separately. 7053 */ 7054 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7055 for (i = 0; i < num_fx; i++) { 7056 /* Desktop cards break if Echo Cancellation is used. */ 7057 if (ca0132_use_pci_mmio(spec)) { 7058 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7059 OUT_EFFECTS_COUNT)) 7060 continue; 7061 } 7062 7063 err = add_fx_switch(codec, ca0132_effects[i].nid, 7064 ca0132_effects[i].name, 7065 ca0132_effects[i].direct); 7066 if (err < 0) 7067 return err; 7068 } 7069 /* 7070 * If codec has use_alt_controls set to true, add effect level sliders, 7071 * EQ presets, and Smart Volume presets. Also, change names to add FX 7072 * prefix, and change PlayEnhancement and CrystalVoice to match. 7073 */ 7074 if (ca0132_use_alt_controls(spec)) { 7075 err = ca0132_alt_add_svm_enum(codec); 7076 if (err < 0) 7077 return err; 7078 7079 err = add_ca0132_alt_eq_presets(codec); 7080 if (err < 0) 7081 return err; 7082 7083 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7084 "Enable OutFX", 0); 7085 if (err < 0) 7086 return err; 7087 7088 err = add_fx_switch(codec, CRYSTAL_VOICE, 7089 "Enable InFX", 1); 7090 if (err < 0) 7091 return err; 7092 7093 num_sliders = OUT_EFFECTS_COUNT - 1; 7094 for (i = 0; i < num_sliders; i++) { 7095 err = ca0132_alt_add_effect_slider(codec, 7096 ca0132_effects[i].nid, 7097 ca0132_effects[i].name, 7098 ca0132_effects[i].direct); 7099 if (err < 0) 7100 return err; 7101 } 7102 7103 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7104 "X-Bass Crossover", EFX_DIR_OUT); 7105 7106 if (err < 0) 7107 return err; 7108 } else { 7109 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7110 "PlayEnhancement", 0); 7111 if (err < 0) 7112 return err; 7113 7114 err = add_fx_switch(codec, CRYSTAL_VOICE, 7115 "CrystalVoice", 1); 7116 if (err < 0) 7117 return err; 7118 } 7119 err = add_voicefx(codec); 7120 if (err < 0) 7121 return err; 7122 7123 /* 7124 * If the codec uses alt_functions, you need the enumerated controls 7125 * to select the new outputs and inputs, plus add the new mic boost 7126 * setting control. 7127 */ 7128 if (ca0132_use_alt_functions(spec)) { 7129 err = ca0132_alt_add_output_enum(codec); 7130 if (err < 0) 7131 return err; 7132 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7133 if (err < 0) 7134 return err; 7135 err = ca0132_alt_add_front_full_range_switch(codec); 7136 if (err < 0) 7137 return err; 7138 err = ca0132_alt_add_rear_full_range_switch(codec); 7139 if (err < 0) 7140 return err; 7141 err = ca0132_alt_add_bass_redirection_crossover(codec); 7142 if (err < 0) 7143 return err; 7144 err = ca0132_alt_add_bass_redirection_switch(codec); 7145 if (err < 0) 7146 return err; 7147 err = ca0132_alt_add_mic_boost_enum(codec); 7148 if (err < 0) 7149 return err; 7150 /* 7151 * ZxR only has microphone input, there is no front panel 7152 * header on the card, and aux-in is handled by the DBPro board. 7153 */ 7154 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7155 err = ca0132_alt_add_input_enum(codec); 7156 if (err < 0) 7157 return err; 7158 } 7159 } 7160 7161 switch (ca0132_quirk(spec)) { 7162 case QUIRK_AE5: 7163 case QUIRK_AE7: 7164 err = ae5_add_headphone_gain_enum(codec); 7165 if (err < 0) 7166 return err; 7167 err = ae5_add_sound_filter_enum(codec); 7168 if (err < 0) 7169 return err; 7170 break; 7171 case QUIRK_ZXR: 7172 err = zxr_add_headphone_gain_switch(codec); 7173 if (err < 0) 7174 return err; 7175 break; 7176 default: 7177 break; 7178 } 7179 7180 #ifdef ENABLE_TUNING_CONTROLS 7181 add_tuning_ctls(codec); 7182 #endif 7183 7184 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7185 if (err < 0) 7186 return err; 7187 7188 if (spec->dig_out) { 7189 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7190 spec->dig_out); 7191 if (err < 0) 7192 return err; 7193 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7194 if (err < 0) 7195 return err; 7196 /* spec->multiout.share_spdif = 1; */ 7197 } 7198 7199 if (spec->dig_in) { 7200 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7201 if (err < 0) 7202 return err; 7203 } 7204 7205 if (ca0132_use_alt_functions(spec)) 7206 ca0132_alt_add_chmap_ctls(codec); 7207 7208 return 0; 7209 } 7210 7211 static int dbpro_build_controls(struct hda_codec *codec) 7212 { 7213 struct ca0132_spec *spec = codec->spec; 7214 int err = 0; 7215 7216 if (spec->dig_out) { 7217 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7218 spec->dig_out); 7219 if (err < 0) 7220 return err; 7221 } 7222 7223 if (spec->dig_in) { 7224 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7225 if (err < 0) 7226 return err; 7227 } 7228 7229 return 0; 7230 } 7231 7232 /* 7233 * PCM 7234 */ 7235 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7236 .substreams = 1, 7237 .channels_min = 2, 7238 .channels_max = 6, 7239 .ops = { 7240 .prepare = ca0132_playback_pcm_prepare, 7241 .cleanup = ca0132_playback_pcm_cleanup, 7242 .get_delay = ca0132_playback_pcm_delay, 7243 }, 7244 }; 7245 7246 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7247 .substreams = 1, 7248 .channels_min = 2, 7249 .channels_max = 2, 7250 .ops = { 7251 .prepare = ca0132_capture_pcm_prepare, 7252 .cleanup = ca0132_capture_pcm_cleanup, 7253 .get_delay = ca0132_capture_pcm_delay, 7254 }, 7255 }; 7256 7257 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7258 .substreams = 1, 7259 .channels_min = 2, 7260 .channels_max = 2, 7261 .ops = { 7262 .open = ca0132_dig_playback_pcm_open, 7263 .close = ca0132_dig_playback_pcm_close, 7264 .prepare = ca0132_dig_playback_pcm_prepare, 7265 .cleanup = ca0132_dig_playback_pcm_cleanup 7266 }, 7267 }; 7268 7269 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7270 .substreams = 1, 7271 .channels_min = 2, 7272 .channels_max = 2, 7273 }; 7274 7275 static int ca0132_build_pcms(struct hda_codec *codec) 7276 { 7277 struct ca0132_spec *spec = codec->spec; 7278 struct hda_pcm *info; 7279 7280 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7281 if (!info) 7282 return -ENOMEM; 7283 if (ca0132_use_alt_functions(spec)) { 7284 info->own_chmap = true; 7285 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7286 = ca0132_alt_chmaps; 7287 } 7288 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7289 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7290 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7291 spec->multiout.max_channels; 7292 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7293 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7294 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7295 7296 /* With the DSP enabled, desktops don't use this ADC. */ 7297 if (!ca0132_use_alt_functions(spec)) { 7298 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7299 if (!info) 7300 return -ENOMEM; 7301 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7302 ca0132_pcm_analog_capture; 7303 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7304 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7305 } 7306 7307 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7308 if (!info) 7309 return -ENOMEM; 7310 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7311 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7312 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7313 7314 if (!spec->dig_out && !spec->dig_in) 7315 return 0; 7316 7317 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7318 if (!info) 7319 return -ENOMEM; 7320 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7321 if (spec->dig_out) { 7322 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7323 ca0132_pcm_digital_playback; 7324 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7325 } 7326 if (spec->dig_in) { 7327 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7328 ca0132_pcm_digital_capture; 7329 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7330 } 7331 7332 return 0; 7333 } 7334 7335 static int dbpro_build_pcms(struct hda_codec *codec) 7336 { 7337 struct ca0132_spec *spec = codec->spec; 7338 struct hda_pcm *info; 7339 7340 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7341 if (!info) 7342 return -ENOMEM; 7343 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7344 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7345 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7346 7347 7348 if (!spec->dig_out && !spec->dig_in) 7349 return 0; 7350 7351 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7352 if (!info) 7353 return -ENOMEM; 7354 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7355 if (spec->dig_out) { 7356 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7357 ca0132_pcm_digital_playback; 7358 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7359 } 7360 if (spec->dig_in) { 7361 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7362 ca0132_pcm_digital_capture; 7363 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7364 } 7365 7366 return 0; 7367 } 7368 7369 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7370 { 7371 if (pin) { 7372 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7373 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7374 snd_hda_codec_write(codec, pin, 0, 7375 AC_VERB_SET_AMP_GAIN_MUTE, 7376 AMP_OUT_UNMUTE); 7377 } 7378 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7379 snd_hda_codec_write(codec, dac, 0, 7380 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7381 } 7382 7383 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7384 { 7385 if (pin) { 7386 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7387 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7388 snd_hda_codec_write(codec, pin, 0, 7389 AC_VERB_SET_AMP_GAIN_MUTE, 7390 AMP_IN_UNMUTE(0)); 7391 } 7392 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7393 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7394 AMP_IN_UNMUTE(0)); 7395 7396 /* init to 0 dB and unmute. */ 7397 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7398 HDA_AMP_VOLMASK, 0x5a); 7399 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7400 HDA_AMP_MUTE, 0); 7401 } 7402 } 7403 7404 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7405 { 7406 unsigned int caps; 7407 7408 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7409 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7410 snd_hda_override_amp_caps(codec, nid, dir, caps); 7411 } 7412 7413 /* 7414 * Switch between Digital built-in mic and analog mic. 7415 */ 7416 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7417 { 7418 struct ca0132_spec *spec = codec->spec; 7419 unsigned int tmp; 7420 u8 val; 7421 unsigned int oldval; 7422 7423 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7424 7425 oldval = stop_mic1(codec); 7426 ca0132_set_vipsource(codec, 0); 7427 if (enable) { 7428 /* set DMic input as 2-ch */ 7429 tmp = FLOAT_TWO; 7430 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7431 7432 val = spec->dmic_ctl; 7433 val |= 0x80; 7434 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7435 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7436 7437 if (!(spec->dmic_ctl & 0x20)) 7438 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7439 } else { 7440 /* set AMic input as mono */ 7441 tmp = FLOAT_ONE; 7442 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7443 7444 val = spec->dmic_ctl; 7445 /* clear bit7 and bit5 to disable dmic */ 7446 val &= 0x5f; 7447 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7448 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7449 7450 if (!(spec->dmic_ctl & 0x20)) 7451 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7452 } 7453 ca0132_set_vipsource(codec, 1); 7454 resume_mic1(codec, oldval); 7455 } 7456 7457 /* 7458 * Initialization for Digital Mic. 7459 */ 7460 static void ca0132_init_dmic(struct hda_codec *codec) 7461 { 7462 struct ca0132_spec *spec = codec->spec; 7463 u8 val; 7464 7465 /* Setup Digital Mic here, but don't enable. 7466 * Enable based on jack detect. 7467 */ 7468 7469 /* MCLK uses MPIO1, set to enable. 7470 * Bit 2-0: MPIO select 7471 * Bit 3: set to disable 7472 * Bit 7-4: reserved 7473 */ 7474 val = 0x01; 7475 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7476 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7477 7478 /* Data1 uses MPIO3. Data2 not use 7479 * Bit 2-0: Data1 MPIO select 7480 * Bit 3: set disable Data1 7481 * Bit 6-4: Data2 MPIO select 7482 * Bit 7: set disable Data2 7483 */ 7484 val = 0x83; 7485 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7486 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7487 7488 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7489 * Bit 3-0: Channel mask 7490 * Bit 4: set for 48KHz, clear for 32KHz 7491 * Bit 5: mode 7492 * Bit 6: set to select Data2, clear for Data1 7493 * Bit 7: set to enable DMic, clear for AMic 7494 */ 7495 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7496 val = 0x33; 7497 else 7498 val = 0x23; 7499 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7500 spec->dmic_ctl = val; 7501 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7502 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7503 } 7504 7505 /* 7506 * Initialization for Analog Mic 2 7507 */ 7508 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7509 { 7510 struct ca0132_spec *spec = codec->spec; 7511 7512 mutex_lock(&spec->chipio_mutex); 7513 7514 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7515 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7516 7517 mutex_unlock(&spec->chipio_mutex); 7518 } 7519 7520 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7521 { 7522 struct ca0132_spec *spec = codec->spec; 7523 int i; 7524 7525 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7526 snd_hda_codec_update_widgets(codec); 7527 7528 for (i = 0; i < spec->multiout.num_dacs; i++) 7529 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7530 7531 for (i = 0; i < spec->num_outputs; i++) 7532 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7533 7534 for (i = 0; i < spec->num_inputs; i++) { 7535 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7536 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7537 } 7538 } 7539 7540 7541 /* If there is an active channel for some reason, find it and free it. */ 7542 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7543 { 7544 unsigned int i, tmp; 7545 int status; 7546 7547 /* Read active DSPDMAC channel register. */ 7548 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7549 if (status >= 0) { 7550 /* AND against 0xfff to get the active channel bits. */ 7551 tmp = tmp & 0xfff; 7552 7553 /* If there are no active channels, nothing to free. */ 7554 if (!tmp) 7555 return; 7556 } else { 7557 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7558 __func__); 7559 return; 7560 } 7561 7562 /* 7563 * Check each DSP DMA channel for activity, and if the channel is 7564 * active, free it. 7565 */ 7566 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7567 if (dsp_is_dma_active(codec, i)) { 7568 status = dspio_free_dma_chan(codec, i); 7569 if (status < 0) 7570 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7571 __func__, i); 7572 } 7573 } 7574 } 7575 7576 /* 7577 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7578 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7579 * Instead, audio is now routed through the DSP's DMA controllers, which 7580 * the DSP is tasked with setting up itself. Through debugging, it seems the 7581 * cause of most of the no-audio on startup issues were due to improperly 7582 * configured DSP DMA channels. 7583 * 7584 * Normally, the DSP configures these the first time an HDA audio stream is 7585 * started post DSP firmware download. That is why creating a 'dummy' stream 7586 * worked in fixing the audio in some cases. This works most of the time, but 7587 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7588 * configuration registers, it ends up in a broken state. Issues can also 7589 * arise if streams are started in an unusual order, i.e the audio output dma 7590 * channel being sandwiched between the mic1 and mic2 dma channels. 7591 * 7592 * The solution to this is to make sure that the DSP has no DMA channels 7593 * in use post DSP firmware download, and then to manually start each default 7594 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7595 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7596 */ 7597 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7598 { 7599 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7600 struct ca0132_spec *spec = codec->spec; 7601 unsigned int i, tmp; 7602 7603 /* 7604 * Check if any of the default streams are active, and if they are, 7605 * stop them. 7606 */ 7607 mutex_lock(&spec->chipio_mutex); 7608 7609 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7610 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7611 7612 if (tmp) { 7613 chipio_set_stream_control(codec, 7614 dsp_dma_stream_ids[i], 0); 7615 } 7616 } 7617 7618 mutex_unlock(&spec->chipio_mutex); 7619 7620 /* 7621 * If all DSP streams are inactive, there should be no active DSP DMA 7622 * channels. Check and make sure this is the case, and if it isn't, 7623 * free any active channels. 7624 */ 7625 ca0132_alt_free_active_dma_channels(codec); 7626 7627 mutex_lock(&spec->chipio_mutex); 7628 7629 /* Make sure stream 0x0c is six channels. */ 7630 chipio_set_stream_channels(codec, 0x0c, 6); 7631 7632 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7633 chipio_set_stream_control(codec, 7634 dsp_dma_stream_ids[i], 1); 7635 7636 /* Give the DSP some time to setup the DMA channel. */ 7637 msleep(75); 7638 } 7639 7640 mutex_unlock(&spec->chipio_mutex); 7641 } 7642 7643 /* 7644 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7645 * router', where each entry represents a 48khz audio channel, with a format 7646 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7647 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7648 * and 3 if it's using Sample Rate Converter ports. 7649 * An example is: 7650 * 0x0001f8c0 7651 * In this case, f8 is the destination, and c0 is the source. The number value 7652 * is 1. 7653 * This region of memory is normally managed internally by the 8051, where 7654 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7655 * entry within the 0x190000 range, and when a range of entries is in use, the 7656 * ending value is overwritten with 0xff. 7657 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7658 * streamID's, where each entry is a starting 0x190000 port offset. 7659 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7660 * offset for the corresponding streamID. 7661 * 7662 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7663 * the 8051, then manually overwritten to remap the ports to work with the 7664 * new DACs. 7665 * 7666 * Currently known portID's: 7667 * 0x00-0x1f: HDA audio stream input/output ports. 7668 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7669 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7670 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7671 * 0xe0-0xff: DAC/ADC audio input/output ports. 7672 * 7673 * Currently known streamID's: 7674 * 0x03: Mic1 ADC to DSP. 7675 * 0x04: Mic2 ADC to DSP. 7676 * 0x05: HDA node 0x02 audio stream to DSP. 7677 * 0x0f: DSP Mic exit to HDA node 0x07. 7678 * 0x0c: DSP processed audio to DACs. 7679 * 0x14: DAC0, front L/R. 7680 * 7681 * It is possible to route the HDA audio streams directly to the DAC and 7682 * bypass the DSP entirely, with the only downside being that since the DSP 7683 * does volume control, the only volume control you'll get is through PCM on 7684 * the PC side, in the same way volume is handled for optical out. This may be 7685 * useful for debugging. 7686 */ 7687 static void chipio_remap_stream(struct hda_codec *codec, 7688 const struct chipio_stream_remap_data *remap_data) 7689 { 7690 unsigned int i, stream_offset; 7691 7692 /* Get the starting port for the stream to be remapped. */ 7693 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7694 &stream_offset); 7695 7696 /* 7697 * Check if the stream's port value is 0xff, because the 8051 may not 7698 * have gotten around to setting up the stream yet. Wait until it's 7699 * setup to remap it's ports. 7700 */ 7701 if (stream_offset == 0xff) { 7702 for (i = 0; i < 5; i++) { 7703 msleep(25); 7704 7705 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7706 &stream_offset); 7707 7708 if (stream_offset != 0xff) 7709 break; 7710 } 7711 } 7712 7713 if (stream_offset == 0xff) { 7714 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7715 __func__, remap_data->stream_id); 7716 return; 7717 } 7718 7719 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7720 stream_offset *= 0x04; 7721 stream_offset += 0x190000; 7722 7723 for (i = 0; i < remap_data->count; i++) { 7724 chipio_write_no_mutex(codec, 7725 stream_offset + remap_data->offset[i], 7726 remap_data->value[i]); 7727 } 7728 7729 /* Update stream map configuration. */ 7730 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7731 } 7732 7733 /* 7734 * Default speaker tuning values setup for alternative codecs. 7735 */ 7736 static const unsigned int sbz_default_delay_values[] = { 7737 /* Non-zero values are floating point 0.000198. */ 7738 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7739 }; 7740 7741 static const unsigned int zxr_default_delay_values[] = { 7742 /* Non-zero values are floating point 0.000220. */ 7743 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7744 }; 7745 7746 static const unsigned int ae5_default_delay_values[] = { 7747 /* Non-zero values are floating point 0.000100. */ 7748 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7749 }; 7750 7751 /* 7752 * If we never change these, probably only need them on initialization. 7753 */ 7754 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7755 { 7756 struct ca0132_spec *spec = codec->spec; 7757 unsigned int i, tmp, start_req, end_req; 7758 const unsigned int *values; 7759 7760 switch (ca0132_quirk(spec)) { 7761 case QUIRK_SBZ: 7762 values = sbz_default_delay_values; 7763 break; 7764 case QUIRK_ZXR: 7765 values = zxr_default_delay_values; 7766 break; 7767 case QUIRK_AE5: 7768 case QUIRK_AE7: 7769 values = ae5_default_delay_values; 7770 break; 7771 default: 7772 values = sbz_default_delay_values; 7773 break; 7774 } 7775 7776 tmp = FLOAT_ZERO; 7777 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7778 7779 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7780 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7781 for (i = start_req; i < end_req + 1; i++) 7782 dspio_set_uint_param(codec, 0x96, i, tmp); 7783 7784 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7785 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7786 for (i = start_req; i < end_req + 1; i++) 7787 dspio_set_uint_param(codec, 0x96, i, tmp); 7788 7789 7790 for (i = 0; i < 6; i++) 7791 dspio_set_uint_param(codec, 0x96, 7792 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7793 } 7794 7795 /* 7796 * Initialize mic for non-chromebook ca0132 implementations. 7797 */ 7798 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7799 { 7800 struct ca0132_spec *spec = codec->spec; 7801 unsigned int tmp; 7802 7803 /* Mic 1 Setup */ 7804 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7805 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7806 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7807 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7808 tmp = FLOAT_ONE; 7809 } else 7810 tmp = FLOAT_THREE; 7811 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7812 7813 /* Mic 2 setup (not present on desktop cards) */ 7814 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7815 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7816 if (ca0132_quirk(spec) == QUIRK_R3DI) 7817 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7818 tmp = FLOAT_ZERO; 7819 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7820 } 7821 7822 /* 7823 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7824 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7825 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7826 * having an updated DAC, which changes the destination to that DAC. 7827 */ 7828 static void sbz_connect_streams(struct hda_codec *codec) 7829 { 7830 struct ca0132_spec *spec = codec->spec; 7831 7832 mutex_lock(&spec->chipio_mutex); 7833 7834 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7835 7836 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7837 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7838 7839 /* Setup stream 0x14 with it's source and destination points */ 7840 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7841 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7842 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7843 chipio_set_stream_channels(codec, 0x14, 2); 7844 chipio_set_stream_control(codec, 0x14, 1); 7845 7846 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7847 7848 mutex_unlock(&spec->chipio_mutex); 7849 } 7850 7851 /* 7852 * Write data through ChipIO to setup proper stream destinations. 7853 * Not sure how it exactly works, but it seems to direct data 7854 * to different destinations. Example is f8 to c0, e0 to c0. 7855 * All I know is, if you don't set these, you get no sound. 7856 */ 7857 static void sbz_chipio_startup_data(struct hda_codec *codec) 7858 { 7859 const struct chipio_stream_remap_data *dsp_out_remap_data; 7860 struct ca0132_spec *spec = codec->spec; 7861 7862 mutex_lock(&spec->chipio_mutex); 7863 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7864 7865 /* Remap DAC0's output ports. */ 7866 chipio_remap_stream(codec, &stream_remap_data[0]); 7867 7868 /* Remap DSP audio output stream ports. */ 7869 switch (ca0132_quirk(spec)) { 7870 case QUIRK_SBZ: 7871 dsp_out_remap_data = &stream_remap_data[1]; 7872 break; 7873 7874 case QUIRK_ZXR: 7875 dsp_out_remap_data = &stream_remap_data[2]; 7876 break; 7877 7878 default: 7879 dsp_out_remap_data = NULL; 7880 break; 7881 } 7882 7883 if (dsp_out_remap_data) 7884 chipio_remap_stream(codec, dsp_out_remap_data); 7885 7886 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7887 mutex_unlock(&spec->chipio_mutex); 7888 } 7889 7890 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7891 { 7892 struct ca0132_spec *spec = codec->spec; 7893 unsigned int tmp; 7894 7895 chipio_set_stream_control(codec, 0x03, 0); 7896 chipio_set_stream_control(codec, 0x04, 0); 7897 7898 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7899 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7900 7901 tmp = FLOAT_THREE; 7902 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7903 7904 chipio_set_stream_control(codec, 0x03, 1); 7905 chipio_set_stream_control(codec, 0x04, 1); 7906 7907 switch (ca0132_quirk(spec)) { 7908 case QUIRK_SBZ: 7909 chipio_write(codec, 0x18b098, 0x0000000c); 7910 chipio_write(codec, 0x18b09C, 0x0000000c); 7911 break; 7912 case QUIRK_AE5: 7913 chipio_write(codec, 0x18b098, 0x0000000c); 7914 chipio_write(codec, 0x18b09c, 0x0000004c); 7915 break; 7916 default: 7917 break; 7918 } 7919 } 7920 7921 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7922 { 7923 struct ca0132_spec *spec = codec->spec; 7924 7925 chipio_8051_write_direct(codec, 0x93, 0x10); 7926 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7927 7928 writeb(0xff, spec->mem_base + 0x304); 7929 writeb(0xff, spec->mem_base + 0x304); 7930 writeb(0xff, spec->mem_base + 0x304); 7931 writeb(0xff, spec->mem_base + 0x304); 7932 writeb(0x00, spec->mem_base + 0x100); 7933 writeb(0xff, spec->mem_base + 0x304); 7934 writeb(0x00, spec->mem_base + 0x100); 7935 writeb(0xff, spec->mem_base + 0x304); 7936 writeb(0x00, spec->mem_base + 0x100); 7937 writeb(0xff, spec->mem_base + 0x304); 7938 writeb(0x00, spec->mem_base + 0x100); 7939 writeb(0xff, spec->mem_base + 0x304); 7940 7941 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7942 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7943 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7944 } 7945 7946 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7947 { 7948 /* 7949 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7950 * which seems to be 'multichannel'. This is also mentioned in the 7951 * AE-5's registry values in Windows. 7952 */ 7953 chipio_set_control_param(codec, 3, 0); 7954 /* 7955 * I believe ASI is 'audio serial interface' and that it's used to 7956 * change colors on the external LED strip connected to the AE-5. 7957 */ 7958 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7959 7960 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7961 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7962 7963 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7964 } 7965 7966 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7967 { 7968 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7969 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7970 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7971 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7972 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7973 } 7974 7975 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7976 { 7977 struct ca0132_spec *spec = codec->spec; 7978 7979 mutex_lock(&spec->chipio_mutex); 7980 7981 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7982 7983 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7984 7985 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7986 7987 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7988 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7989 chipio_set_stream_channels(codec, 0x18, 6); 7990 chipio_set_stream_control(codec, 0x18, 1); 7991 7992 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7993 7994 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7995 7996 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7997 7998 mutex_unlock(&spec->chipio_mutex); 7999 } 8000 8001 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8002 { 8003 struct ca0132_spec *spec = codec->spec; 8004 8005 mutex_lock(&spec->chipio_mutex); 8006 8007 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8008 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8009 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8010 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8011 8012 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8013 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8014 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8015 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8016 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8017 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8018 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8019 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8020 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8021 ca0113_mmio_gpio_set(codec, 0, true); 8022 ca0113_mmio_gpio_set(codec, 1, true); 8023 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8024 8025 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8026 8027 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8028 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8029 8030 mutex_unlock(&spec->chipio_mutex); 8031 } 8032 8033 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8034 { 8035 struct ca0132_spec *spec = codec->spec; 8036 8037 mutex_lock(&spec->chipio_mutex); 8038 8039 /* Seems to share the same port remapping as the SBZ. */ 8040 chipio_remap_stream(codec, &stream_remap_data[1]); 8041 8042 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8043 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8044 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8045 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8046 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8047 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8048 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8049 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8050 8051 mutex_unlock(&spec->chipio_mutex); 8052 } 8053 8054 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8055 { 8056 struct ca0132_spec *spec = codec->spec; 8057 8058 mutex_lock(&spec->chipio_mutex); 8059 8060 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8061 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8062 8063 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8064 8065 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8066 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8067 8068 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8069 chipio_set_stream_channels(codec, 0x18, 6); 8070 chipio_set_stream_control(codec, 0x18, 1); 8071 8072 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8073 8074 mutex_unlock(&spec->chipio_mutex); 8075 } 8076 8077 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8078 { 8079 static const unsigned int addr[] = { 8080 0x41, 0x45, 0x40, 0x43, 0x51 8081 }; 8082 static const unsigned int data[] = { 8083 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8084 }; 8085 unsigned int i; 8086 8087 for (i = 0; i < ARRAY_SIZE(addr); i++) 8088 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8089 } 8090 8091 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8092 { 8093 struct ca0132_spec *spec = codec->spec; 8094 static const unsigned int target[] = { 8095 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8096 }; 8097 static const unsigned int data[] = { 8098 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8099 }; 8100 unsigned int i; 8101 8102 mutex_lock(&spec->chipio_mutex); 8103 8104 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8105 8106 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8107 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8108 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8109 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8110 8111 ae7_post_dsp_pll_setup(codec); 8112 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8113 8114 for (i = 0; i < ARRAY_SIZE(target); i++) 8115 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8116 8117 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8118 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8119 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8120 8121 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8122 chipio_set_stream_channels(codec, 0x21, 2); 8123 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8124 8125 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8126 /* 8127 * In the 8051's memory, this param is referred to as 'n2sid', which I 8128 * believe is 'node to streamID'. It seems to be a way to assign a 8129 * stream to a given HDA node. 8130 */ 8131 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8132 8133 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8134 8135 /* 8136 * Now, at this point on Windows, an actual stream is setup and 8137 * seemingly sends data to the HDA node 0x09, which is the digital 8138 * audio input node. This is left out here, because obviously I don't 8139 * know what data is being sent. Interestingly, the AE-5 seems to go 8140 * through the motions of getting here and never actually takes this 8141 * step, but the AE-7 does. 8142 */ 8143 8144 ca0113_mmio_gpio_set(codec, 0, 1); 8145 ca0113_mmio_gpio_set(codec, 1, 1); 8146 8147 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8148 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8149 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8150 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8151 8152 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8153 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8154 8155 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8156 chipio_set_stream_channels(codec, 0x18, 6); 8157 8158 /* 8159 * Runs again, this has been repeated a few times, but I'm just 8160 * following what the Windows driver does. 8161 */ 8162 ae7_post_dsp_pll_setup(codec); 8163 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8164 8165 mutex_unlock(&spec->chipio_mutex); 8166 } 8167 8168 /* 8169 * The Windows driver has commands that seem to setup ASI, which I believe to 8170 * be some sort of audio serial interface. My current speculation is that it's 8171 * related to communicating with the new DAC. 8172 */ 8173 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8174 { 8175 chipio_8051_write_direct(codec, 0x93, 0x10); 8176 8177 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8178 8179 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8180 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8181 8182 chipio_set_control_param(codec, 3, 3); 8183 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8184 8185 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8186 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8187 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8188 8189 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8190 8191 ae7_post_dsp_pll_setup(codec); 8192 ae7_post_dsp_asi_stream_setup(codec); 8193 8194 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8195 8196 ae7_post_dsp_asi_setup_ports(codec); 8197 } 8198 8199 /* 8200 * Setup default parameters for DSP 8201 */ 8202 static void ca0132_setup_defaults(struct hda_codec *codec) 8203 { 8204 struct ca0132_spec *spec = codec->spec; 8205 unsigned int tmp; 8206 int num_fx; 8207 int idx, i; 8208 8209 if (spec->dsp_state != DSP_DOWNLOADED) 8210 return; 8211 8212 /* out, in effects + voicefx */ 8213 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8214 for (idx = 0; idx < num_fx; idx++) { 8215 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8216 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8217 ca0132_effects[idx].reqs[i], 8218 ca0132_effects[idx].def_vals[i]); 8219 } 8220 } 8221 8222 /*remove DSP headroom*/ 8223 tmp = FLOAT_ZERO; 8224 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8225 8226 /*set speaker EQ bypass attenuation*/ 8227 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8228 8229 /* set AMic1 and AMic2 as mono mic */ 8230 tmp = FLOAT_ONE; 8231 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8232 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8233 8234 /* set AMic1 as CrystalVoice input */ 8235 tmp = FLOAT_ONE; 8236 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8237 8238 /* set WUH source */ 8239 tmp = FLOAT_TWO; 8240 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8241 } 8242 8243 /* 8244 * Setup default parameters for Recon3D/Recon3Di DSP. 8245 */ 8246 8247 static void r3d_setup_defaults(struct hda_codec *codec) 8248 { 8249 struct ca0132_spec *spec = codec->spec; 8250 unsigned int tmp; 8251 int num_fx; 8252 int idx, i; 8253 8254 if (spec->dsp_state != DSP_DOWNLOADED) 8255 return; 8256 8257 ca0132_alt_init_analog_mics(codec); 8258 ca0132_alt_start_dsp_audio_streams(codec); 8259 8260 /*remove DSP headroom*/ 8261 tmp = FLOAT_ZERO; 8262 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8263 8264 /* set WUH source */ 8265 tmp = FLOAT_TWO; 8266 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8267 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8268 8269 /* Set speaker source? */ 8270 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8271 8272 if (ca0132_quirk(spec) == QUIRK_R3DI) 8273 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8274 8275 /* Disable mute on Center/LFE. */ 8276 if (ca0132_quirk(spec) == QUIRK_R3D) { 8277 ca0113_mmio_gpio_set(codec, 2, false); 8278 ca0113_mmio_gpio_set(codec, 4, true); 8279 } 8280 8281 /* Setup effect defaults */ 8282 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8283 for (idx = 0; idx < num_fx; idx++) { 8284 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8285 dspio_set_uint_param(codec, 8286 ca0132_effects[idx].mid, 8287 ca0132_effects[idx].reqs[i], 8288 ca0132_effects[idx].def_vals[i]); 8289 } 8290 } 8291 } 8292 8293 /* 8294 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8295 * than the Chromebook setup. 8296 */ 8297 static void sbz_setup_defaults(struct hda_codec *codec) 8298 { 8299 struct ca0132_spec *spec = codec->spec; 8300 unsigned int tmp; 8301 int num_fx; 8302 int idx, i; 8303 8304 if (spec->dsp_state != DSP_DOWNLOADED) 8305 return; 8306 8307 ca0132_alt_init_analog_mics(codec); 8308 ca0132_alt_start_dsp_audio_streams(codec); 8309 sbz_connect_streams(codec); 8310 sbz_chipio_startup_data(codec); 8311 8312 /* 8313 * Sets internal input loopback to off, used to have a switch to 8314 * enable input loopback, but turned out to be way too buggy. 8315 */ 8316 tmp = FLOAT_ONE; 8317 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8318 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8319 8320 /*remove DSP headroom*/ 8321 tmp = FLOAT_ZERO; 8322 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8323 8324 /* set WUH source */ 8325 tmp = FLOAT_TWO; 8326 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8327 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8328 8329 /* Set speaker source? */ 8330 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8331 8332 ca0132_alt_dsp_initial_mic_setup(codec); 8333 8334 /* out, in effects + voicefx */ 8335 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8336 for (idx = 0; idx < num_fx; idx++) { 8337 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8338 dspio_set_uint_param(codec, 8339 ca0132_effects[idx].mid, 8340 ca0132_effects[idx].reqs[i], 8341 ca0132_effects[idx].def_vals[i]); 8342 } 8343 } 8344 8345 ca0132_alt_init_speaker_tuning(codec); 8346 } 8347 8348 /* 8349 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8350 */ 8351 static void ae5_setup_defaults(struct hda_codec *codec) 8352 { 8353 struct ca0132_spec *spec = codec->spec; 8354 unsigned int tmp; 8355 int num_fx; 8356 int idx, i; 8357 8358 if (spec->dsp_state != DSP_DOWNLOADED) 8359 return; 8360 8361 ca0132_alt_init_analog_mics(codec); 8362 ca0132_alt_start_dsp_audio_streams(codec); 8363 8364 /* New, unknown SCP req's */ 8365 tmp = FLOAT_ZERO; 8366 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8367 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8368 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8369 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8370 8371 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8372 ca0113_mmio_gpio_set(codec, 0, false); 8373 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8374 8375 /* Internal loopback off */ 8376 tmp = FLOAT_ONE; 8377 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8378 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8379 8380 /*remove DSP headroom*/ 8381 tmp = FLOAT_ZERO; 8382 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8383 8384 /* set WUH source */ 8385 tmp = FLOAT_TWO; 8386 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8387 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8388 8389 /* Set speaker source? */ 8390 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8391 8392 ca0132_alt_dsp_initial_mic_setup(codec); 8393 ae5_post_dsp_register_set(codec); 8394 ae5_post_dsp_param_setup(codec); 8395 ae5_post_dsp_pll_setup(codec); 8396 ae5_post_dsp_stream_setup(codec); 8397 ae5_post_dsp_startup_data(codec); 8398 8399 /* out, in effects + voicefx */ 8400 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8401 for (idx = 0; idx < num_fx; idx++) { 8402 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8403 dspio_set_uint_param(codec, 8404 ca0132_effects[idx].mid, 8405 ca0132_effects[idx].reqs[i], 8406 ca0132_effects[idx].def_vals[i]); 8407 } 8408 } 8409 8410 ca0132_alt_init_speaker_tuning(codec); 8411 } 8412 8413 /* 8414 * Setup default parameters for the Sound Blaster AE-7 DSP. 8415 */ 8416 static void ae7_setup_defaults(struct hda_codec *codec) 8417 { 8418 struct ca0132_spec *spec = codec->spec; 8419 unsigned int tmp; 8420 int num_fx; 8421 int idx, i; 8422 8423 if (spec->dsp_state != DSP_DOWNLOADED) 8424 return; 8425 8426 ca0132_alt_init_analog_mics(codec); 8427 ca0132_alt_start_dsp_audio_streams(codec); 8428 ae7_post_dsp_setup_ports(codec); 8429 8430 tmp = FLOAT_ZERO; 8431 dspio_set_uint_param(codec, 0x96, 8432 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8433 dspio_set_uint_param(codec, 0x96, 8434 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8435 8436 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8437 8438 /* New, unknown SCP req's */ 8439 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8440 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8441 8442 ca0113_mmio_gpio_set(codec, 0, false); 8443 8444 /* Internal loopback off */ 8445 tmp = FLOAT_ONE; 8446 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8447 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8448 8449 /*remove DSP headroom*/ 8450 tmp = FLOAT_ZERO; 8451 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8452 8453 /* set WUH source */ 8454 tmp = FLOAT_TWO; 8455 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8456 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8457 8458 /* Set speaker source? */ 8459 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8460 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8461 8462 /* 8463 * This is the second time we've called this, but this is seemingly 8464 * what Windows does. 8465 */ 8466 ca0132_alt_init_analog_mics(codec); 8467 8468 ae7_post_dsp_asi_setup(codec); 8469 8470 /* 8471 * Not sure why, but these are both set to 1. They're only set to 0 8472 * upon shutdown. 8473 */ 8474 ca0113_mmio_gpio_set(codec, 0, true); 8475 ca0113_mmio_gpio_set(codec, 1, true); 8476 8477 /* Volume control related. */ 8478 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8479 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8480 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8481 8482 /* out, in effects + voicefx */ 8483 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8484 for (idx = 0; idx < num_fx; idx++) { 8485 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8486 dspio_set_uint_param(codec, 8487 ca0132_effects[idx].mid, 8488 ca0132_effects[idx].reqs[i], 8489 ca0132_effects[idx].def_vals[i]); 8490 } 8491 } 8492 8493 ca0132_alt_init_speaker_tuning(codec); 8494 } 8495 8496 /* 8497 * Initialization of flags in chip 8498 */ 8499 static void ca0132_init_flags(struct hda_codec *codec) 8500 { 8501 struct ca0132_spec *spec = codec->spec; 8502 8503 if (ca0132_use_alt_functions(spec)) { 8504 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8505 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8506 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8507 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8508 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8509 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8510 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8511 chipio_set_control_flag(codec, 8512 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8513 chipio_set_control_flag(codec, 8514 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8515 } else { 8516 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8517 chipio_set_control_flag(codec, 8518 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8519 chipio_set_control_flag(codec, 8520 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8521 chipio_set_control_flag(codec, 8522 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8523 chipio_set_control_flag(codec, 8524 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8525 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8526 } 8527 } 8528 8529 /* 8530 * Initialization of parameters in chip 8531 */ 8532 static void ca0132_init_params(struct hda_codec *codec) 8533 { 8534 struct ca0132_spec *spec = codec->spec; 8535 8536 if (ca0132_use_alt_functions(spec)) { 8537 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8538 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8539 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8540 chipio_set_control_param(codec, 0, 0); 8541 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8542 } 8543 8544 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8545 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8546 } 8547 8548 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8549 { 8550 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8551 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8552 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8553 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8554 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8555 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8556 8557 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8558 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8559 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8560 } 8561 8562 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8563 { 8564 bool dsp_loaded = false; 8565 struct ca0132_spec *spec = codec->spec; 8566 const struct dsp_image_seg *dsp_os_image; 8567 const struct firmware *fw_entry = NULL; 8568 /* 8569 * Alternate firmwares for different variants. The Recon3Di apparently 8570 * can use the default firmware, but I'll leave the option in case 8571 * it needs it again. 8572 */ 8573 switch (ca0132_quirk(spec)) { 8574 case QUIRK_SBZ: 8575 case QUIRK_R3D: 8576 case QUIRK_AE5: 8577 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8578 codec->card->dev) != 0) 8579 codec_dbg(codec, "Desktop firmware not found."); 8580 else 8581 codec_dbg(codec, "Desktop firmware selected."); 8582 break; 8583 case QUIRK_R3DI: 8584 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8585 codec->card->dev) != 0) 8586 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8587 else 8588 codec_dbg(codec, "Recon3Di firmware selected."); 8589 break; 8590 default: 8591 break; 8592 } 8593 /* 8594 * Use default ctefx.bin if no alt firmware is detected, or if none 8595 * exists for your particular codec. 8596 */ 8597 if (!fw_entry) { 8598 codec_dbg(codec, "Default firmware selected."); 8599 if (request_firmware(&fw_entry, EFX_FILE, 8600 codec->card->dev) != 0) 8601 return false; 8602 } 8603 8604 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8605 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8606 codec_err(codec, "ca0132 DSP load image failed\n"); 8607 goto exit_download; 8608 } 8609 8610 dsp_loaded = dspload_wait_loaded(codec); 8611 8612 exit_download: 8613 release_firmware(fw_entry); 8614 8615 return dsp_loaded; 8616 } 8617 8618 static void ca0132_download_dsp(struct hda_codec *codec) 8619 { 8620 struct ca0132_spec *spec = codec->spec; 8621 8622 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8623 return; /* NOP */ 8624 #endif 8625 8626 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8627 return; /* don't retry failures */ 8628 8629 chipio_enable_clocks(codec); 8630 if (spec->dsp_state != DSP_DOWNLOADED) { 8631 spec->dsp_state = DSP_DOWNLOADING; 8632 8633 if (!ca0132_download_dsp_images(codec)) 8634 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8635 else 8636 spec->dsp_state = DSP_DOWNLOADED; 8637 } 8638 8639 /* For codecs using alt functions, this is already done earlier */ 8640 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8641 ca0132_set_dsp_msr(codec, true); 8642 } 8643 8644 static void ca0132_process_dsp_response(struct hda_codec *codec, 8645 struct hda_jack_callback *callback) 8646 { 8647 struct ca0132_spec *spec = codec->spec; 8648 8649 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8650 snd_hda_power_up_pm(codec); 8651 if (spec->wait_scp) { 8652 if (dspio_get_response_data(codec) >= 0) 8653 spec->wait_scp = 0; 8654 } 8655 8656 dspio_clear_response_queue(codec); 8657 snd_hda_power_down_pm(codec); 8658 } 8659 8660 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8661 { 8662 struct ca0132_spec *spec = codec->spec; 8663 struct hda_jack_tbl *tbl; 8664 8665 /* Delay enabling the HP amp, to let the mic-detection 8666 * state machine run. 8667 */ 8668 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8669 if (tbl) 8670 tbl->block_report = 1; 8671 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8672 } 8673 8674 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8675 { 8676 struct ca0132_spec *spec = codec->spec; 8677 8678 if (ca0132_use_alt_functions(spec)) 8679 ca0132_alt_select_in(codec); 8680 else 8681 ca0132_select_mic(codec); 8682 } 8683 8684 static void ca0132_setup_unsol(struct hda_codec *codec) 8685 { 8686 struct ca0132_spec *spec = codec->spec; 8687 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8688 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8689 amic_callback); 8690 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8691 ca0132_process_dsp_response); 8692 /* Front headphone jack detection */ 8693 if (ca0132_use_alt_functions(spec)) 8694 snd_hda_jack_detect_enable_callback(codec, 8695 spec->unsol_tag_front_hp, hp_callback); 8696 } 8697 8698 /* 8699 * Verbs tables. 8700 */ 8701 8702 /* Sends before DSP download. */ 8703 static const struct hda_verb ca0132_base_init_verbs[] = { 8704 /*enable ct extension*/ 8705 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8706 {} 8707 }; 8708 8709 /* Send at exit. */ 8710 static const struct hda_verb ca0132_base_exit_verbs[] = { 8711 /*set afg to D3*/ 8712 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8713 /*disable ct extension*/ 8714 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8715 {} 8716 }; 8717 8718 /* Other verbs tables. Sends after DSP download. */ 8719 8720 static const struct hda_verb ca0132_init_verbs0[] = { 8721 /* chip init verbs */ 8722 {0x15, 0x70D, 0xF0}, 8723 {0x15, 0x70E, 0xFE}, 8724 {0x15, 0x707, 0x75}, 8725 {0x15, 0x707, 0xD3}, 8726 {0x15, 0x707, 0x09}, 8727 {0x15, 0x707, 0x53}, 8728 {0x15, 0x707, 0xD4}, 8729 {0x15, 0x707, 0xEF}, 8730 {0x15, 0x707, 0x75}, 8731 {0x15, 0x707, 0xD3}, 8732 {0x15, 0x707, 0x09}, 8733 {0x15, 0x707, 0x02}, 8734 {0x15, 0x707, 0x37}, 8735 {0x15, 0x707, 0x78}, 8736 {0x15, 0x53C, 0xCE}, 8737 {0x15, 0x575, 0xC9}, 8738 {0x15, 0x53D, 0xCE}, 8739 {0x15, 0x5B7, 0xC9}, 8740 {0x15, 0x70D, 0xE8}, 8741 {0x15, 0x70E, 0xFE}, 8742 {0x15, 0x707, 0x02}, 8743 {0x15, 0x707, 0x68}, 8744 {0x15, 0x707, 0x62}, 8745 {0x15, 0x53A, 0xCE}, 8746 {0x15, 0x546, 0xC9}, 8747 {0x15, 0x53B, 0xCE}, 8748 {0x15, 0x5E8, 0xC9}, 8749 {} 8750 }; 8751 8752 /* Extra init verbs for desktop cards. */ 8753 static const struct hda_verb ca0132_init_verbs1[] = { 8754 {0x15, 0x70D, 0x20}, 8755 {0x15, 0x70E, 0x19}, 8756 {0x15, 0x707, 0x00}, 8757 {0x15, 0x539, 0xCE}, 8758 {0x15, 0x546, 0xC9}, 8759 {0x15, 0x70D, 0xB7}, 8760 {0x15, 0x70E, 0x09}, 8761 {0x15, 0x707, 0x10}, 8762 {0x15, 0x70D, 0xAF}, 8763 {0x15, 0x70E, 0x09}, 8764 {0x15, 0x707, 0x01}, 8765 {0x15, 0x707, 0x05}, 8766 {0x15, 0x70D, 0x73}, 8767 {0x15, 0x70E, 0x09}, 8768 {0x15, 0x707, 0x14}, 8769 {0x15, 0x6FF, 0xC4}, 8770 {} 8771 }; 8772 8773 static void ca0132_init_chip(struct hda_codec *codec) 8774 { 8775 struct ca0132_spec *spec = codec->spec; 8776 int num_fx; 8777 int i; 8778 unsigned int on; 8779 8780 mutex_init(&spec->chipio_mutex); 8781 8782 /* 8783 * The Windows driver always does this upon startup, which seems to 8784 * clear out any previous configuration. This should help issues where 8785 * a boot into Windows prior to a boot into Linux breaks things. Also, 8786 * Windows always sends the reset twice. 8787 */ 8788 if (ca0132_use_alt_functions(spec)) { 8789 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8790 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8791 8792 snd_hda_codec_write(codec, codec->core.afg, 0, 8793 AC_VERB_SET_CODEC_RESET, 0); 8794 snd_hda_codec_write(codec, codec->core.afg, 0, 8795 AC_VERB_SET_CODEC_RESET, 0); 8796 } 8797 8798 spec->cur_out_type = SPEAKER_OUT; 8799 if (!ca0132_use_alt_functions(spec)) 8800 spec->cur_mic_type = DIGITAL_MIC; 8801 else 8802 spec->cur_mic_type = REAR_MIC; 8803 8804 spec->cur_mic_boost = 0; 8805 8806 for (i = 0; i < VNODES_COUNT; i++) { 8807 spec->vnode_lvol[i] = 0x5a; 8808 spec->vnode_rvol[i] = 0x5a; 8809 spec->vnode_lswitch[i] = 0; 8810 spec->vnode_rswitch[i] = 0; 8811 } 8812 8813 /* 8814 * Default states for effects are in ca0132_effects[]. 8815 */ 8816 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8817 for (i = 0; i < num_fx; i++) { 8818 on = (unsigned int)ca0132_effects[i].reqs[0]; 8819 spec->effects_switch[i] = on ? 1 : 0; 8820 } 8821 /* 8822 * Sets defaults for the effect slider controls, only for alternative 8823 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8824 */ 8825 if (ca0132_use_alt_controls(spec)) { 8826 /* Set speakers to default to full range. */ 8827 spec->speaker_range_val[0] = 1; 8828 spec->speaker_range_val[1] = 1; 8829 8830 spec->xbass_xover_freq = 8; 8831 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8832 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8833 8834 spec->bass_redirect_xover_freq = 8; 8835 } 8836 8837 spec->voicefx_val = 0; 8838 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8839 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8840 8841 /* 8842 * The ZxR doesn't have a front panel header, and it's line-in is on 8843 * the daughter board. So, there is no input enum control, and we need 8844 * to make sure that spec->in_enum_val is set properly. 8845 */ 8846 if (ca0132_quirk(spec) == QUIRK_ZXR) 8847 spec->in_enum_val = REAR_MIC; 8848 8849 #ifdef ENABLE_TUNING_CONTROLS 8850 ca0132_init_tuning_defaults(codec); 8851 #endif 8852 } 8853 8854 /* 8855 * Recon3Di exit specific commands. 8856 */ 8857 /* prevents popping noise on shutdown */ 8858 static void r3di_gpio_shutdown(struct hda_codec *codec) 8859 { 8860 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8861 } 8862 8863 /* 8864 * Sound Blaster Z exit specific commands. 8865 */ 8866 static void sbz_region2_exit(struct hda_codec *codec) 8867 { 8868 struct ca0132_spec *spec = codec->spec; 8869 unsigned int i; 8870 8871 for (i = 0; i < 4; i++) 8872 writeb(0x0, spec->mem_base + 0x100); 8873 for (i = 0; i < 8; i++) 8874 writeb(0xb3, spec->mem_base + 0x304); 8875 8876 ca0113_mmio_gpio_set(codec, 0, false); 8877 ca0113_mmio_gpio_set(codec, 1, false); 8878 ca0113_mmio_gpio_set(codec, 4, true); 8879 ca0113_mmio_gpio_set(codec, 5, false); 8880 ca0113_mmio_gpio_set(codec, 7, false); 8881 } 8882 8883 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8884 { 8885 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8886 unsigned int i; 8887 8888 snd_hda_codec_write(codec, 0x11, 0, 8889 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8890 8891 for (i = 0; i < ARRAY_SIZE(pins); i++) 8892 snd_hda_codec_write(codec, pins[i], 0, 8893 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8894 } 8895 8896 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8897 { 8898 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8899 unsigned int i; 8900 8901 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8902 snd_hda_codec_write(codec, pins[i], 0, 8903 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8904 } 8905 } 8906 8907 /* On shutdown, sends commands in sets of three */ 8908 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8909 int mask, int data) 8910 { 8911 if (dir >= 0) 8912 snd_hda_codec_write(codec, 0x01, 0, 8913 AC_VERB_SET_GPIO_DIRECTION, dir); 8914 if (mask >= 0) 8915 snd_hda_codec_write(codec, 0x01, 0, 8916 AC_VERB_SET_GPIO_MASK, mask); 8917 8918 if (data >= 0) 8919 snd_hda_codec_write(codec, 0x01, 0, 8920 AC_VERB_SET_GPIO_DATA, data); 8921 } 8922 8923 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8924 { 8925 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8926 unsigned int i; 8927 8928 for (i = 0; i < ARRAY_SIZE(pins); i++) 8929 snd_hda_codec_write(codec, pins[i], 0, 8930 AC_VERB_SET_POWER_STATE, 0x03); 8931 } 8932 8933 static void sbz_exit_chip(struct hda_codec *codec) 8934 { 8935 chipio_set_stream_control(codec, 0x03, 0); 8936 chipio_set_stream_control(codec, 0x04, 0); 8937 8938 /* Mess with GPIO */ 8939 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8940 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8941 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8942 8943 chipio_set_stream_control(codec, 0x14, 0); 8944 chipio_set_stream_control(codec, 0x0C, 0); 8945 8946 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8947 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8948 8949 chipio_write(codec, 0x18a020, 0x00000083); 8950 8951 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8952 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8954 8955 chipio_set_stream_control(codec, 0x0C, 0); 8956 8957 chipio_set_control_param(codec, 0x0D, 0x24); 8958 8959 ca0132_clear_unsolicited(codec); 8960 sbz_set_pin_ctl_default(codec); 8961 8962 snd_hda_codec_write(codec, 0x0B, 0, 8963 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8964 8965 sbz_region2_exit(codec); 8966 } 8967 8968 static void r3d_exit_chip(struct hda_codec *codec) 8969 { 8970 ca0132_clear_unsolicited(codec); 8971 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8972 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8973 } 8974 8975 static void ae5_exit_chip(struct hda_codec *codec) 8976 { 8977 chipio_set_stream_control(codec, 0x03, 0); 8978 chipio_set_stream_control(codec, 0x04, 0); 8979 8980 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8981 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8982 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8983 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8984 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8985 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8986 ca0113_mmio_gpio_set(codec, 0, false); 8987 ca0113_mmio_gpio_set(codec, 1, false); 8988 8989 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8990 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8991 8992 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8993 8994 chipio_set_stream_control(codec, 0x18, 0); 8995 chipio_set_stream_control(codec, 0x0c, 0); 8996 8997 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8998 } 8999 9000 static void ae7_exit_chip(struct hda_codec *codec) 9001 { 9002 chipio_set_stream_control(codec, 0x18, 0); 9003 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9004 chipio_set_stream_channels(codec, 0x21, 0); 9005 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9006 chipio_set_control_param(codec, 0x20, 0x01); 9007 9008 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9009 9010 chipio_set_stream_control(codec, 0x18, 0); 9011 chipio_set_stream_control(codec, 0x0c, 0); 9012 9013 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9014 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9015 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9016 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9017 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9018 ca0113_mmio_gpio_set(codec, 0, false); 9019 ca0113_mmio_gpio_set(codec, 1, false); 9020 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9021 9022 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9023 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9024 } 9025 9026 static void zxr_exit_chip(struct hda_codec *codec) 9027 { 9028 chipio_set_stream_control(codec, 0x03, 0); 9029 chipio_set_stream_control(codec, 0x04, 0); 9030 chipio_set_stream_control(codec, 0x14, 0); 9031 chipio_set_stream_control(codec, 0x0C, 0); 9032 9033 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9034 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9035 9036 chipio_write(codec, 0x18a020, 0x00000083); 9037 9038 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9039 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9040 9041 ca0132_clear_unsolicited(codec); 9042 sbz_set_pin_ctl_default(codec); 9043 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9044 9045 ca0113_mmio_gpio_set(codec, 5, false); 9046 ca0113_mmio_gpio_set(codec, 2, false); 9047 ca0113_mmio_gpio_set(codec, 3, false); 9048 ca0113_mmio_gpio_set(codec, 0, false); 9049 ca0113_mmio_gpio_set(codec, 4, true); 9050 ca0113_mmio_gpio_set(codec, 0, true); 9051 ca0113_mmio_gpio_set(codec, 5, true); 9052 ca0113_mmio_gpio_set(codec, 2, false); 9053 ca0113_mmio_gpio_set(codec, 3, false); 9054 } 9055 9056 static void ca0132_exit_chip(struct hda_codec *codec) 9057 { 9058 /* put any chip cleanup stuffs here. */ 9059 9060 if (dspload_is_loaded(codec)) 9061 dsp_reset(codec); 9062 } 9063 9064 /* 9065 * This fixes a problem that was hard to reproduce. Very rarely, I would 9066 * boot up, and there would be no sound, but the DSP indicated it had loaded 9067 * properly. I did a few memory dumps to see if anything was different, and 9068 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9069 * checks if those areas are uninitialized, and if they are, it'll attempt to 9070 * reload the card 3 times. Usually it fixes by the second. 9071 */ 9072 static void sbz_dsp_startup_check(struct hda_codec *codec) 9073 { 9074 struct ca0132_spec *spec = codec->spec; 9075 unsigned int dsp_data_check[4]; 9076 unsigned int cur_address = 0x390; 9077 unsigned int i; 9078 unsigned int failure = 0; 9079 unsigned int reload = 3; 9080 9081 if (spec->startup_check_entered) 9082 return; 9083 9084 spec->startup_check_entered = true; 9085 9086 for (i = 0; i < 4; i++) { 9087 chipio_read(codec, cur_address, &dsp_data_check[i]); 9088 cur_address += 0x4; 9089 } 9090 for (i = 0; i < 4; i++) { 9091 if (dsp_data_check[i] == 0xa1a2a3a4) 9092 failure = 1; 9093 } 9094 9095 codec_dbg(codec, "Startup Check: %d ", failure); 9096 if (failure) 9097 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9098 /* 9099 * While the failure condition is true, and we haven't reached our 9100 * three reload limit, continue trying to reload the driver and 9101 * fix the issue. 9102 */ 9103 while (failure && (reload != 0)) { 9104 codec_info(codec, "Reloading... Tries left: %d", reload); 9105 sbz_exit_chip(codec); 9106 spec->dsp_state = DSP_DOWNLOAD_INIT; 9107 codec->patch_ops.init(codec); 9108 failure = 0; 9109 for (i = 0; i < 4; i++) { 9110 chipio_read(codec, cur_address, &dsp_data_check[i]); 9111 cur_address += 0x4; 9112 } 9113 for (i = 0; i < 4; i++) { 9114 if (dsp_data_check[i] == 0xa1a2a3a4) 9115 failure = 1; 9116 } 9117 reload--; 9118 } 9119 9120 if (!failure && reload < 3) 9121 codec_info(codec, "DSP fixed."); 9122 9123 if (!failure) 9124 return; 9125 9126 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9127 } 9128 9129 /* 9130 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9131 * extra precision for decibel values. If you had the dB value in floating point 9132 * you would take the value after the decimal point, multiply by 64, and divide 9133 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9134 * implement fixed point or floating point dB volumes. For now, I'll set them 9135 * to 0 just incase a value has lingered from a boot into Windows. 9136 */ 9137 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9138 { 9139 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9140 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9141 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9142 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9143 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9144 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9145 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9146 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9147 } 9148 9149 /* 9150 * Extra commands that don't really fit anywhere else. 9151 */ 9152 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9153 { 9154 struct ca0132_spec *spec = codec->spec; 9155 9156 writel(0x00820680, spec->mem_base + 0x01C); 9157 writel(0x00820680, spec->mem_base + 0x01C); 9158 9159 chipio_write(codec, 0x18b0a4, 0x000000c2); 9160 9161 snd_hda_codec_write(codec, 0x11, 0, 9162 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9163 } 9164 9165 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9166 { 9167 chipio_write(codec, 0x18b0a4, 0x000000c2); 9168 9169 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9170 9171 snd_hda_codec_write(codec, 0x11, 0, 9172 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9173 } 9174 9175 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9176 { 9177 chipio_write(codec, 0x18b0a4, 0x000000c2); 9178 9179 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9180 chipio_8051_write_exram(codec, 0x1920, 0x00); 9181 chipio_8051_write_exram(codec, 0x1921, 0x40); 9182 9183 snd_hda_codec_write(codec, 0x11, 0, 9184 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9185 } 9186 9187 /* 9188 * The ZxR seems to use alternative DAC's for the surround channels, which 9189 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9190 * this up, we get no audio out of the surround jacks. 9191 */ 9192 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9193 { 9194 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9195 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9196 unsigned int i; 9197 9198 chipio_write(codec, 0x189000, 0x0001f100); 9199 msleep(50); 9200 chipio_write(codec, 0x18900c, 0x0001f100); 9201 msleep(50); 9202 9203 /* 9204 * This writes a RET instruction at the entry point of the function at 9205 * 0xfa92 in exram. This function seems to have something to do with 9206 * ASI. Might be some way to prevent the card from reconfiguring the 9207 * ASI stuff itself. 9208 */ 9209 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9210 9211 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9212 9213 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9214 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9215 9216 chipio_write(codec, 0x18902c, 0x00000000); 9217 msleep(50); 9218 chipio_write(codec, 0x18902c, 0x00000003); 9219 msleep(50); 9220 9221 for (i = 0; i < ARRAY_SIZE(addr); i++) 9222 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9223 } 9224 9225 /* 9226 * These are sent before the DSP is downloaded. Not sure 9227 * what they do, or if they're necessary. Could possibly 9228 * be removed. Figure they're better to leave in. 9229 */ 9230 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9231 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9232 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9233 }; 9234 9235 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9236 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9237 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9238 0x000000c1, 0x00000080 9239 }; 9240 9241 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9242 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9243 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9244 0x000000c1, 0x00000080 9245 }; 9246 9247 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9248 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9249 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9250 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9251 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9252 }; 9253 9254 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9255 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9256 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9257 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9258 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9259 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9260 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9261 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9262 0x00000080, 0x00880680 9263 }; 9264 9265 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9266 { 9267 struct ca0132_spec *spec = codec->spec; 9268 unsigned int tmp[2], i, count, cur_addr; 9269 const unsigned int *addr, *data; 9270 9271 addr = ca0113_mmio_init_address_sbz; 9272 for (i = 0; i < 3; i++) 9273 writel(0x00000000, spec->mem_base + addr[i]); 9274 9275 cur_addr = i; 9276 switch (ca0132_quirk(spec)) { 9277 case QUIRK_ZXR: 9278 tmp[0] = 0x00880480; 9279 tmp[1] = 0x00000080; 9280 break; 9281 case QUIRK_SBZ: 9282 tmp[0] = 0x00820680; 9283 tmp[1] = 0x00000083; 9284 break; 9285 case QUIRK_R3D: 9286 tmp[0] = 0x00880680; 9287 tmp[1] = 0x00000083; 9288 break; 9289 default: 9290 tmp[0] = 0x00000000; 9291 tmp[1] = 0x00000000; 9292 break; 9293 } 9294 9295 for (i = 0; i < 2; i++) 9296 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9297 9298 cur_addr += i; 9299 9300 switch (ca0132_quirk(spec)) { 9301 case QUIRK_ZXR: 9302 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9303 data = ca0113_mmio_init_data_zxr; 9304 break; 9305 default: 9306 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9307 data = ca0113_mmio_init_data_sbz; 9308 break; 9309 } 9310 9311 for (i = 0; i < count; i++) 9312 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9313 } 9314 9315 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9316 { 9317 struct ca0132_spec *spec = codec->spec; 9318 const unsigned int *addr, *data; 9319 unsigned int i, count; 9320 9321 addr = ca0113_mmio_init_address_ae5; 9322 data = ca0113_mmio_init_data_ae5; 9323 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9324 9325 if (ca0132_quirk(spec) == QUIRK_AE7) { 9326 writel(0x00000680, spec->mem_base + 0x1c); 9327 writel(0x00880680, spec->mem_base + 0x1c); 9328 } 9329 9330 for (i = 0; i < count; i++) { 9331 /* 9332 * AE-7 shares all writes with the AE-5, except that it writes 9333 * a different value to 0x20c. 9334 */ 9335 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9336 writel(0x00800001, spec->mem_base + addr[i]); 9337 continue; 9338 } 9339 9340 writel(data[i], spec->mem_base + addr[i]); 9341 } 9342 9343 if (ca0132_quirk(spec) == QUIRK_AE5) 9344 writel(0x00880680, spec->mem_base + 0x1c); 9345 } 9346 9347 static void ca0132_mmio_init(struct hda_codec *codec) 9348 { 9349 struct ca0132_spec *spec = codec->spec; 9350 9351 switch (ca0132_quirk(spec)) { 9352 case QUIRK_R3D: 9353 case QUIRK_SBZ: 9354 case QUIRK_ZXR: 9355 ca0132_mmio_init_sbz(codec); 9356 break; 9357 case QUIRK_AE5: 9358 ca0132_mmio_init_ae5(codec); 9359 break; 9360 default: 9361 break; 9362 } 9363 } 9364 9365 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9366 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9367 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9368 }; 9369 9370 static const unsigned char ca0132_ae5_register_set_data[] = { 9371 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9372 0x01, 0x6b, 0x57 9373 }; 9374 9375 /* 9376 * This function writes to some SFR's, does some region2 writes, and then 9377 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9378 * what it does. 9379 */ 9380 static void ae5_register_set(struct hda_codec *codec) 9381 { 9382 struct ca0132_spec *spec = codec->spec; 9383 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9384 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9385 const unsigned char *data = ca0132_ae5_register_set_data; 9386 unsigned int i, cur_addr; 9387 unsigned char tmp[3]; 9388 9389 if (ca0132_quirk(spec) == QUIRK_AE7) 9390 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9391 9392 chipio_8051_write_direct(codec, 0x93, 0x10); 9393 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9394 9395 if (ca0132_quirk(spec) == QUIRK_AE7) { 9396 tmp[0] = 0x03; 9397 tmp[1] = 0x03; 9398 tmp[2] = 0x07; 9399 } else { 9400 tmp[0] = 0x0f; 9401 tmp[1] = 0x0f; 9402 tmp[2] = 0x0f; 9403 } 9404 9405 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9406 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9407 9408 /* 9409 * First writes are in single bytes, final are in 4 bytes. So, we use 9410 * writeb, then writel. 9411 */ 9412 for (i = 0; cur_addr < 12; i++, cur_addr++) 9413 writeb(data[i], spec->mem_base + addr[cur_addr]); 9414 9415 for (; cur_addr < count; i++, cur_addr++) 9416 writel(data[i], spec->mem_base + addr[cur_addr]); 9417 9418 writel(0x00800001, spec->mem_base + 0x20c); 9419 9420 if (ca0132_quirk(spec) == QUIRK_AE7) { 9421 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9422 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9423 } else { 9424 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9425 } 9426 9427 chipio_8051_write_direct(codec, 0x90, 0x00); 9428 chipio_8051_write_direct(codec, 0x90, 0x10); 9429 9430 if (ca0132_quirk(spec) == QUIRK_AE5) 9431 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9432 } 9433 9434 /* 9435 * Extra init functions for alternative ca0132 codecs. Done 9436 * here so they don't clutter up the main ca0132_init function 9437 * anymore than they have to. 9438 */ 9439 static void ca0132_alt_init(struct hda_codec *codec) 9440 { 9441 struct ca0132_spec *spec = codec->spec; 9442 9443 ca0132_alt_vol_setup(codec); 9444 9445 switch (ca0132_quirk(spec)) { 9446 case QUIRK_SBZ: 9447 codec_dbg(codec, "SBZ alt_init"); 9448 ca0132_gpio_init(codec); 9449 sbz_pre_dsp_setup(codec); 9450 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9451 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9452 break; 9453 case QUIRK_R3DI: 9454 codec_dbg(codec, "R3DI alt_init"); 9455 ca0132_gpio_init(codec); 9456 ca0132_gpio_setup(codec); 9457 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9458 r3di_pre_dsp_setup(codec); 9459 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9460 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9461 break; 9462 case QUIRK_R3D: 9463 r3d_pre_dsp_setup(codec); 9464 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9465 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9466 break; 9467 case QUIRK_AE5: 9468 ca0132_gpio_init(codec); 9469 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9470 chipio_write(codec, 0x18b030, 0x00000020); 9471 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9472 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9473 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9474 break; 9475 case QUIRK_AE7: 9476 ca0132_gpio_init(codec); 9477 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9478 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9479 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9480 chipio_write(codec, 0x18b008, 0x000000f8); 9481 chipio_write(codec, 0x18b008, 0x000000f0); 9482 chipio_write(codec, 0x18b030, 0x00000020); 9483 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9484 break; 9485 case QUIRK_ZXR: 9486 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9487 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9488 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9489 zxr_pre_dsp_setup(codec); 9490 break; 9491 default: 9492 break; 9493 } 9494 } 9495 9496 static int ca0132_init(struct hda_codec *codec) 9497 { 9498 struct ca0132_spec *spec = codec->spec; 9499 struct auto_pin_cfg *cfg = &spec->autocfg; 9500 int i; 9501 bool dsp_loaded; 9502 9503 /* 9504 * If the DSP is already downloaded, and init has been entered again, 9505 * there's only two reasons for it. One, the codec has awaken from a 9506 * suspended state, and in that case dspload_is_loaded will return 9507 * false, and the init will be ran again. The other reason it gets 9508 * re entered is on startup for some reason it triggers a suspend and 9509 * resume state. In this case, it will check if the DSP is downloaded, 9510 * and not run the init function again. For codecs using alt_functions, 9511 * it will check if the DSP is loaded properly. 9512 */ 9513 if (spec->dsp_state == DSP_DOWNLOADED) { 9514 dsp_loaded = dspload_is_loaded(codec); 9515 if (!dsp_loaded) { 9516 spec->dsp_reload = true; 9517 spec->dsp_state = DSP_DOWNLOAD_INIT; 9518 } else { 9519 if (ca0132_quirk(spec) == QUIRK_SBZ) 9520 sbz_dsp_startup_check(codec); 9521 return 0; 9522 } 9523 } 9524 9525 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9526 spec->dsp_state = DSP_DOWNLOAD_INIT; 9527 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9528 9529 if (ca0132_use_pci_mmio(spec)) 9530 ca0132_mmio_init(codec); 9531 9532 snd_hda_power_up_pm(codec); 9533 9534 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9535 ae5_register_set(codec); 9536 9537 ca0132_init_params(codec); 9538 ca0132_init_flags(codec); 9539 9540 snd_hda_sequence_write(codec, spec->base_init_verbs); 9541 9542 if (ca0132_use_alt_functions(spec)) 9543 ca0132_alt_init(codec); 9544 9545 ca0132_download_dsp(codec); 9546 9547 ca0132_refresh_widget_caps(codec); 9548 9549 switch (ca0132_quirk(spec)) { 9550 case QUIRK_R3DI: 9551 case QUIRK_R3D: 9552 r3d_setup_defaults(codec); 9553 break; 9554 case QUIRK_SBZ: 9555 case QUIRK_ZXR: 9556 sbz_setup_defaults(codec); 9557 break; 9558 case QUIRK_AE5: 9559 ae5_setup_defaults(codec); 9560 break; 9561 case QUIRK_AE7: 9562 ae7_setup_defaults(codec); 9563 break; 9564 default: 9565 ca0132_setup_defaults(codec); 9566 ca0132_init_analog_mic2(codec); 9567 ca0132_init_dmic(codec); 9568 break; 9569 } 9570 9571 for (i = 0; i < spec->num_outputs; i++) 9572 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9573 9574 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9575 9576 for (i = 0; i < spec->num_inputs; i++) 9577 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9578 9579 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9580 9581 if (!ca0132_use_alt_functions(spec)) { 9582 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9583 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9584 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9585 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9586 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9587 } 9588 9589 if (ca0132_quirk(spec) == QUIRK_SBZ) 9590 ca0132_gpio_setup(codec); 9591 9592 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9593 if (ca0132_use_alt_functions(spec)) { 9594 ca0132_alt_select_out(codec); 9595 ca0132_alt_select_in(codec); 9596 } else { 9597 ca0132_select_out(codec); 9598 ca0132_select_mic(codec); 9599 } 9600 9601 snd_hda_jack_report_sync(codec); 9602 9603 /* 9604 * Re set the PlayEnhancement switch on a resume event, because the 9605 * controls will not be reloaded. 9606 */ 9607 if (spec->dsp_reload) { 9608 spec->dsp_reload = false; 9609 ca0132_pe_switch_set(codec); 9610 } 9611 9612 snd_hda_power_down_pm(codec); 9613 9614 return 0; 9615 } 9616 9617 static int dbpro_init(struct hda_codec *codec) 9618 { 9619 struct ca0132_spec *spec = codec->spec; 9620 struct auto_pin_cfg *cfg = &spec->autocfg; 9621 unsigned int i; 9622 9623 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9624 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9625 9626 for (i = 0; i < spec->num_inputs; i++) 9627 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9628 9629 return 0; 9630 } 9631 9632 static void ca0132_free(struct hda_codec *codec) 9633 { 9634 struct ca0132_spec *spec = codec->spec; 9635 9636 cancel_delayed_work_sync(&spec->unsol_hp_work); 9637 snd_hda_power_up(codec); 9638 switch (ca0132_quirk(spec)) { 9639 case QUIRK_SBZ: 9640 sbz_exit_chip(codec); 9641 break; 9642 case QUIRK_ZXR: 9643 zxr_exit_chip(codec); 9644 break; 9645 case QUIRK_R3D: 9646 r3d_exit_chip(codec); 9647 break; 9648 case QUIRK_AE5: 9649 ae5_exit_chip(codec); 9650 break; 9651 case QUIRK_AE7: 9652 ae7_exit_chip(codec); 9653 break; 9654 case QUIRK_R3DI: 9655 r3di_gpio_shutdown(codec); 9656 break; 9657 default: 9658 break; 9659 } 9660 9661 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9662 ca0132_exit_chip(codec); 9663 9664 snd_hda_power_down(codec); 9665 #ifdef CONFIG_PCI 9666 if (spec->mem_base) 9667 pci_iounmap(codec->bus->pci, spec->mem_base); 9668 #endif 9669 kfree(spec->spec_init_verbs); 9670 kfree(codec->spec); 9671 } 9672 9673 static void dbpro_free(struct hda_codec *codec) 9674 { 9675 struct ca0132_spec *spec = codec->spec; 9676 9677 zxr_dbpro_power_state_shutdown(codec); 9678 9679 kfree(spec->spec_init_verbs); 9680 kfree(codec->spec); 9681 } 9682 9683 #ifdef CONFIG_PM 9684 static int ca0132_suspend(struct hda_codec *codec) 9685 { 9686 struct ca0132_spec *spec = codec->spec; 9687 9688 cancel_delayed_work_sync(&spec->unsol_hp_work); 9689 return 0; 9690 } 9691 #endif 9692 9693 static const struct hda_codec_ops ca0132_patch_ops = { 9694 .build_controls = ca0132_build_controls, 9695 .build_pcms = ca0132_build_pcms, 9696 .init = ca0132_init, 9697 .free = ca0132_free, 9698 .unsol_event = snd_hda_jack_unsol_event, 9699 #ifdef CONFIG_PM 9700 .suspend = ca0132_suspend, 9701 #endif 9702 }; 9703 9704 static const struct hda_codec_ops dbpro_patch_ops = { 9705 .build_controls = dbpro_build_controls, 9706 .build_pcms = dbpro_build_pcms, 9707 .init = dbpro_init, 9708 .free = dbpro_free, 9709 }; 9710 9711 static void ca0132_config(struct hda_codec *codec) 9712 { 9713 struct ca0132_spec *spec = codec->spec; 9714 9715 spec->dacs[0] = 0x2; 9716 spec->dacs[1] = 0x3; 9717 spec->dacs[2] = 0x4; 9718 9719 spec->multiout.dac_nids = spec->dacs; 9720 spec->multiout.num_dacs = 3; 9721 9722 if (!ca0132_use_alt_functions(spec)) 9723 spec->multiout.max_channels = 2; 9724 else 9725 spec->multiout.max_channels = 6; 9726 9727 switch (ca0132_quirk(spec)) { 9728 case QUIRK_ALIENWARE: 9729 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9730 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9731 break; 9732 case QUIRK_SBZ: 9733 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9734 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9735 break; 9736 case QUIRK_ZXR: 9737 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9738 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9739 break; 9740 case QUIRK_R3D: 9741 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9742 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9743 break; 9744 case QUIRK_R3DI: 9745 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9746 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9747 break; 9748 case QUIRK_AE5: 9749 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9750 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9751 break; 9752 case QUIRK_AE7: 9753 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9754 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9755 break; 9756 default: 9757 break; 9758 } 9759 9760 switch (ca0132_quirk(spec)) { 9761 case QUIRK_ALIENWARE: 9762 spec->num_outputs = 2; 9763 spec->out_pins[0] = 0x0b; /* speaker out */ 9764 spec->out_pins[1] = 0x0f; 9765 spec->shared_out_nid = 0x2; 9766 spec->unsol_tag_hp = 0x0f; 9767 9768 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9769 spec->adcs[1] = 0x8; /* analog mic2 */ 9770 spec->adcs[2] = 0xa; /* what u hear */ 9771 9772 spec->num_inputs = 3; 9773 spec->input_pins[0] = 0x12; 9774 spec->input_pins[1] = 0x11; 9775 spec->input_pins[2] = 0x13; 9776 spec->shared_mic_nid = 0x7; 9777 spec->unsol_tag_amic1 = 0x11; 9778 break; 9779 case QUIRK_SBZ: 9780 case QUIRK_R3D: 9781 spec->num_outputs = 2; 9782 spec->out_pins[0] = 0x0B; /* Line out */ 9783 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9784 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9785 spec->out_pins[3] = 0x11; /* Rear surround */ 9786 spec->shared_out_nid = 0x2; 9787 spec->unsol_tag_hp = spec->out_pins[1]; 9788 spec->unsol_tag_front_hp = spec->out_pins[2]; 9789 9790 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9791 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9792 spec->adcs[2] = 0xa; /* what u hear */ 9793 9794 spec->num_inputs = 2; 9795 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9796 spec->input_pins[1] = 0x13; /* What U Hear */ 9797 spec->shared_mic_nid = 0x7; 9798 spec->unsol_tag_amic1 = spec->input_pins[0]; 9799 9800 /* SPDIF I/O */ 9801 spec->dig_out = 0x05; 9802 spec->multiout.dig_out_nid = spec->dig_out; 9803 spec->dig_in = 0x09; 9804 break; 9805 case QUIRK_ZXR: 9806 spec->num_outputs = 2; 9807 spec->out_pins[0] = 0x0B; /* Line out */ 9808 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9809 spec->out_pins[2] = 0x10; /* Center/LFE */ 9810 spec->out_pins[3] = 0x11; /* Rear surround */ 9811 spec->shared_out_nid = 0x2; 9812 spec->unsol_tag_hp = spec->out_pins[1]; 9813 spec->unsol_tag_front_hp = spec->out_pins[2]; 9814 9815 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9816 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9817 spec->adcs[2] = 0xa; /* what u hear */ 9818 9819 spec->num_inputs = 2; 9820 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9821 spec->input_pins[1] = 0x13; /* What U Hear */ 9822 spec->shared_mic_nid = 0x7; 9823 spec->unsol_tag_amic1 = spec->input_pins[0]; 9824 break; 9825 case QUIRK_ZXR_DBPRO: 9826 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9827 9828 spec->num_inputs = 1; 9829 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9830 9831 spec->dig_out = 0x05; 9832 spec->multiout.dig_out_nid = spec->dig_out; 9833 9834 spec->dig_in = 0x09; 9835 break; 9836 case QUIRK_AE5: 9837 case QUIRK_AE7: 9838 spec->num_outputs = 2; 9839 spec->out_pins[0] = 0x0B; /* Line out */ 9840 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9841 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9842 spec->out_pins[3] = 0x0F; /* Rear surround */ 9843 spec->shared_out_nid = 0x2; 9844 spec->unsol_tag_hp = spec->out_pins[1]; 9845 spec->unsol_tag_front_hp = spec->out_pins[2]; 9846 9847 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9848 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9849 spec->adcs[2] = 0xa; /* what u hear */ 9850 9851 spec->num_inputs = 2; 9852 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9853 spec->input_pins[1] = 0x13; /* What U Hear */ 9854 spec->shared_mic_nid = 0x7; 9855 spec->unsol_tag_amic1 = spec->input_pins[0]; 9856 9857 /* SPDIF I/O */ 9858 spec->dig_out = 0x05; 9859 spec->multiout.dig_out_nid = spec->dig_out; 9860 break; 9861 case QUIRK_R3DI: 9862 spec->num_outputs = 2; 9863 spec->out_pins[0] = 0x0B; /* Line out */ 9864 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9865 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9866 spec->out_pins[3] = 0x11; /* Rear surround */ 9867 spec->shared_out_nid = 0x2; 9868 spec->unsol_tag_hp = spec->out_pins[1]; 9869 spec->unsol_tag_front_hp = spec->out_pins[2]; 9870 9871 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9872 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9873 spec->adcs[2] = 0x0a; /* what u hear */ 9874 9875 spec->num_inputs = 2; 9876 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9877 spec->input_pins[1] = 0x13; /* What U Hear */ 9878 spec->shared_mic_nid = 0x7; 9879 spec->unsol_tag_amic1 = spec->input_pins[0]; 9880 9881 /* SPDIF I/O */ 9882 spec->dig_out = 0x05; 9883 spec->multiout.dig_out_nid = spec->dig_out; 9884 break; 9885 default: 9886 spec->num_outputs = 2; 9887 spec->out_pins[0] = 0x0b; /* speaker out */ 9888 spec->out_pins[1] = 0x10; /* headphone out */ 9889 spec->shared_out_nid = 0x2; 9890 spec->unsol_tag_hp = spec->out_pins[1]; 9891 9892 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9893 spec->adcs[1] = 0x8; /* analog mic2 */ 9894 spec->adcs[2] = 0xa; /* what u hear */ 9895 9896 spec->num_inputs = 3; 9897 spec->input_pins[0] = 0x12; 9898 spec->input_pins[1] = 0x11; 9899 spec->input_pins[2] = 0x13; 9900 spec->shared_mic_nid = 0x7; 9901 spec->unsol_tag_amic1 = spec->input_pins[0]; 9902 9903 /* SPDIF I/O */ 9904 spec->dig_out = 0x05; 9905 spec->multiout.dig_out_nid = spec->dig_out; 9906 spec->dig_in = 0x09; 9907 break; 9908 } 9909 } 9910 9911 static int ca0132_prepare_verbs(struct hda_codec *codec) 9912 { 9913 /* Verbs + terminator (an empty element) */ 9914 #define NUM_SPEC_VERBS 2 9915 struct ca0132_spec *spec = codec->spec; 9916 9917 spec->chip_init_verbs = ca0132_init_verbs0; 9918 /* 9919 * Since desktop cards use pci_mmio, this can be used to determine 9920 * whether or not to use these verbs instead of a separate bool. 9921 */ 9922 if (ca0132_use_pci_mmio(spec)) 9923 spec->desktop_init_verbs = ca0132_init_verbs1; 9924 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9925 sizeof(struct hda_verb), 9926 GFP_KERNEL); 9927 if (!spec->spec_init_verbs) 9928 return -ENOMEM; 9929 9930 /* config EAPD */ 9931 spec->spec_init_verbs[0].nid = 0x0b; 9932 spec->spec_init_verbs[0].param = 0x78D; 9933 spec->spec_init_verbs[0].verb = 0x00; 9934 9935 /* Previously commented configuration */ 9936 /* 9937 spec->spec_init_verbs[2].nid = 0x0b; 9938 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9939 spec->spec_init_verbs[2].verb = 0x02; 9940 9941 spec->spec_init_verbs[3].nid = 0x10; 9942 spec->spec_init_verbs[3].param = 0x78D; 9943 spec->spec_init_verbs[3].verb = 0x02; 9944 9945 spec->spec_init_verbs[4].nid = 0x10; 9946 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9947 spec->spec_init_verbs[4].verb = 0x02; 9948 */ 9949 9950 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9951 return 0; 9952 } 9953 9954 /* 9955 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9956 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9957 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9958 * daughter boards ID. 9959 */ 9960 static void sbz_detect_quirk(struct hda_codec *codec) 9961 { 9962 struct ca0132_spec *spec = codec->spec; 9963 9964 switch (codec->core.subsystem_id) { 9965 case 0x11020033: 9966 spec->quirk = QUIRK_ZXR; 9967 break; 9968 case 0x1102003f: 9969 spec->quirk = QUIRK_ZXR_DBPRO; 9970 break; 9971 default: 9972 spec->quirk = QUIRK_SBZ; 9973 break; 9974 } 9975 } 9976 9977 static int patch_ca0132(struct hda_codec *codec) 9978 { 9979 struct ca0132_spec *spec; 9980 int err; 9981 const struct snd_pci_quirk *quirk; 9982 9983 codec_dbg(codec, "patch_ca0132\n"); 9984 9985 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9986 if (!spec) 9987 return -ENOMEM; 9988 codec->spec = spec; 9989 spec->codec = codec; 9990 9991 /* Detect codec quirk */ 9992 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 9993 if (quirk) 9994 spec->quirk = quirk->value; 9995 else 9996 spec->quirk = QUIRK_NONE; 9997 if (ca0132_quirk(spec) == QUIRK_SBZ) 9998 sbz_detect_quirk(codec); 9999 10000 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10001 codec->patch_ops = dbpro_patch_ops; 10002 else 10003 codec->patch_ops = ca0132_patch_ops; 10004 10005 codec->pcm_format_first = 1; 10006 codec->no_sticky_stream = 1; 10007 10008 10009 spec->dsp_state = DSP_DOWNLOAD_INIT; 10010 spec->num_mixers = 1; 10011 10012 /* Set which mixers each quirk uses. */ 10013 switch (ca0132_quirk(spec)) { 10014 case QUIRK_SBZ: 10015 spec->mixers[0] = desktop_mixer; 10016 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10017 break; 10018 case QUIRK_ZXR: 10019 spec->mixers[0] = desktop_mixer; 10020 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10021 break; 10022 case QUIRK_ZXR_DBPRO: 10023 break; 10024 case QUIRK_R3D: 10025 spec->mixers[0] = desktop_mixer; 10026 snd_hda_codec_set_name(codec, "Recon3D"); 10027 break; 10028 case QUIRK_R3DI: 10029 spec->mixers[0] = r3di_mixer; 10030 snd_hda_codec_set_name(codec, "Recon3Di"); 10031 break; 10032 case QUIRK_AE5: 10033 spec->mixers[0] = desktop_mixer; 10034 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10035 break; 10036 case QUIRK_AE7: 10037 spec->mixers[0] = desktop_mixer; 10038 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10039 break; 10040 default: 10041 spec->mixers[0] = ca0132_mixer; 10042 break; 10043 } 10044 10045 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10046 switch (ca0132_quirk(spec)) { 10047 case QUIRK_SBZ: 10048 case QUIRK_R3D: 10049 case QUIRK_AE5: 10050 case QUIRK_AE7: 10051 case QUIRK_ZXR: 10052 spec->use_alt_controls = true; 10053 spec->use_alt_functions = true; 10054 spec->use_pci_mmio = true; 10055 break; 10056 case QUIRK_R3DI: 10057 spec->use_alt_controls = true; 10058 spec->use_alt_functions = true; 10059 spec->use_pci_mmio = false; 10060 break; 10061 default: 10062 spec->use_alt_controls = false; 10063 spec->use_alt_functions = false; 10064 spec->use_pci_mmio = false; 10065 break; 10066 } 10067 10068 #ifdef CONFIG_PCI 10069 if (spec->use_pci_mmio) { 10070 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10071 if (spec->mem_base == NULL) { 10072 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10073 spec->quirk = QUIRK_NONE; 10074 } 10075 } 10076 #endif 10077 10078 spec->base_init_verbs = ca0132_base_init_verbs; 10079 spec->base_exit_verbs = ca0132_base_exit_verbs; 10080 10081 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10082 10083 ca0132_init_chip(codec); 10084 10085 ca0132_config(codec); 10086 10087 err = ca0132_prepare_verbs(codec); 10088 if (err < 0) 10089 goto error; 10090 10091 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10092 if (err < 0) 10093 goto error; 10094 10095 ca0132_setup_unsol(codec); 10096 10097 return 0; 10098 10099 error: 10100 ca0132_free(codec); 10101 return err; 10102 } 10103 10104 /* 10105 * patch entries 10106 */ 10107 static const struct hda_device_id snd_hda_id_ca0132[] = { 10108 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 10109 {} /* terminator */ 10110 }; 10111 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10112 10113 MODULE_LICENSE("GPL"); 10114 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10115 10116 static struct hda_codec_driver ca0132_driver = { 10117 .id = snd_hda_id_ca0132, 10118 }; 10119 10120 module_hda_codec_driver(ca0132_driver); 10121