109c434b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2decbc00eSZhengShunQian /*
3decbc00eSZhengShunQian * Driver of Inno codec for rk3036 by Rockchip Inc.
4decbc00eSZhengShunQian *
5decbc00eSZhengShunQian * Author: Rockchip Inc.
6decbc00eSZhengShunQian * Author: Zheng ShunQian<zhengsq@rock-chips.com>
7decbc00eSZhengShunQian */
8decbc00eSZhengShunQian
9decbc00eSZhengShunQian #include <sound/soc.h>
10decbc00eSZhengShunQian #include <sound/tlv.h>
11decbc00eSZhengShunQian #include <sound/soc-dapm.h>
12decbc00eSZhengShunQian #include <sound/soc-dai.h>
13decbc00eSZhengShunQian #include <sound/pcm.h>
14decbc00eSZhengShunQian #include <sound/pcm_params.h>
15decbc00eSZhengShunQian
16decbc00eSZhengShunQian #include <linux/platform_device.h>
17decbc00eSZhengShunQian #include <linux/of.h>
18decbc00eSZhengShunQian #include <linux/clk.h>
19decbc00eSZhengShunQian #include <linux/regmap.h>
20decbc00eSZhengShunQian #include <linux/device.h>
21decbc00eSZhengShunQian #include <linux/mfd/syscon.h>
22decbc00eSZhengShunQian #include <linux/module.h>
23decbc00eSZhengShunQian #include <linux/io.h>
24decbc00eSZhengShunQian
25decbc00eSZhengShunQian #include "inno_rk3036.h"
26decbc00eSZhengShunQian
27decbc00eSZhengShunQian struct rk3036_codec_priv {
28decbc00eSZhengShunQian void __iomem *base;
29decbc00eSZhengShunQian struct clk *pclk;
30decbc00eSZhengShunQian struct regmap *regmap;
31decbc00eSZhengShunQian struct device *dev;
32decbc00eSZhengShunQian };
33decbc00eSZhengShunQian
34decbc00eSZhengShunQian static const DECLARE_TLV_DB_MINMAX(rk3036_codec_hp_tlv, -39, 0);
35decbc00eSZhengShunQian
rk3036_codec_antipop_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)36decbc00eSZhengShunQian static int rk3036_codec_antipop_info(struct snd_kcontrol *kcontrol,
37decbc00eSZhengShunQian struct snd_ctl_elem_info *uinfo)
38decbc00eSZhengShunQian {
39decbc00eSZhengShunQian uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
40decbc00eSZhengShunQian uinfo->count = 2;
41decbc00eSZhengShunQian uinfo->value.integer.min = 0;
42decbc00eSZhengShunQian uinfo->value.integer.max = 1;
43decbc00eSZhengShunQian
44decbc00eSZhengShunQian return 0;
45decbc00eSZhengShunQian }
46decbc00eSZhengShunQian
rk3036_codec_antipop_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)47decbc00eSZhengShunQian static int rk3036_codec_antipop_get(struct snd_kcontrol *kcontrol,
48decbc00eSZhengShunQian struct snd_ctl_elem_value *ucontrol)
49decbc00eSZhengShunQian {
50decbc00eSZhengShunQian struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
51cf6e26c7SKuninori Morimoto int val, regval;
52decbc00eSZhengShunQian
53cf6e26c7SKuninori Morimoto regval = snd_soc_component_read(component, INNO_R09);
54decbc00eSZhengShunQian val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) &
55decbc00eSZhengShunQian INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON;
56decbc00eSZhengShunQian ucontrol->value.integer.value[0] = val;
57decbc00eSZhengShunQian
58decbc00eSZhengShunQian val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) &
59decbc00eSZhengShunQian INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON;
60decbc00eSZhengShunQian ucontrol->value.integer.value[1] = val;
61decbc00eSZhengShunQian
62decbc00eSZhengShunQian return 0;
63decbc00eSZhengShunQian }
64decbc00eSZhengShunQian
rk3036_codec_antipop_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)65decbc00eSZhengShunQian static int rk3036_codec_antipop_put(struct snd_kcontrol *kcontrol,
66decbc00eSZhengShunQian struct snd_ctl_elem_value *ucontrol)
67decbc00eSZhengShunQian {
68decbc00eSZhengShunQian struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
69decbc00eSZhengShunQian int val, ret, regmsk;
70decbc00eSZhengShunQian
71decbc00eSZhengShunQian val = (ucontrol->value.integer.value[0] ?
72decbc00eSZhengShunQian INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) <<
73decbc00eSZhengShunQian INNO_R09_HPL_ANITPOP_SHIFT;
74decbc00eSZhengShunQian val |= (ucontrol->value.integer.value[1] ?
75decbc00eSZhengShunQian INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) <<
76decbc00eSZhengShunQian INNO_R09_HPR_ANITPOP_SHIFT;
77decbc00eSZhengShunQian
78decbc00eSZhengShunQian regmsk = INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPL_ANITPOP_SHIFT |
79decbc00eSZhengShunQian INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPR_ANITPOP_SHIFT;
80decbc00eSZhengShunQian
81decbc00eSZhengShunQian ret = snd_soc_component_update_bits(component, INNO_R09,
82decbc00eSZhengShunQian regmsk, val);
83decbc00eSZhengShunQian if (ret < 0)
84decbc00eSZhengShunQian return ret;
85decbc00eSZhengShunQian
86decbc00eSZhengShunQian return 0;
87decbc00eSZhengShunQian }
88decbc00eSZhengShunQian
89decbc00eSZhengShunQian #define SOC_RK3036_CODEC_ANTIPOP_DECL(xname) \
90decbc00eSZhengShunQian { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
91decbc00eSZhengShunQian .info = rk3036_codec_antipop_info, .get = rk3036_codec_antipop_get, \
92decbc00eSZhengShunQian .put = rk3036_codec_antipop_put, }
93decbc00eSZhengShunQian
94decbc00eSZhengShunQian static const struct snd_kcontrol_new rk3036_codec_dapm_controls[] = {
95decbc00eSZhengShunQian SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", INNO_R07, INNO_R08,
96decbc00eSZhengShunQian INNO_HP_GAIN_SHIFT, INNO_HP_GAIN_N39DB,
97decbc00eSZhengShunQian INNO_HP_GAIN_0DB, 0, rk3036_codec_hp_tlv),
98decbc00eSZhengShunQian SOC_DOUBLE("Zero Cross Switch", INNO_R06, INNO_R06_VOUTL_CZ_SHIFT,
99decbc00eSZhengShunQian INNO_R06_VOUTR_CZ_SHIFT, 1, 0),
100decbc00eSZhengShunQian SOC_DOUBLE("Headphone Switch", INNO_R09, INNO_R09_HPL_MUTE_SHIFT,
101decbc00eSZhengShunQian INNO_R09_HPR_MUTE_SHIFT, 1, 0),
102decbc00eSZhengShunQian SOC_RK3036_CODEC_ANTIPOP_DECL("Anti-pop Switch"),
103decbc00eSZhengShunQian };
104decbc00eSZhengShunQian
105decbc00eSZhengShunQian static const struct snd_kcontrol_new rk3036_codec_hpl_mixer_controls[] = {
106decbc00eSZhengShunQian SOC_DAPM_SINGLE("DAC Left Out Switch", INNO_R09,
107decbc00eSZhengShunQian INNO_R09_DACL_SWITCH_SHIFT, 1, 0),
108decbc00eSZhengShunQian };
109decbc00eSZhengShunQian
110decbc00eSZhengShunQian static const struct snd_kcontrol_new rk3036_codec_hpr_mixer_controls[] = {
111decbc00eSZhengShunQian SOC_DAPM_SINGLE("DAC Right Out Switch", INNO_R09,
112decbc00eSZhengShunQian INNO_R09_DACR_SWITCH_SHIFT, 1, 0),
113decbc00eSZhengShunQian };
114decbc00eSZhengShunQian
115decbc00eSZhengShunQian static const struct snd_kcontrol_new rk3036_codec_hpl_switch_controls[] = {
116decbc00eSZhengShunQian SOC_DAPM_SINGLE("HP Left Out Switch", INNO_R05,
117decbc00eSZhengShunQian INNO_R05_HPL_WORK_SHIFT, 1, 0),
118decbc00eSZhengShunQian };
119decbc00eSZhengShunQian
120decbc00eSZhengShunQian static const struct snd_kcontrol_new rk3036_codec_hpr_switch_controls[] = {
121decbc00eSZhengShunQian SOC_DAPM_SINGLE("HP Right Out Switch", INNO_R05,
122decbc00eSZhengShunQian INNO_R05_HPR_WORK_SHIFT, 1, 0),
123decbc00eSZhengShunQian };
124decbc00eSZhengShunQian
125decbc00eSZhengShunQian static const struct snd_soc_dapm_widget rk3036_codec_dapm_widgets[] = {
126decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DAC PWR", 1, INNO_R06,
127decbc00eSZhengShunQian INNO_R06_DAC_EN_SHIFT, 0, NULL, 0),
128decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACL VREF", 2, INNO_R04,
129decbc00eSZhengShunQian INNO_R04_DACL_VREF_SHIFT, 0, NULL, 0),
130decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACR VREF", 2, INNO_R04,
131decbc00eSZhengShunQian INNO_R04_DACR_VREF_SHIFT, 0, NULL, 0),
132decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACL HiLo VREF", 3, INNO_R06,
133decbc00eSZhengShunQian INNO_R06_DACL_HILO_VREF_SHIFT, 0, NULL, 0),
134decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACR HiLo VREF", 3, INNO_R06,
135decbc00eSZhengShunQian INNO_R06_DACR_HILO_VREF_SHIFT, 0, NULL, 0),
136decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACR CLK", 3, INNO_R04,
137decbc00eSZhengShunQian INNO_R04_DACR_CLK_SHIFT, 0, NULL, 0),
138decbc00eSZhengShunQian SND_SOC_DAPM_SUPPLY_S("DACL CLK", 3, INNO_R04,
139decbc00eSZhengShunQian INNO_R04_DACL_CLK_SHIFT, 0, NULL, 0),
140decbc00eSZhengShunQian
141decbc00eSZhengShunQian SND_SOC_DAPM_DAC("DACL", "Left Playback", INNO_R04,
142decbc00eSZhengShunQian INNO_R04_DACL_SW_SHIFT, 0),
143decbc00eSZhengShunQian SND_SOC_DAPM_DAC("DACR", "Right Playback", INNO_R04,
144decbc00eSZhengShunQian INNO_R04_DACR_SW_SHIFT, 0),
145decbc00eSZhengShunQian
146decbc00eSZhengShunQian SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
147decbc00eSZhengShunQian rk3036_codec_hpl_mixer_controls,
148decbc00eSZhengShunQian ARRAY_SIZE(rk3036_codec_hpl_mixer_controls)),
149decbc00eSZhengShunQian SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
150decbc00eSZhengShunQian rk3036_codec_hpr_mixer_controls,
151decbc00eSZhengShunQian ARRAY_SIZE(rk3036_codec_hpr_mixer_controls)),
152decbc00eSZhengShunQian
153decbc00eSZhengShunQian SND_SOC_DAPM_PGA("HP Left Out", INNO_R05,
154decbc00eSZhengShunQian INNO_R05_HPL_EN_SHIFT, 0, NULL, 0),
155decbc00eSZhengShunQian SND_SOC_DAPM_PGA("HP Right Out", INNO_R05,
156decbc00eSZhengShunQian INNO_R05_HPR_EN_SHIFT, 0, NULL, 0),
157decbc00eSZhengShunQian
158decbc00eSZhengShunQian SND_SOC_DAPM_MIXER("HP Left Switch", SND_SOC_NOPM, 0, 0,
159decbc00eSZhengShunQian rk3036_codec_hpl_switch_controls,
160decbc00eSZhengShunQian ARRAY_SIZE(rk3036_codec_hpl_switch_controls)),
161decbc00eSZhengShunQian SND_SOC_DAPM_MIXER("HP Right Switch", SND_SOC_NOPM, 0, 0,
162decbc00eSZhengShunQian rk3036_codec_hpr_switch_controls,
163decbc00eSZhengShunQian ARRAY_SIZE(rk3036_codec_hpr_switch_controls)),
164decbc00eSZhengShunQian
165decbc00eSZhengShunQian SND_SOC_DAPM_OUTPUT("HPL"),
166decbc00eSZhengShunQian SND_SOC_DAPM_OUTPUT("HPR"),
167decbc00eSZhengShunQian };
168decbc00eSZhengShunQian
169decbc00eSZhengShunQian static const struct snd_soc_dapm_route rk3036_codec_dapm_routes[] = {
170decbc00eSZhengShunQian {"DACL VREF", NULL, "DAC PWR"},
171decbc00eSZhengShunQian {"DACR VREF", NULL, "DAC PWR"},
172decbc00eSZhengShunQian {"DACL HiLo VREF", NULL, "DAC PWR"},
173decbc00eSZhengShunQian {"DACR HiLo VREF", NULL, "DAC PWR"},
174decbc00eSZhengShunQian {"DACL CLK", NULL, "DAC PWR"},
175decbc00eSZhengShunQian {"DACR CLK", NULL, "DAC PWR"},
176decbc00eSZhengShunQian
177decbc00eSZhengShunQian {"DACL", NULL, "DACL VREF"},
178decbc00eSZhengShunQian {"DACL", NULL, "DACL HiLo VREF"},
179decbc00eSZhengShunQian {"DACL", NULL, "DACL CLK"},
180decbc00eSZhengShunQian {"DACR", NULL, "DACR VREF"},
181decbc00eSZhengShunQian {"DACR", NULL, "DACR HiLo VREF"},
182decbc00eSZhengShunQian {"DACR", NULL, "DACR CLK"},
183decbc00eSZhengShunQian
184decbc00eSZhengShunQian {"Left Headphone Mixer", "DAC Left Out Switch", "DACL"},
185decbc00eSZhengShunQian {"Right Headphone Mixer", "DAC Right Out Switch", "DACR"},
186decbc00eSZhengShunQian {"HP Left Out", NULL, "Left Headphone Mixer"},
187decbc00eSZhengShunQian {"HP Right Out", NULL, "Right Headphone Mixer"},
188decbc00eSZhengShunQian
189decbc00eSZhengShunQian {"HP Left Switch", "HP Left Out Switch", "HP Left Out"},
190decbc00eSZhengShunQian {"HP Right Switch", "HP Right Out Switch", "HP Right Out"},
191decbc00eSZhengShunQian
192decbc00eSZhengShunQian {"HPL", NULL, "HP Left Switch"},
193decbc00eSZhengShunQian {"HPR", NULL, "HP Right Switch"},
194decbc00eSZhengShunQian };
195decbc00eSZhengShunQian
rk3036_codec_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)196decbc00eSZhengShunQian static int rk3036_codec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
197decbc00eSZhengShunQian {
19840aa60a2SKuninori Morimoto struct snd_soc_component *component = dai->component;
199decbc00eSZhengShunQian unsigned int reg01_val = 0, reg02_val = 0, reg03_val = 0;
200decbc00eSZhengShunQian
20140aa60a2SKuninori Morimoto dev_dbg(component->dev, "rk3036_codec dai set fmt : %08x\n", fmt);
202decbc00eSZhengShunQian
20358d858aeSMark Brown switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
20458d858aeSMark Brown case SND_SOC_DAIFMT_CBC_CFC:
205decbc00eSZhengShunQian reg01_val |= INNO_R01_PINDIR_IN_SLAVE |
206decbc00eSZhengShunQian INNO_R01_I2SMODE_SLAVE;
207decbc00eSZhengShunQian break;
20858d858aeSMark Brown case SND_SOC_DAIFMT_CBP_CFP:
209decbc00eSZhengShunQian reg01_val |= INNO_R01_PINDIR_OUT_MASTER |
210decbc00eSZhengShunQian INNO_R01_I2SMODE_MASTER;
211decbc00eSZhengShunQian break;
212decbc00eSZhengShunQian default:
21340aa60a2SKuninori Morimoto dev_err(component->dev, "invalid fmt\n");
214decbc00eSZhengShunQian return -EINVAL;
215decbc00eSZhengShunQian }
216decbc00eSZhengShunQian
217decbc00eSZhengShunQian switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
218decbc00eSZhengShunQian case SND_SOC_DAIFMT_DSP_A:
219decbc00eSZhengShunQian reg02_val |= INNO_R02_DACM_PCM;
220decbc00eSZhengShunQian break;
221decbc00eSZhengShunQian case SND_SOC_DAIFMT_I2S:
222decbc00eSZhengShunQian reg02_val |= INNO_R02_DACM_I2S;
223decbc00eSZhengShunQian break;
224decbc00eSZhengShunQian case SND_SOC_DAIFMT_RIGHT_J:
225decbc00eSZhengShunQian reg02_val |= INNO_R02_DACM_RJM;
226decbc00eSZhengShunQian break;
227decbc00eSZhengShunQian case SND_SOC_DAIFMT_LEFT_J:
228decbc00eSZhengShunQian reg02_val |= INNO_R02_DACM_LJM;
229decbc00eSZhengShunQian break;
230decbc00eSZhengShunQian default:
23140aa60a2SKuninori Morimoto dev_err(component->dev, "set dai format failed\n");
232decbc00eSZhengShunQian return -EINVAL;
233decbc00eSZhengShunQian }
234decbc00eSZhengShunQian
235decbc00eSZhengShunQian switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
236decbc00eSZhengShunQian case SND_SOC_DAIFMT_NB_NF:
237decbc00eSZhengShunQian reg02_val |= INNO_R02_LRCP_NORMAL;
238decbc00eSZhengShunQian reg03_val |= INNO_R03_BCP_NORMAL;
239decbc00eSZhengShunQian break;
240decbc00eSZhengShunQian case SND_SOC_DAIFMT_IB_IF:
241decbc00eSZhengShunQian reg02_val |= INNO_R02_LRCP_REVERSAL;
242decbc00eSZhengShunQian reg03_val |= INNO_R03_BCP_REVERSAL;
243decbc00eSZhengShunQian break;
244decbc00eSZhengShunQian case SND_SOC_DAIFMT_IB_NF:
245decbc00eSZhengShunQian reg02_val |= INNO_R02_LRCP_REVERSAL;
246decbc00eSZhengShunQian reg03_val |= INNO_R03_BCP_NORMAL;
247decbc00eSZhengShunQian break;
248decbc00eSZhengShunQian case SND_SOC_DAIFMT_NB_IF:
249decbc00eSZhengShunQian reg02_val |= INNO_R02_LRCP_NORMAL;
250decbc00eSZhengShunQian reg03_val |= INNO_R03_BCP_REVERSAL;
251decbc00eSZhengShunQian break;
252decbc00eSZhengShunQian default:
25340aa60a2SKuninori Morimoto dev_err(component->dev, "set dai format failed\n");
254decbc00eSZhengShunQian return -EINVAL;
255decbc00eSZhengShunQian }
256decbc00eSZhengShunQian
25740aa60a2SKuninori Morimoto snd_soc_component_update_bits(component, INNO_R01, INNO_R01_I2SMODE_MSK |
258decbc00eSZhengShunQian INNO_R01_PINDIR_MSK, reg01_val);
25940aa60a2SKuninori Morimoto snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
260decbc00eSZhengShunQian INNO_R02_DACM_MSK, reg02_val);
26140aa60a2SKuninori Morimoto snd_soc_component_update_bits(component, INNO_R03, INNO_R03_BCP_MSK, reg03_val);
262decbc00eSZhengShunQian
263decbc00eSZhengShunQian return 0;
264decbc00eSZhengShunQian }
265decbc00eSZhengShunQian
rk3036_codec_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params,struct snd_soc_dai * dai)266decbc00eSZhengShunQian static int rk3036_codec_dai_hw_params(struct snd_pcm_substream *substream,
267decbc00eSZhengShunQian struct snd_pcm_hw_params *hw_params,
268decbc00eSZhengShunQian struct snd_soc_dai *dai)
269decbc00eSZhengShunQian {
27040aa60a2SKuninori Morimoto struct snd_soc_component *component = dai->component;
271decbc00eSZhengShunQian unsigned int reg02_val = 0, reg03_val = 0;
272decbc00eSZhengShunQian
273decbc00eSZhengShunQian switch (params_format(hw_params)) {
274decbc00eSZhengShunQian case SNDRV_PCM_FORMAT_S16_LE:
275decbc00eSZhengShunQian reg02_val |= INNO_R02_VWL_16BIT;
276decbc00eSZhengShunQian break;
277decbc00eSZhengShunQian case SNDRV_PCM_FORMAT_S20_3LE:
278decbc00eSZhengShunQian reg02_val |= INNO_R02_VWL_20BIT;
279decbc00eSZhengShunQian break;
280decbc00eSZhengShunQian case SNDRV_PCM_FORMAT_S24_LE:
281decbc00eSZhengShunQian reg02_val |= INNO_R02_VWL_24BIT;
282decbc00eSZhengShunQian break;
283decbc00eSZhengShunQian case SNDRV_PCM_FORMAT_S32_LE:
284decbc00eSZhengShunQian reg02_val |= INNO_R02_VWL_32BIT;
285decbc00eSZhengShunQian break;
286decbc00eSZhengShunQian default:
287decbc00eSZhengShunQian return -EINVAL;
288decbc00eSZhengShunQian }
289decbc00eSZhengShunQian
290decbc00eSZhengShunQian reg02_val |= INNO_R02_LRCP_NORMAL;
291decbc00eSZhengShunQian reg03_val |= INNO_R03_FWL_32BIT | INNO_R03_DACR_WORK;
292decbc00eSZhengShunQian
29340aa60a2SKuninori Morimoto snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
294decbc00eSZhengShunQian INNO_R02_VWL_MSK, reg02_val);
29540aa60a2SKuninori Morimoto snd_soc_component_update_bits(component, INNO_R03, INNO_R03_DACR_MSK |
296decbc00eSZhengShunQian INNO_R03_FWL_MSK, reg03_val);
297decbc00eSZhengShunQian return 0;
298decbc00eSZhengShunQian }
299decbc00eSZhengShunQian
300decbc00eSZhengShunQian #define RK3036_CODEC_RATES (SNDRV_PCM_RATE_8000 | \
301decbc00eSZhengShunQian SNDRV_PCM_RATE_16000 | \
302decbc00eSZhengShunQian SNDRV_PCM_RATE_32000 | \
303decbc00eSZhengShunQian SNDRV_PCM_RATE_44100 | \
304decbc00eSZhengShunQian SNDRV_PCM_RATE_48000 | \
305decbc00eSZhengShunQian SNDRV_PCM_RATE_96000)
306decbc00eSZhengShunQian
307decbc00eSZhengShunQian #define RK3036_CODEC_FMTS (SNDRV_PCM_FMTBIT_S16_LE | \
308decbc00eSZhengShunQian SNDRV_PCM_FMTBIT_S20_3LE | \
309decbc00eSZhengShunQian SNDRV_PCM_FMTBIT_S24_LE | \
310decbc00eSZhengShunQian SNDRV_PCM_FMTBIT_S32_LE)
311decbc00eSZhengShunQian
312eb59d73cSArvind Yadav static const struct snd_soc_dai_ops rk3036_codec_dai_ops = {
313decbc00eSZhengShunQian .set_fmt = rk3036_codec_dai_set_fmt,
314decbc00eSZhengShunQian .hw_params = rk3036_codec_dai_hw_params,
315decbc00eSZhengShunQian };
316decbc00eSZhengShunQian
317decbc00eSZhengShunQian static struct snd_soc_dai_driver rk3036_codec_dai_driver[] = {
318decbc00eSZhengShunQian {
319decbc00eSZhengShunQian .name = "rk3036-codec-dai",
320decbc00eSZhengShunQian .playback = {
321decbc00eSZhengShunQian .stream_name = "Playback",
322decbc00eSZhengShunQian .channels_min = 1,
323decbc00eSZhengShunQian .channels_max = 2,
324decbc00eSZhengShunQian .rates = RK3036_CODEC_RATES,
325decbc00eSZhengShunQian .formats = RK3036_CODEC_FMTS,
326decbc00eSZhengShunQian },
327decbc00eSZhengShunQian .ops = &rk3036_codec_dai_ops,
328d5d396c8SKuninori Morimoto .symmetric_rate = 1,
329decbc00eSZhengShunQian },
330decbc00eSZhengShunQian };
331decbc00eSZhengShunQian
rk3036_codec_reset(struct snd_soc_component * component)33240aa60a2SKuninori Morimoto static void rk3036_codec_reset(struct snd_soc_component *component)
333decbc00eSZhengShunQian {
33440aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R00,
335decbc00eSZhengShunQian INNO_R00_CSR_RESET | INNO_R00_CDCR_RESET);
33640aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R00,
337decbc00eSZhengShunQian INNO_R00_CSR_WORK | INNO_R00_CDCR_WORK);
338decbc00eSZhengShunQian }
339decbc00eSZhengShunQian
rk3036_codec_probe(struct snd_soc_component * component)34040aa60a2SKuninori Morimoto static int rk3036_codec_probe(struct snd_soc_component *component)
341decbc00eSZhengShunQian {
34240aa60a2SKuninori Morimoto rk3036_codec_reset(component);
343decbc00eSZhengShunQian return 0;
344decbc00eSZhengShunQian }
345decbc00eSZhengShunQian
rk3036_codec_remove(struct snd_soc_component * component)34640aa60a2SKuninori Morimoto static void rk3036_codec_remove(struct snd_soc_component *component)
347decbc00eSZhengShunQian {
34840aa60a2SKuninori Morimoto rk3036_codec_reset(component);
349decbc00eSZhengShunQian }
350decbc00eSZhengShunQian
rk3036_codec_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)35140aa60a2SKuninori Morimoto static int rk3036_codec_set_bias_level(struct snd_soc_component *component,
352decbc00eSZhengShunQian enum snd_soc_bias_level level)
353decbc00eSZhengShunQian {
354decbc00eSZhengShunQian switch (level) {
355decbc00eSZhengShunQian case SND_SOC_BIAS_STANDBY:
356decbc00eSZhengShunQian /* set a big current for capacitor charging. */
35740aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R10, INNO_R10_MAX_CUR);
358decbc00eSZhengShunQian /* start precharge */
35940aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_PRECHARGE);
360decbc00eSZhengShunQian
361decbc00eSZhengShunQian break;
362decbc00eSZhengShunQian
363decbc00eSZhengShunQian case SND_SOC_BIAS_OFF:
364decbc00eSZhengShunQian /* set a big current for capacitor discharging. */
36540aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R10, INNO_R10_MAX_CUR);
366decbc00eSZhengShunQian /* start discharge. */
36740aa60a2SKuninori Morimoto snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_DISCHARGE);
368decbc00eSZhengShunQian
369decbc00eSZhengShunQian break;
370decbc00eSZhengShunQian default:
371decbc00eSZhengShunQian break;
372decbc00eSZhengShunQian }
373decbc00eSZhengShunQian
374decbc00eSZhengShunQian return 0;
375decbc00eSZhengShunQian }
376decbc00eSZhengShunQian
37740aa60a2SKuninori Morimoto static const struct snd_soc_component_driver rk3036_codec_driver = {
378decbc00eSZhengShunQian .probe = rk3036_codec_probe,
379decbc00eSZhengShunQian .remove = rk3036_codec_remove,
380decbc00eSZhengShunQian .set_bias_level = rk3036_codec_set_bias_level,
381decbc00eSZhengShunQian .controls = rk3036_codec_dapm_controls,
382decbc00eSZhengShunQian .num_controls = ARRAY_SIZE(rk3036_codec_dapm_controls),
383decbc00eSZhengShunQian .dapm_routes = rk3036_codec_dapm_routes,
384decbc00eSZhengShunQian .num_dapm_routes = ARRAY_SIZE(rk3036_codec_dapm_routes),
385decbc00eSZhengShunQian .dapm_widgets = rk3036_codec_dapm_widgets,
386decbc00eSZhengShunQian .num_dapm_widgets = ARRAY_SIZE(rk3036_codec_dapm_widgets),
38740aa60a2SKuninori Morimoto .idle_bias_on = 1,
38840aa60a2SKuninori Morimoto .use_pmdown_time = 1,
38940aa60a2SKuninori Morimoto .endianness = 1,
390decbc00eSZhengShunQian };
391decbc00eSZhengShunQian
392decbc00eSZhengShunQian static const struct regmap_config rk3036_codec_regmap_config = {
393decbc00eSZhengShunQian .reg_bits = 32,
394decbc00eSZhengShunQian .reg_stride = 4,
395decbc00eSZhengShunQian .val_bits = 32,
396decbc00eSZhengShunQian };
397decbc00eSZhengShunQian
398decbc00eSZhengShunQian #define GRF_SOC_CON0 0x00140
399decbc00eSZhengShunQian #define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10))
400decbc00eSZhengShunQian
rk3036_codec_platform_probe(struct platform_device * pdev)401decbc00eSZhengShunQian static int rk3036_codec_platform_probe(struct platform_device *pdev)
402decbc00eSZhengShunQian {
403decbc00eSZhengShunQian struct rk3036_codec_priv *priv;
404decbc00eSZhengShunQian struct device_node *of_node = pdev->dev.of_node;
405decbc00eSZhengShunQian void __iomem *base;
406decbc00eSZhengShunQian struct regmap *grf;
407decbc00eSZhengShunQian int ret;
408decbc00eSZhengShunQian
409decbc00eSZhengShunQian priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
410decbc00eSZhengShunQian if (!priv)
411decbc00eSZhengShunQian return -ENOMEM;
412decbc00eSZhengShunQian
4132d1ffc7dSYueHaibing base = devm_platform_ioremap_resource(pdev, 0);
414decbc00eSZhengShunQian if (IS_ERR(base))
415decbc00eSZhengShunQian return PTR_ERR(base);
416decbc00eSZhengShunQian
417decbc00eSZhengShunQian priv->base = base;
418decbc00eSZhengShunQian priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base,
419decbc00eSZhengShunQian &rk3036_codec_regmap_config);
420decbc00eSZhengShunQian if (IS_ERR(priv->regmap)) {
421decbc00eSZhengShunQian dev_err(&pdev->dev, "init regmap failed\n");
422decbc00eSZhengShunQian return PTR_ERR(priv->regmap);
423decbc00eSZhengShunQian }
424decbc00eSZhengShunQian
425decbc00eSZhengShunQian grf = syscon_regmap_lookup_by_phandle(of_node, "rockchip,grf");
426decbc00eSZhengShunQian if (IS_ERR(grf)) {
427decbc00eSZhengShunQian dev_err(&pdev->dev, "needs 'rockchip,grf' property\n");
428decbc00eSZhengShunQian return PTR_ERR(grf);
429decbc00eSZhengShunQian }
430decbc00eSZhengShunQian ret = regmap_write(grf, GRF_SOC_CON0, GRF_ACODEC_SEL);
431decbc00eSZhengShunQian if (ret) {
432decbc00eSZhengShunQian dev_err(&pdev->dev, "Could not write to GRF: %d\n", ret);
433decbc00eSZhengShunQian return ret;
434decbc00eSZhengShunQian }
435decbc00eSZhengShunQian
436decbc00eSZhengShunQian priv->pclk = devm_clk_get(&pdev->dev, "acodec_pclk");
437decbc00eSZhengShunQian if (IS_ERR(priv->pclk))
438decbc00eSZhengShunQian return PTR_ERR(priv->pclk);
439decbc00eSZhengShunQian
440decbc00eSZhengShunQian ret = clk_prepare_enable(priv->pclk);
441decbc00eSZhengShunQian if (ret < 0) {
442decbc00eSZhengShunQian dev_err(&pdev->dev, "failed to enable clk\n");
443decbc00eSZhengShunQian return ret;
444decbc00eSZhengShunQian }
445decbc00eSZhengShunQian
446decbc00eSZhengShunQian priv->dev = &pdev->dev;
447decbc00eSZhengShunQian dev_set_drvdata(&pdev->dev, priv);
448decbc00eSZhengShunQian
44940aa60a2SKuninori Morimoto ret = devm_snd_soc_register_component(&pdev->dev, &rk3036_codec_driver,
450decbc00eSZhengShunQian rk3036_codec_dai_driver,
451decbc00eSZhengShunQian ARRAY_SIZE(rk3036_codec_dai_driver));
452decbc00eSZhengShunQian if (ret) {
453decbc00eSZhengShunQian clk_disable_unprepare(priv->pclk);
454decbc00eSZhengShunQian dev_set_drvdata(&pdev->dev, NULL);
455decbc00eSZhengShunQian }
456decbc00eSZhengShunQian
457decbc00eSZhengShunQian return ret;
458decbc00eSZhengShunQian }
459decbc00eSZhengShunQian
rk3036_codec_platform_remove(struct platform_device * pdev)460*8756b2ecSUwe Kleine-König static void rk3036_codec_platform_remove(struct platform_device *pdev)
461decbc00eSZhengShunQian {
462decbc00eSZhengShunQian struct rk3036_codec_priv *priv = dev_get_drvdata(&pdev->dev);
463decbc00eSZhengShunQian
464decbc00eSZhengShunQian clk_disable_unprepare(priv->pclk);
465decbc00eSZhengShunQian }
466decbc00eSZhengShunQian
46766b98906SKrzysztof Kozlowski static const struct of_device_id rk3036_codec_of_match[] __maybe_unused = {
468decbc00eSZhengShunQian { .compatible = "rockchip,rk3036-codec", },
469decbc00eSZhengShunQian {}
470decbc00eSZhengShunQian };
471decbc00eSZhengShunQian MODULE_DEVICE_TABLE(of, rk3036_codec_of_match);
472decbc00eSZhengShunQian
473decbc00eSZhengShunQian static struct platform_driver rk3036_codec_platform_driver = {
474decbc00eSZhengShunQian .driver = {
475decbc00eSZhengShunQian .name = "rk3036-codec-platform",
476decbc00eSZhengShunQian .of_match_table = of_match_ptr(rk3036_codec_of_match),
477decbc00eSZhengShunQian },
478decbc00eSZhengShunQian .probe = rk3036_codec_platform_probe,
479*8756b2ecSUwe Kleine-König .remove_new = rk3036_codec_platform_remove,
480decbc00eSZhengShunQian };
481decbc00eSZhengShunQian
482decbc00eSZhengShunQian module_platform_driver(rk3036_codec_platform_driver);
483decbc00eSZhengShunQian
484decbc00eSZhengShunQian MODULE_AUTHOR("Rockchip Inc.");
485decbc00eSZhengShunQian MODULE_DESCRIPTION("Rockchip rk3036 codec driver");
486decbc00eSZhengShunQian MODULE_LICENSE("GPL");
487