1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98090.c -- MAX98090 ALSA SoC Audio driver 4 * 5 * Copyright 2011-2012 Maxim Integrated Products 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/acpi.h> 17 #include <linux/clk.h> 18 #include <sound/jack.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include <sound/max98090.h> 24 #include "max98090.h" 25 26 /* Allows for sparsely populated register maps */ 27 static const struct reg_default max98090_reg[] = { 28 { 0x00, 0x00 }, /* 00 Software Reset */ 29 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 30 { 0x04, 0x00 }, /* 04 System Clock Quick */ 31 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 32 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 33 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 34 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 35 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 36 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 37 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 38 { 0x0C, 0x00 }, /* 0C Reserved */ 39 { 0x0D, 0x00 }, /* 0D Input Config */ 40 { 0x0E, 0x1B }, /* 0E Line Input Level */ 41 { 0x0F, 0x00 }, /* 0F Line Config */ 42 43 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 44 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 45 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 46 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 47 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 48 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 49 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 50 { 0x17, 0x03 }, /* 17 Left ADC Level */ 51 { 0x18, 0x03 }, /* 18 Right ADC Level */ 52 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 53 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 54 { 0x1B, 0x00 }, /* 1B System Clock */ 55 { 0x1C, 0x00 }, /* 1C Clock Mode */ 56 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 57 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 58 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 59 60 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 61 { 0x21, 0x00 }, /* 21 Master Mode */ 62 { 0x22, 0x00 }, /* 22 Interface Format */ 63 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 64 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 65 { 0x25, 0x00 }, /* 25 I/O Configuration */ 66 { 0x26, 0x80 }, /* 26 Filter Config */ 67 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 68 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 69 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 70 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 71 { 0x2B, 0x00 }, /* 2B HP Control */ 72 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 73 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 74 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 75 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 76 77 { 0x30, 0x00 }, /* 30 Spk Control */ 78 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 79 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 80 { 0x33, 0x00 }, /* 33 ALC Timing */ 81 { 0x34, 0x00 }, /* 34 ALC Compressor */ 82 { 0x35, 0x00 }, /* 35 ALC Expander */ 83 { 0x36, 0x00 }, /* 36 ALC Gain */ 84 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 85 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 86 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 87 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 88 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 89 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 90 { 0x3D, 0x00 }, /* 3D Jack Detect */ 91 { 0x3E, 0x00 }, /* 3E Input Enable */ 92 { 0x3F, 0x00 }, /* 3F Output Enable */ 93 94 { 0x40, 0x00 }, /* 40 Level Control */ 95 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 96 { 0x42, 0x00 }, /* 42 Bias Control */ 97 { 0x43, 0x00 }, /* 43 DAC Control */ 98 { 0x44, 0x06 }, /* 44 ADC Control */ 99 { 0x45, 0x00 }, /* 45 Device Shutdown */ 100 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 101 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 102 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 103 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 104 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 105 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 106 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 107 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 108 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 109 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 110 111 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 112 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 113 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 114 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 115 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 116 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 117 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 118 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 119 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 120 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 121 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 122 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 123 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 124 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 125 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 126 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 127 128 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 129 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 130 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 131 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 132 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 133 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 134 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 135 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 136 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 137 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 138 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 139 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 140 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 141 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 142 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 143 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 144 145 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 146 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 147 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 148 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 149 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 150 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 151 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 152 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 153 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 154 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 155 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 156 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 157 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 158 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 159 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 160 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 161 162 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 163 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 164 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 165 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 166 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 167 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 168 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 169 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 170 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 171 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 172 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 173 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 174 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 175 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 176 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 177 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 178 179 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 180 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 181 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 182 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 183 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 184 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 185 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 186 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 187 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 188 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 189 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 190 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 191 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 192 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 193 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 194 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 195 196 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 197 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 198 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 199 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 200 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 201 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 202 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 203 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 204 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 205 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 206 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 207 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 208 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 209 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 210 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 211 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 212 213 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 214 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 215 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 216 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 217 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 218 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 219 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 220 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 221 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 222 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 223 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 224 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 225 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 226 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 227 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 228 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 229 230 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 231 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 232 { 0xC2, 0x00 }, /* C2 Sample Rate */ 233 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 234 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 235 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 236 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 237 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 238 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 239 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 240 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 241 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 242 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 243 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 244 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 245 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 246 247 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 248 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 249 }; 250 251 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case M98090_REG_SOFTWARE_RESET: 255 case M98090_REG_DEVICE_STATUS: 256 case M98090_REG_JACK_STATUS: 257 case M98090_REG_REVISION_ID: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool max98090_readable_register(struct device *dev, unsigned int reg) 265 { 266 switch (reg) { 267 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: 268 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: 269 case M98090_REG_REVISION_ID: 270 return true; 271 default: 272 return false; 273 } 274 } 275 276 static int max98090_reset(struct max98090_priv *max98090) 277 { 278 int ret; 279 280 /* Reset the codec by writing to this write-only reset register */ 281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 282 M98090_SWRESET_MASK); 283 if (ret < 0) { 284 dev_err(max98090->component->dev, 285 "Failed to reset codec: %d\n", ret); 286 return ret; 287 } 288 289 msleep(20); 290 return ret; 291 } 292 293 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv, 294 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 295 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 296 ); 297 298 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 299 300 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 301 -600, 600, 0); 302 303 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv, 304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 305 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 306 ); 307 308 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 310 311 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 313 314 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 317 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 318 319 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv, 320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0) 322 ); 323 324 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv, 325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 329 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 330 ); 331 332 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv, 333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 337 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0) 338 ); 339 340 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv, 341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 344 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 345 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 346 ); 347 348 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 349 struct snd_ctl_elem_value *ucontrol) 350 { 351 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 352 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 353 struct soc_mixer_control *mc = 354 (struct soc_mixer_control *)kcontrol->private_value; 355 unsigned int mask = (1 << fls(mc->max)) - 1; 356 unsigned int val = snd_soc_component_read(component, mc->reg); 357 unsigned int *select; 358 359 switch (mc->reg) { 360 case M98090_REG_MIC1_INPUT_LEVEL: 361 select = &(max98090->pa1en); 362 break; 363 case M98090_REG_MIC2_INPUT_LEVEL: 364 select = &(max98090->pa2en); 365 break; 366 case M98090_REG_ADC_SIDETONE: 367 select = &(max98090->sidetone); 368 break; 369 default: 370 return -EINVAL; 371 } 372 373 val = (val >> mc->shift) & mask; 374 375 if (val >= 1) { 376 /* If on, return the volume */ 377 val = val - 1; 378 *select = val; 379 } else { 380 /* If off, return last stored value */ 381 val = *select; 382 } 383 384 ucontrol->value.integer.value[0] = val; 385 return 0; 386 } 387 388 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 389 struct snd_ctl_elem_value *ucontrol) 390 { 391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 392 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 393 struct soc_mixer_control *mc = 394 (struct soc_mixer_control *)kcontrol->private_value; 395 unsigned int mask = (1 << fls(mc->max)) - 1; 396 unsigned int sel = ucontrol->value.integer.value[0]; 397 unsigned int val = snd_soc_component_read(component, mc->reg); 398 unsigned int *select; 399 400 switch (mc->reg) { 401 case M98090_REG_MIC1_INPUT_LEVEL: 402 select = &(max98090->pa1en); 403 break; 404 case M98090_REG_MIC2_INPUT_LEVEL: 405 select = &(max98090->pa2en); 406 break; 407 case M98090_REG_ADC_SIDETONE: 408 select = &(max98090->sidetone); 409 break; 410 default: 411 return -EINVAL; 412 } 413 414 val = (val >> mc->shift) & mask; 415 416 if (sel < 0 || sel > mc->max) 417 return -EINVAL; 418 419 *select = sel; 420 421 /* Setting a volume is only valid if it is already On */ 422 if (val >= 1) { 423 sel = sel + 1; 424 } else { 425 /* Write what was already there */ 426 sel = val; 427 } 428 429 snd_soc_component_update_bits(component, mc->reg, 430 mask << mc->shift, 431 sel << mc->shift); 432 433 return *select != val; 434 } 435 436 static const char *max98090_perf_pwr_text[] = 437 { "High Performance", "Low Power" }; 438 static const char *max98090_pwr_perf_text[] = 439 { "Low Power", "High Performance" }; 440 441 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 442 M98090_REG_BIAS_CONTROL, 443 M98090_VCM_MODE_SHIFT, 444 max98090_pwr_perf_text); 445 446 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 447 448 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 449 M98090_REG_ADC_CONTROL, 450 M98090_OSR128_SHIFT, 451 max98090_osr128_text); 452 453 static const char *max98090_mode_text[] = { "Voice", "Music" }; 454 455 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 456 M98090_REG_FILTER_CONFIG, 457 M98090_MODE_SHIFT, 458 max98090_mode_text); 459 460 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 461 M98090_REG_FILTER_CONFIG, 462 M98090_FLT_DMIC34MODE_SHIFT, 463 max98090_mode_text); 464 465 static const char *max98090_drcatk_text[] = 466 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 467 468 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 469 M98090_REG_DRC_TIMING, 470 M98090_DRCATK_SHIFT, 471 max98090_drcatk_text); 472 473 static const char *max98090_drcrls_text[] = 474 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 475 476 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 477 M98090_REG_DRC_TIMING, 478 M98090_DRCRLS_SHIFT, 479 max98090_drcrls_text); 480 481 static const char *max98090_alccmp_text[] = 482 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 483 484 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 485 M98090_REG_DRC_COMPRESSOR, 486 M98090_DRCCMP_SHIFT, 487 max98090_alccmp_text); 488 489 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 490 491 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 492 M98090_REG_DRC_EXPANDER, 493 M98090_DRCEXP_SHIFT, 494 max98090_drcexp_text); 495 496 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 497 M98090_REG_DAC_CONTROL, 498 M98090_PERFMODE_SHIFT, 499 max98090_perf_pwr_text); 500 501 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 502 M98090_REG_DAC_CONTROL, 503 M98090_DACHP_SHIFT, 504 max98090_pwr_perf_text); 505 506 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 507 M98090_REG_ADC_CONTROL, 508 M98090_ADCHP_SHIFT, 509 max98090_pwr_perf_text); 510 511 static const struct snd_kcontrol_new max98090_snd_controls[] = { 512 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 513 514 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 515 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 516 517 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 518 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 519 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 520 max98090_put_enab_tlv, max98090_micboost_tlv), 521 522 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 523 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 524 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 525 max98090_put_enab_tlv, max98090_micboost_tlv), 526 527 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 528 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 529 max98090_mic_tlv), 530 531 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 532 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 533 max98090_mic_tlv), 534 535 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 536 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 537 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 538 539 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 540 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 541 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 542 543 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 544 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 545 max98090_line_tlv), 546 547 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 548 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 549 max98090_line_tlv), 550 551 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 552 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 553 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 554 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 555 556 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 557 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 558 max98090_avg_tlv), 559 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 560 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 561 max98090_avg_tlv), 562 563 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 564 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 565 max98090_av_tlv), 566 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 567 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 568 max98090_av_tlv), 569 570 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 571 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 572 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 573 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 574 575 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 576 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 577 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 578 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 579 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 580 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 581 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 582 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 583 SOC_ENUM("Filter Mode", max98090_mode_enum), 584 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 585 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 586 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 587 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 588 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 589 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 590 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 591 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 592 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 593 max98090_put_enab_tlv, max98090_sdg_tlv), 594 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 595 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 596 max98090_dvg_tlv), 597 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 598 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 599 max98090_dv_tlv), 600 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 601 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 602 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 603 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 604 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 605 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 606 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 607 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 608 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 609 1), 610 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 611 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 612 max98090_dv_tlv), 613 614 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 615 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 616 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 617 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 618 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 619 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 620 max98090_alcmakeup_tlv), 621 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 622 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 623 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 624 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 625 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 626 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 627 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 628 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 629 630 SOC_ENUM("DAC HP Playback Performance Mode", 631 max98090_dac_perfmode_enum), 632 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 633 634 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 635 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 636 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 637 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 638 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 639 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 640 641 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 642 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 643 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 644 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 645 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 646 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 647 648 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 649 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 650 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 651 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 652 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 653 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 654 655 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 656 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 657 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 658 659 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 660 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 661 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 662 0, max98090_spk_tlv), 663 664 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 665 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 666 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 667 668 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 669 M98090_HPLM_SHIFT, 1, 1), 670 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 671 M98090_HPRM_SHIFT, 1, 1), 672 673 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 674 M98090_SPLM_SHIFT, 1, 1), 675 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 676 M98090_SPRM_SHIFT, 1, 1), 677 678 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 679 M98090_RCVLM_SHIFT, 1, 1), 680 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 681 M98090_RCVRM_SHIFT, 1, 1), 682 683 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 684 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 685 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 686 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 687 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 688 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 689 690 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 691 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 692 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 693 }; 694 695 static const struct snd_kcontrol_new max98091_snd_controls[] = { 696 697 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 698 M98090_DMIC34_ZEROPAD_SHIFT, 699 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 700 701 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 702 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 703 M98090_FLT_DMIC34HPF_SHIFT, 704 M98090_FLT_DMIC34HPF_NUM - 1, 0), 705 706 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 707 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 708 max98090_avg_tlv), 709 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 710 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 711 max98090_avg_tlv), 712 713 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 714 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 715 max98090_av_tlv), 716 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 717 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 718 max98090_av_tlv), 719 720 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 721 M98090_REG_DMIC34_BIQUAD_BASE, 15), 722 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 723 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 724 725 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 726 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 727 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 728 }; 729 730 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 731 struct snd_kcontrol *kcontrol, int event) 732 { 733 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 734 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 735 736 unsigned int val = snd_soc_component_read(component, w->reg); 737 738 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 739 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 740 else 741 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 742 743 if (val >= 1) { 744 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 745 max98090->pa1en = val - 1; /* Update for volatile */ 746 } else { 747 max98090->pa2en = val - 1; /* Update for volatile */ 748 } 749 } 750 751 switch (event) { 752 case SND_SOC_DAPM_POST_PMU: 753 /* If turning on, set to most recently selected volume */ 754 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 755 val = max98090->pa1en + 1; 756 else 757 val = max98090->pa2en + 1; 758 break; 759 case SND_SOC_DAPM_POST_PMD: 760 /* If turning off, turn off */ 761 val = 0; 762 break; 763 default: 764 return -EINVAL; 765 } 766 767 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 768 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, 769 val << M98090_MIC_PA1EN_SHIFT); 770 else 771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, 772 val << M98090_MIC_PA2EN_SHIFT); 773 774 return 0; 775 } 776 777 static int max98090_shdn_event(struct snd_soc_dapm_widget *w, 778 struct snd_kcontrol *kcontrol, int event) 779 { 780 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 781 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 782 783 if (event & SND_SOC_DAPM_POST_PMU) 784 max98090->shdn_pending = true; 785 786 return 0; 787 788 } 789 790 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 791 792 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 793 M98090_REG_INPUT_MODE, 794 M98090_EXTMIC1_SHIFT, 795 mic1_mux_text); 796 797 static const struct snd_kcontrol_new max98090_mic1_mux = 798 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 799 800 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 801 802 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 803 M98090_REG_INPUT_MODE, 804 M98090_EXTMIC2_SHIFT, 805 mic2_mux_text); 806 807 static const struct snd_kcontrol_new max98090_mic2_mux = 808 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 809 810 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 811 812 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 813 814 static const struct snd_kcontrol_new max98090_dmic_mux = 815 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 816 817 /* LINEA mixer switch */ 818 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 819 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 820 M98090_IN1SEEN_SHIFT, 1, 0), 821 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 822 M98090_IN3SEEN_SHIFT, 1, 0), 823 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 824 M98090_IN5SEEN_SHIFT, 1, 0), 825 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 826 M98090_IN34DIFF_SHIFT, 1, 0), 827 }; 828 829 /* LINEB mixer switch */ 830 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 831 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 832 M98090_IN2SEEN_SHIFT, 1, 0), 833 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 834 M98090_IN4SEEN_SHIFT, 1, 0), 835 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 836 M98090_IN6SEEN_SHIFT, 1, 0), 837 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 838 M98090_IN56DIFF_SHIFT, 1, 0), 839 }; 840 841 /* Left ADC mixer switch */ 842 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 843 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 844 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 845 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 846 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 847 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 848 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 849 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 850 M98090_MIXADL_LINEA_SHIFT, 1, 0), 851 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 852 M98090_MIXADL_LINEB_SHIFT, 1, 0), 853 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 854 M98090_MIXADL_MIC1_SHIFT, 1, 0), 855 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 856 M98090_MIXADL_MIC2_SHIFT, 1, 0), 857 }; 858 859 /* Right ADC mixer switch */ 860 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 861 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 862 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 863 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 864 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 865 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 866 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 867 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 868 M98090_MIXADR_LINEA_SHIFT, 1, 0), 869 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 870 M98090_MIXADR_LINEB_SHIFT, 1, 0), 871 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 872 M98090_MIXADR_MIC1_SHIFT, 1, 0), 873 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 874 M98090_MIXADR_MIC2_SHIFT, 1, 0), 875 }; 876 877 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 878 879 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 880 M98090_REG_IO_CONFIGURATION, 881 M98090_LTEN_SHIFT, 882 lten_mux_text); 883 884 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 885 M98090_REG_IO_CONFIGURATION, 886 M98090_LTEN_SHIFT, 887 lten_mux_text); 888 889 static const struct snd_kcontrol_new max98090_ltenl_mux = 890 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 891 892 static const struct snd_kcontrol_new max98090_ltenr_mux = 893 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 894 895 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 896 897 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 898 M98090_REG_IO_CONFIGURATION, 899 M98090_LBEN_SHIFT, 900 lben_mux_text); 901 902 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 903 M98090_REG_IO_CONFIGURATION, 904 M98090_LBEN_SHIFT, 905 lben_mux_text); 906 907 static const struct snd_kcontrol_new max98090_lbenl_mux = 908 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 909 910 static const struct snd_kcontrol_new max98090_lbenr_mux = 911 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 912 913 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 914 915 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 916 917 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 918 M98090_REG_ADC_SIDETONE, 919 M98090_DSTSL_SHIFT, 920 stenl_mux_text); 921 922 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 923 M98090_REG_ADC_SIDETONE, 924 M98090_DSTSR_SHIFT, 925 stenr_mux_text); 926 927 static const struct snd_kcontrol_new max98090_stenl_mux = 928 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 929 930 static const struct snd_kcontrol_new max98090_stenr_mux = 931 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 932 933 /* Left speaker mixer switch */ 934 static const struct 935 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 936 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 937 M98090_MIXSPL_DACL_SHIFT, 1, 0), 938 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 939 M98090_MIXSPL_DACR_SHIFT, 1, 0), 940 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 941 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 942 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 943 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 944 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 945 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 946 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 947 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 948 }; 949 950 /* Right speaker mixer switch */ 951 static const struct 952 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 953 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 954 M98090_MIXSPR_DACL_SHIFT, 1, 0), 955 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 956 M98090_MIXSPR_DACR_SHIFT, 1, 0), 957 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 958 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 959 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 960 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 961 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 962 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 963 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 964 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 965 }; 966 967 /* Left headphone mixer switch */ 968 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 969 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 970 M98090_MIXHPL_DACL_SHIFT, 1, 0), 971 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 972 M98090_MIXHPL_DACR_SHIFT, 1, 0), 973 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 974 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 975 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 976 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 977 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 978 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 979 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 980 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 981 }; 982 983 /* Right headphone mixer switch */ 984 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 985 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 986 M98090_MIXHPR_DACL_SHIFT, 1, 0), 987 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 988 M98090_MIXHPR_DACR_SHIFT, 1, 0), 989 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 990 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 991 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 992 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 993 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 994 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 995 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 996 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 997 }; 998 999 /* Left receiver mixer switch */ 1000 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1001 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1002 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1003 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1004 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1005 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1006 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1007 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1008 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1009 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1010 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1011 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1012 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1013 }; 1014 1015 /* Right receiver mixer switch */ 1016 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1017 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1018 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1019 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1020 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1021 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1022 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1023 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1024 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1025 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1026 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1027 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1028 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1029 }; 1030 1031 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1032 1033 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1034 M98090_REG_LOUTR_MIXER, 1035 M98090_LINMOD_SHIFT, 1036 linmod_mux_text); 1037 1038 static const struct snd_kcontrol_new max98090_linmod_mux = 1039 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1040 1041 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1042 1043 /* 1044 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1045 */ 1046 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1047 M98090_REG_HP_CONTROL, 1048 M98090_MIXHPLSEL_SHIFT, 1049 mixhpsel_mux_text); 1050 1051 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1052 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1053 1054 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1055 M98090_REG_HP_CONTROL, 1056 M98090_MIXHPRSEL_SHIFT, 1057 mixhpsel_mux_text); 1058 1059 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1060 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1061 1062 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1063 SND_SOC_DAPM_INPUT("MIC1"), 1064 SND_SOC_DAPM_INPUT("MIC2"), 1065 SND_SOC_DAPM_INPUT("DMICL"), 1066 SND_SOC_DAPM_INPUT("DMICR"), 1067 SND_SOC_DAPM_INPUT("IN1"), 1068 SND_SOC_DAPM_INPUT("IN2"), 1069 SND_SOC_DAPM_INPUT("IN3"), 1070 SND_SOC_DAPM_INPUT("IN4"), 1071 SND_SOC_DAPM_INPUT("IN5"), 1072 SND_SOC_DAPM_INPUT("IN6"), 1073 SND_SOC_DAPM_INPUT("IN12"), 1074 SND_SOC_DAPM_INPUT("IN34"), 1075 SND_SOC_DAPM_INPUT("IN56"), 1076 1077 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1078 M98090_MBEN_SHIFT, 0, NULL, 0), 1079 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1080 M98090_SHDNN_SHIFT, 0, NULL, 0), 1081 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1082 M98090_SDIEN_SHIFT, 0, NULL, 0), 1083 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1084 M98090_SDOEN_SHIFT, 0, NULL, 0), 1085 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1086 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event, 1087 SND_SOC_DAPM_POST_PMU), 1088 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1089 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event, 1090 SND_SOC_DAPM_POST_PMU), 1091 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1092 M98090_AHPF_SHIFT, 0, NULL, 0), 1093 1094 /* 1095 * Note: Sysclk and misc power supplies are taken care of by SHDN 1096 */ 1097 1098 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1099 0, 0, &max98090_mic1_mux), 1100 1101 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1102 0, 0, &max98090_mic2_mux), 1103 1104 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1105 1106 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1107 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1108 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1109 1110 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1111 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1113 1114 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1115 &max98090_linea_mixer_controls[0], 1116 ARRAY_SIZE(max98090_linea_mixer_controls)), 1117 1118 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1119 &max98090_lineb_mixer_controls[0], 1120 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1121 1122 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1123 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1124 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1125 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1126 1127 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1128 &max98090_left_adc_mixer_controls[0], 1129 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1130 1131 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1132 &max98090_right_adc_mixer_controls[0], 1133 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1134 1135 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1136 M98090_ADLEN_SHIFT, 0, max98090_shdn_event, 1137 SND_SOC_DAPM_POST_PMU), 1138 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1139 M98090_ADREN_SHIFT, 0, max98090_shdn_event, 1140 SND_SOC_DAPM_POST_PMU), 1141 1142 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1143 SND_SOC_NOPM, 0, 0), 1144 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1145 SND_SOC_NOPM, 0, 0), 1146 1147 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1148 0, 0, &max98090_lbenl_mux), 1149 1150 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1151 0, 0, &max98090_lbenr_mux), 1152 1153 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1154 0, 0, &max98090_ltenl_mux), 1155 1156 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1157 0, 0, &max98090_ltenr_mux), 1158 1159 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1160 0, 0, &max98090_stenl_mux), 1161 1162 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1163 0, 0, &max98090_stenr_mux), 1164 1165 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1166 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1167 1168 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1169 M98090_DALEN_SHIFT, 0), 1170 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1171 M98090_DAREN_SHIFT, 0), 1172 1173 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1174 &max98090_left_hp_mixer_controls[0], 1175 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1176 1177 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1178 &max98090_right_hp_mixer_controls[0], 1179 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1180 1181 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1182 &max98090_left_speaker_mixer_controls[0], 1183 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1184 1185 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1186 &max98090_right_speaker_mixer_controls[0], 1187 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1188 1189 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1190 &max98090_left_rcv_mixer_controls[0], 1191 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1192 1193 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1194 &max98090_right_rcv_mixer_controls[0], 1195 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1196 1197 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0, 1198 &max98090_linmod_mux), 1199 1200 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0, 1201 &max98090_mixhplsel_mux), 1202 1203 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, 1204 &max98090_mixhprsel_mux), 1205 1206 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1207 M98090_HPLEN_SHIFT, 0, NULL, 0), 1208 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1209 M98090_HPREN_SHIFT, 0, NULL, 0), 1210 1211 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1212 M98090_SPLEN_SHIFT, 0, NULL, 0), 1213 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1214 M98090_SPREN_SHIFT, 0, NULL, 0), 1215 1216 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1217 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1218 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1219 M98090_RCVREN_SHIFT, 0, NULL, 0), 1220 1221 SND_SOC_DAPM_OUTPUT("HPL"), 1222 SND_SOC_DAPM_OUTPUT("HPR"), 1223 SND_SOC_DAPM_OUTPUT("SPKL"), 1224 SND_SOC_DAPM_OUTPUT("SPKR"), 1225 SND_SOC_DAPM_OUTPUT("RCVL"), 1226 SND_SOC_DAPM_OUTPUT("RCVR"), 1227 }; 1228 1229 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1230 SND_SOC_DAPM_INPUT("DMIC3"), 1231 SND_SOC_DAPM_INPUT("DMIC4"), 1232 1233 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1234 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1235 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1236 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1237 }; 1238 1239 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1240 {"MIC1 Input", NULL, "MIC1"}, 1241 {"MIC2 Input", NULL, "MIC2"}, 1242 1243 {"DMICL", NULL, "DMICL_ENA"}, 1244 {"DMICL", NULL, "DMICR_ENA"}, 1245 {"DMICR", NULL, "DMICL_ENA"}, 1246 {"DMICR", NULL, "DMICR_ENA"}, 1247 {"DMICL", NULL, "AHPF"}, 1248 {"DMICR", NULL, "AHPF"}, 1249 1250 /* MIC1 input mux */ 1251 {"MIC1 Mux", "IN12", "IN12"}, 1252 {"MIC1 Mux", "IN56", "IN56"}, 1253 1254 /* MIC2 input mux */ 1255 {"MIC2 Mux", "IN34", "IN34"}, 1256 {"MIC2 Mux", "IN56", "IN56"}, 1257 1258 {"MIC1 Input", NULL, "MIC1 Mux"}, 1259 {"MIC2 Input", NULL, "MIC2 Mux"}, 1260 1261 /* Left ADC input mixer */ 1262 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1263 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1264 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1265 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1266 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1267 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1268 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1269 1270 /* Right ADC input mixer */ 1271 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1272 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1273 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1274 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1275 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1276 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1277 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1278 1279 /* Line A input mixer */ 1280 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1281 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1282 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1283 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1284 1285 /* Line B input mixer */ 1286 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1287 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1288 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1289 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1290 1291 {"LINEA Input", NULL, "LINEA Mixer"}, 1292 {"LINEB Input", NULL, "LINEB Mixer"}, 1293 1294 /* Inputs */ 1295 {"ADCL", NULL, "Left ADC Mixer"}, 1296 {"ADCR", NULL, "Right ADC Mixer"}, 1297 {"ADCL", NULL, "SHDN"}, 1298 {"ADCR", NULL, "SHDN"}, 1299 1300 {"DMIC Mux", "ADC", "ADCL"}, 1301 {"DMIC Mux", "ADC", "ADCR"}, 1302 {"DMIC Mux", "DMIC", "DMICL"}, 1303 {"DMIC Mux", "DMIC", "DMICR"}, 1304 1305 {"LBENL Mux", "Normal", "DMIC Mux"}, 1306 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1307 {"LBENR Mux", "Normal", "DMIC Mux"}, 1308 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1309 1310 {"AIFOUTL", NULL, "LBENL Mux"}, 1311 {"AIFOUTR", NULL, "LBENR Mux"}, 1312 {"AIFOUTL", NULL, "SHDN"}, 1313 {"AIFOUTR", NULL, "SHDN"}, 1314 {"AIFOUTL", NULL, "SDOEN"}, 1315 {"AIFOUTR", NULL, "SDOEN"}, 1316 1317 {"LTENL Mux", "Normal", "AIFINL"}, 1318 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1319 {"LTENR Mux", "Normal", "AIFINR"}, 1320 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1321 1322 {"DACL", NULL, "LTENL Mux"}, 1323 {"DACR", NULL, "LTENR Mux"}, 1324 1325 {"STENL Mux", "Sidetone Left", "ADCL"}, 1326 {"STENL Mux", "Sidetone Left", "DMICL"}, 1327 {"STENR Mux", "Sidetone Right", "ADCR"}, 1328 {"STENR Mux", "Sidetone Right", "DMICR"}, 1329 {"DACL", NULL, "STENL Mux"}, 1330 {"DACR", NULL, "STENR Mux"}, 1331 1332 {"AIFINL", NULL, "SHDN"}, 1333 {"AIFINR", NULL, "SHDN"}, 1334 {"AIFINL", NULL, "SDIEN"}, 1335 {"AIFINR", NULL, "SDIEN"}, 1336 {"DACL", NULL, "SHDN"}, 1337 {"DACR", NULL, "SHDN"}, 1338 1339 /* Left headphone output mixer */ 1340 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1341 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1342 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1343 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1344 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1345 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1346 1347 /* Right headphone output mixer */ 1348 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1349 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1350 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1351 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1352 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1353 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1354 1355 /* Left speaker output mixer */ 1356 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1357 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1358 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1359 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1360 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1361 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1362 1363 /* Right speaker output mixer */ 1364 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1365 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1366 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1367 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1368 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1369 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1370 1371 /* Left Receiver output mixer */ 1372 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1373 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1374 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1375 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1376 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1377 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1378 1379 /* Right Receiver output mixer */ 1380 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1381 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1382 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1383 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1384 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1385 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1386 1387 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1388 1389 /* 1390 * Disable this for lowest power if bypassing 1391 * the DAC with an analog signal 1392 */ 1393 {"HP Left Out", NULL, "DACL"}, 1394 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1395 1396 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1397 1398 /* 1399 * Disable this for lowest power if bypassing 1400 * the DAC with an analog signal 1401 */ 1402 {"HP Right Out", NULL, "DACR"}, 1403 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1404 1405 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1406 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1407 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1408 1409 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1410 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1411 {"RCV Right Out", NULL, "LINMOD Mux"}, 1412 1413 {"HPL", NULL, "HP Left Out"}, 1414 {"HPR", NULL, "HP Right Out"}, 1415 {"SPKL", NULL, "SPK Left Out"}, 1416 {"SPKR", NULL, "SPK Right Out"}, 1417 {"RCVL", NULL, "RCV Left Out"}, 1418 {"RCVR", NULL, "RCV Right Out"}, 1419 }; 1420 1421 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1422 /* DMIC inputs */ 1423 {"DMIC3", NULL, "DMIC3_ENA"}, 1424 {"DMIC4", NULL, "DMIC4_ENA"}, 1425 {"DMIC3", NULL, "AHPF"}, 1426 {"DMIC4", NULL, "AHPF"}, 1427 }; 1428 1429 static int max98090_add_widgets(struct snd_soc_component *component) 1430 { 1431 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1432 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1433 1434 snd_soc_add_component_controls(component, max98090_snd_controls, 1435 ARRAY_SIZE(max98090_snd_controls)); 1436 1437 if (max98090->devtype == MAX98091) { 1438 snd_soc_add_component_controls(component, max98091_snd_controls, 1439 ARRAY_SIZE(max98091_snd_controls)); 1440 } 1441 1442 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1443 ARRAY_SIZE(max98090_dapm_widgets)); 1444 1445 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1446 ARRAY_SIZE(max98090_dapm_routes)); 1447 1448 if (max98090->devtype == MAX98091) { 1449 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1450 ARRAY_SIZE(max98091_dapm_widgets)); 1451 1452 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1453 ARRAY_SIZE(max98091_dapm_routes)); 1454 } 1455 1456 return 0; 1457 } 1458 1459 static const int pclk_rates[] = { 1460 12000000, 12000000, 13000000, 13000000, 1461 16000000, 16000000, 19200000, 19200000 1462 }; 1463 1464 static const int lrclk_rates[] = { 1465 8000, 16000, 8000, 16000, 1466 8000, 16000, 8000, 16000 1467 }; 1468 1469 static const int user_pclk_rates[] = { 1470 13000000, 13000000, 19200000, 19200000, 1471 }; 1472 1473 static const int user_lrclk_rates[] = { 1474 44100, 48000, 44100, 48000, 1475 }; 1476 1477 static const unsigned long long ni_value[] = { 1478 3528, 768, 441, 8 1479 }; 1480 1481 static const unsigned long long mi_value[] = { 1482 8125, 1625, 1500, 25 1483 }; 1484 1485 static void max98090_configure_bclk(struct snd_soc_component *component) 1486 { 1487 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1488 unsigned long long ni; 1489 int i; 1490 1491 if (!max98090->sysclk) { 1492 dev_err(component->dev, "No SYSCLK configured\n"); 1493 return; 1494 } 1495 1496 if (!max98090->bclk || !max98090->lrclk) { 1497 dev_err(component->dev, "No audio clocks configured\n"); 1498 return; 1499 } 1500 1501 /* Skip configuration when operating as slave */ 1502 if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) & 1503 M98090_MAS_MASK)) { 1504 return; 1505 } 1506 1507 /* Check for supported PCLK to LRCLK ratios */ 1508 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1509 if ((pclk_rates[i] == max98090->sysclk) && 1510 (lrclk_rates[i] == max98090->lrclk)) { 1511 dev_dbg(component->dev, 1512 "Found supported PCLK to LRCLK rates 0x%x\n", 1513 i + 0x8); 1514 1515 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1516 M98090_FREQ_MASK, 1517 (i + 0x8) << M98090_FREQ_SHIFT); 1518 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1519 M98090_USE_M1_MASK, 0); 1520 return; 1521 } 1522 } 1523 1524 /* Check for user calculated MI and NI ratios */ 1525 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1526 if ((user_pclk_rates[i] == max98090->sysclk) && 1527 (user_lrclk_rates[i] == max98090->lrclk)) { 1528 dev_dbg(component->dev, 1529 "Found user supported PCLK to LRCLK rates\n"); 1530 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", 1531 i, ni_value[i], mi_value[i]); 1532 1533 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1534 M98090_FREQ_MASK, 0); 1535 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1536 M98090_USE_M1_MASK, 1537 1 << M98090_USE_M1_SHIFT); 1538 1539 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1540 (ni_value[i] >> 8) & 0x7F); 1541 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, 1542 ni_value[i] & 0xFF); 1543 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB, 1544 (mi_value[i] >> 8) & 0x7F); 1545 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB, 1546 mi_value[i] & 0xFF); 1547 1548 return; 1549 } 1550 } 1551 1552 /* 1553 * Calculate based on MI = 65536 (not as good as either method above) 1554 */ 1555 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1556 M98090_FREQ_MASK, 0); 1557 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1558 M98090_USE_M1_MASK, 0); 1559 1560 /* 1561 * Configure NI when operating as master 1562 * Note: There is a small, but significant audio quality improvement 1563 * by calculating ni and mi. 1564 */ 1565 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1566 * (unsigned long long int)max98090->lrclk; 1567 do_div(ni, (unsigned long long int)max98090->sysclk); 1568 dev_info(component->dev, "No better method found\n"); 1569 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); 1570 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1571 (ni >> 8) & 0x7F); 1572 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1573 } 1574 1575 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1576 unsigned int fmt) 1577 { 1578 struct snd_soc_component *component = codec_dai->component; 1579 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1580 struct max98090_cdata *cdata; 1581 u8 regval; 1582 1583 max98090->dai_fmt = fmt; 1584 cdata = &max98090->dai[0]; 1585 1586 if (fmt != cdata->fmt) { 1587 cdata->fmt = fmt; 1588 1589 regval = 0; 1590 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1591 case SND_SOC_DAIFMT_CBS_CFS: 1592 /* Set to slave mode PLL - MAS mode off */ 1593 snd_soc_component_write(component, 1594 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1595 snd_soc_component_write(component, 1596 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1597 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1598 M98090_USE_M1_MASK, 0); 1599 max98090->master = false; 1600 break; 1601 case SND_SOC_DAIFMT_CBM_CFM: 1602 /* Set to master mode */ 1603 if (max98090->tdm_slots == 4) { 1604 /* TDM */ 1605 regval |= M98090_MAS_MASK | 1606 M98090_BSEL_64; 1607 } else if (max98090->tdm_slots == 3) { 1608 /* TDM */ 1609 regval |= M98090_MAS_MASK | 1610 M98090_BSEL_48; 1611 } else { 1612 /* Few TDM slots, or No TDM */ 1613 regval |= M98090_MAS_MASK | 1614 M98090_BSEL_32; 1615 } 1616 max98090->master = true; 1617 break; 1618 case SND_SOC_DAIFMT_CBS_CFM: 1619 case SND_SOC_DAIFMT_CBM_CFS: 1620 default: 1621 dev_err(component->dev, "DAI clock mode unsupported"); 1622 return -EINVAL; 1623 } 1624 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); 1625 1626 regval = 0; 1627 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1628 case SND_SOC_DAIFMT_I2S: 1629 regval |= M98090_DLY_MASK; 1630 break; 1631 case SND_SOC_DAIFMT_LEFT_J: 1632 break; 1633 case SND_SOC_DAIFMT_RIGHT_J: 1634 regval |= M98090_RJ_MASK; 1635 break; 1636 case SND_SOC_DAIFMT_DSP_A: 1637 /* Not supported mode */ 1638 default: 1639 dev_err(component->dev, "DAI format unsupported"); 1640 return -EINVAL; 1641 } 1642 1643 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1644 case SND_SOC_DAIFMT_NB_NF: 1645 break; 1646 case SND_SOC_DAIFMT_NB_IF: 1647 regval |= M98090_WCI_MASK; 1648 break; 1649 case SND_SOC_DAIFMT_IB_NF: 1650 regval |= M98090_BCI_MASK; 1651 break; 1652 case SND_SOC_DAIFMT_IB_IF: 1653 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1654 break; 1655 default: 1656 dev_err(component->dev, "DAI invert mode unsupported"); 1657 return -EINVAL; 1658 } 1659 1660 /* 1661 * This accommodates an inverted logic in the MAX98090 chip 1662 * for Bit Clock Invert (BCI). The inverted logic is only 1663 * seen for the case of TDM mode. The remaining cases have 1664 * normal logic. 1665 */ 1666 if (max98090->tdm_slots > 1) 1667 regval ^= M98090_BCI_MASK; 1668 1669 snd_soc_component_write(component, 1670 M98090_REG_INTERFACE_FORMAT, regval); 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1677 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1678 { 1679 struct snd_soc_component *component = codec_dai->component; 1680 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1681 struct max98090_cdata *cdata; 1682 cdata = &max98090->dai[0]; 1683 1684 if (slots < 0 || slots > 4) 1685 return -EINVAL; 1686 1687 max98090->tdm_slots = slots; 1688 max98090->tdm_width = slot_width; 1689 1690 if (max98090->tdm_slots > 1) { 1691 /* SLOTL SLOTR SLOTDLY */ 1692 snd_soc_component_write(component, M98090_REG_TDM_FORMAT, 1693 0 << M98090_TDM_SLOTL_SHIFT | 1694 1 << M98090_TDM_SLOTR_SHIFT | 1695 0 << M98090_TDM_SLOTDLY_SHIFT); 1696 1697 /* FSW TDM */ 1698 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL, 1699 M98090_TDM_MASK, 1700 M98090_TDM_MASK); 1701 } 1702 1703 /* 1704 * Normally advisable to set TDM first, but this permits either order 1705 */ 1706 cdata->fmt = 0; 1707 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1708 1709 return 0; 1710 } 1711 1712 static int max98090_set_bias_level(struct snd_soc_component *component, 1713 enum snd_soc_bias_level level) 1714 { 1715 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1716 int ret; 1717 1718 switch (level) { 1719 case SND_SOC_BIAS_ON: 1720 break; 1721 1722 case SND_SOC_BIAS_PREPARE: 1723 /* 1724 * SND_SOC_BIAS_PREPARE is called while preparing for a 1725 * transition to ON or away from ON. If current bias_level 1726 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1727 * away from ON. Disable the clock in that case, otherwise 1728 * enable it. 1729 */ 1730 if (IS_ERR(max98090->mclk)) 1731 break; 1732 1733 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { 1734 clk_disable_unprepare(max98090->mclk); 1735 } else { 1736 ret = clk_prepare_enable(max98090->mclk); 1737 if (ret) 1738 return ret; 1739 } 1740 break; 1741 1742 case SND_SOC_BIAS_STANDBY: 1743 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1744 ret = regcache_sync(max98090->regmap); 1745 if (ret != 0) { 1746 dev_err(component->dev, 1747 "Failed to sync cache: %d\n", ret); 1748 return ret; 1749 } 1750 } 1751 break; 1752 1753 case SND_SOC_BIAS_OFF: 1754 /* Set internal pull-up to lowest power mode */ 1755 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 1756 M98090_JDWK_MASK, M98090_JDWK_MASK); 1757 regcache_mark_dirty(max98090->regmap); 1758 break; 1759 } 1760 return 0; 1761 } 1762 1763 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 }; 1764 1765 static const int comp_lrclk_rates[] = { 1766 8000, 16000, 32000, 44100, 48000, 96000 1767 }; 1768 1769 struct dmic_table { 1770 int pclk; 1771 struct { 1772 int freq; 1773 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */ 1774 } settings[6]; /* One for each dmic divisor. */ 1775 }; 1776 1777 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */ 1778 { 1779 .pclk = 11289600, 1780 .settings = { 1781 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1782 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1783 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1784 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1785 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1786 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1787 }, 1788 }, 1789 { 1790 .pclk = 12000000, 1791 .settings = { 1792 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1793 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1794 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1795 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1796 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1797 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1798 } 1799 }, 1800 { 1801 .pclk = 12288000, 1802 .settings = { 1803 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1804 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1805 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1806 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1807 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1808 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1809 } 1810 }, 1811 { 1812 .pclk = 13000000, 1813 .settings = { 1814 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } }, 1815 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } }, 1816 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1817 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } }, 1818 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1819 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1820 } 1821 }, 1822 { 1823 .pclk = 19200000, 1824 .settings = { 1825 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } }, 1826 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } }, 1827 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1828 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } }, 1829 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } }, 1830 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1831 } 1832 }, 1833 }; 1834 1835 static int max98090_find_divisor(int target_freq, int pclk) 1836 { 1837 int current_diff = INT_MAX; 1838 int test_diff; 1839 int divisor_index = 0; 1840 int i; 1841 1842 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) { 1843 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); 1844 if (test_diff < current_diff) { 1845 current_diff = test_diff; 1846 divisor_index = i; 1847 } 1848 } 1849 1850 return divisor_index; 1851 } 1852 1853 static int max98090_find_closest_pclk(int pclk) 1854 { 1855 int m1; 1856 int m2; 1857 int i; 1858 1859 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) { 1860 if (pclk == dmic_table[i].pclk) 1861 return i; 1862 if (pclk < dmic_table[i].pclk) { 1863 if (i == 0) 1864 return i; 1865 m1 = pclk - dmic_table[i-1].pclk; 1866 m2 = dmic_table[i].pclk - pclk; 1867 if (m1 < m2) 1868 return i - 1; 1869 else 1870 return i; 1871 } 1872 } 1873 1874 return -EINVAL; 1875 } 1876 1877 static int max98090_configure_dmic(struct max98090_priv *max98090, 1878 int target_dmic_clk, int pclk, int fs) 1879 { 1880 int micclk_index; 1881 int pclk_index; 1882 int dmic_freq; 1883 int dmic_comp; 1884 int i; 1885 1886 pclk_index = max98090_find_closest_pclk(pclk); 1887 if (pclk_index < 0) 1888 return pclk_index; 1889 1890 micclk_index = max98090_find_divisor(target_dmic_clk, pclk); 1891 1892 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1893 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2) 1894 break; 1895 } 1896 1897 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; 1898 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; 1899 1900 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, 1901 M98090_MICCLK_MASK, 1902 micclk_index << M98090_MICCLK_SHIFT); 1903 1904 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, 1905 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, 1906 dmic_comp << M98090_DMIC_COMP_SHIFT | 1907 dmic_freq << M98090_DMIC_FREQ_SHIFT); 1908 1909 return 0; 1910 } 1911 1912 static int max98090_dai_startup(struct snd_pcm_substream *substream, 1913 struct snd_soc_dai *dai) 1914 { 1915 struct snd_soc_component *component = dai->component; 1916 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1917 unsigned int fmt = max98090->dai_fmt; 1918 1919 /* Remove 24-bit format support if it is not in right justified mode. */ 1920 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) { 1921 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; 1922 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); 1923 } 1924 return 0; 1925 } 1926 1927 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1928 struct snd_pcm_hw_params *params, 1929 struct snd_soc_dai *dai) 1930 { 1931 struct snd_soc_component *component = dai->component; 1932 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1933 struct max98090_cdata *cdata; 1934 1935 cdata = &max98090->dai[0]; 1936 max98090->bclk = snd_soc_params_to_bclk(params); 1937 if (params_channels(params) == 1) 1938 max98090->bclk *= 2; 1939 1940 max98090->lrclk = params_rate(params); 1941 1942 switch (params_width(params)) { 1943 case 16: 1944 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, 1945 M98090_WS_MASK, 0); 1946 break; 1947 default: 1948 return -EINVAL; 1949 } 1950 1951 if (max98090->master) 1952 max98090_configure_bclk(component); 1953 1954 cdata->rate = max98090->lrclk; 1955 1956 /* Update filter mode */ 1957 if (max98090->lrclk < 24000) 1958 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1959 M98090_MODE_MASK, 0); 1960 else 1961 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1962 M98090_MODE_MASK, M98090_MODE_MASK); 1963 1964 /* Update sample rate mode */ 1965 if (max98090->lrclk < 50000) 1966 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1967 M98090_DHF_MASK, 0); 1968 else 1969 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1970 M98090_DHF_MASK, M98090_DHF_MASK); 1971 1972 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, 1973 max98090->lrclk); 1974 1975 return 0; 1976 } 1977 1978 /* 1979 * PLL / Sysclk 1980 */ 1981 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1982 int clk_id, unsigned int freq, int dir) 1983 { 1984 struct snd_soc_component *component = dai->component; 1985 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1986 1987 /* Requested clock frequency is already setup */ 1988 if (freq == max98090->sysclk) 1989 return 0; 1990 1991 if (!IS_ERR(max98090->mclk)) { 1992 freq = clk_round_rate(max98090->mclk, freq); 1993 clk_set_rate(max98090->mclk, freq); 1994 } 1995 1996 /* Setup clocks for slave mode, and using the PLL 1997 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1998 * 0x02 (when master clk is 20MHz to 40MHz).. 1999 * 0x03 (when master clk is 40MHz to 60MHz).. 2000 */ 2001 if ((freq >= 10000000) && (freq <= 20000000)) { 2002 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2003 M98090_PSCLK_DIV1); 2004 max98090->pclk = freq; 2005 } else if ((freq > 20000000) && (freq <= 40000000)) { 2006 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2007 M98090_PSCLK_DIV2); 2008 max98090->pclk = freq >> 1; 2009 } else if ((freq > 40000000) && (freq <= 60000000)) { 2010 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2011 M98090_PSCLK_DIV4); 2012 max98090->pclk = freq >> 2; 2013 } else { 2014 dev_err(component->dev, "Invalid master clock frequency\n"); 2015 return -EINVAL; 2016 } 2017 2018 max98090->sysclk = freq; 2019 2020 return 0; 2021 } 2022 2023 static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute, 2024 int direction) 2025 { 2026 struct snd_soc_component *component = codec_dai->component; 2027 int regval; 2028 2029 regval = mute ? M98090_DVM_MASK : 0; 2030 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL, 2031 M98090_DVM_MASK, regval); 2032 2033 return 0; 2034 } 2035 2036 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, 2037 struct snd_soc_dai *dai) 2038 { 2039 struct snd_soc_component *component = dai->component; 2040 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2041 2042 switch (cmd) { 2043 case SNDRV_PCM_TRIGGER_START: 2044 case SNDRV_PCM_TRIGGER_RESUME: 2045 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2046 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2047 queue_delayed_work(system_power_efficient_wq, 2048 &max98090->pll_det_enable_work, 2049 msecs_to_jiffies(10)); 2050 break; 2051 case SNDRV_PCM_TRIGGER_STOP: 2052 case SNDRV_PCM_TRIGGER_SUSPEND: 2053 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2054 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2055 schedule_work(&max98090->pll_det_disable_work); 2056 break; 2057 default: 2058 break; 2059 } 2060 2061 return 0; 2062 } 2063 2064 static void max98090_pll_det_enable_work(struct work_struct *work) 2065 { 2066 struct max98090_priv *max98090 = 2067 container_of(work, struct max98090_priv, 2068 pll_det_enable_work.work); 2069 struct snd_soc_component *component = max98090->component; 2070 unsigned int status, mask; 2071 2072 /* 2073 * Clear status register in order to clear possibly already occurred 2074 * PLL unlock. If PLL hasn't still locked, the status will be set 2075 * again and PLL unlock interrupt will occur. 2076 * Note this will clear all status bits 2077 */ 2078 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2079 2080 /* 2081 * Queue jack work in case jack state has just changed but handler 2082 * hasn't run yet 2083 */ 2084 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2085 status &= mask; 2086 if (status & M98090_JDET_MASK) 2087 queue_delayed_work(system_power_efficient_wq, 2088 &max98090->jack_work, 2089 msecs_to_jiffies(100)); 2090 2091 /* Enable PLL unlock interrupt */ 2092 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2093 M98090_IULK_MASK, 2094 1 << M98090_IULK_SHIFT); 2095 } 2096 2097 static void max98090_pll_det_disable_work(struct work_struct *work) 2098 { 2099 struct max98090_priv *max98090 = 2100 container_of(work, struct max98090_priv, pll_det_disable_work); 2101 struct snd_soc_component *component = max98090->component; 2102 2103 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2104 2105 /* Disable PLL unlock interrupt */ 2106 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2107 M98090_IULK_MASK, 0); 2108 } 2109 2110 static void max98090_pll_work(struct max98090_priv *max98090) 2111 { 2112 struct snd_soc_component *component = max98090->component; 2113 unsigned int pll; 2114 int i; 2115 2116 if (!snd_soc_component_active(component)) 2117 return; 2118 2119 dev_info_ratelimited(component->dev, "PLL unlocked\n"); 2120 2121 /* 2122 * As the datasheet suggested, the maximum PLL lock time should be 2123 * 7 msec. The workaround resets the codec softly by toggling SHDN 2124 * off and on if PLL failed to lock for 10 msec. Notably, there is 2125 * no suggested hold time for SHDN off. 2126 */ 2127 2128 /* Toggle shutdown OFF then ON */ 2129 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2130 M98090_SHDNN_MASK, 0); 2131 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2132 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2133 2134 for (i = 0; i < 10; ++i) { 2135 /* Give PLL time to lock */ 2136 usleep_range(1000, 1200); 2137 2138 /* Check lock status */ 2139 pll = snd_soc_component_read( 2140 component, M98090_REG_DEVICE_STATUS); 2141 if (!(pll & M98090_ULK_MASK)) 2142 break; 2143 } 2144 } 2145 2146 static void max98090_jack_work(struct work_struct *work) 2147 { 2148 struct max98090_priv *max98090 = container_of(work, 2149 struct max98090_priv, 2150 jack_work.work); 2151 struct snd_soc_component *component = max98090->component; 2152 int status = 0; 2153 int reg; 2154 2155 /* Read a second time */ 2156 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 2157 2158 /* Strong pull up allows mic detection */ 2159 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2160 M98090_JDWK_MASK, 0); 2161 2162 msleep(50); 2163 2164 snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2165 2166 /* Weak pull up allows only insertion detection */ 2167 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2168 M98090_JDWK_MASK, M98090_JDWK_MASK); 2169 } 2170 2171 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2172 2173 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 2174 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2175 dev_dbg(component->dev, "No Headset Detected\n"); 2176 2177 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2178 2179 status |= 0; 2180 2181 break; 2182 2183 case 0: 2184 if (max98090->jack_state == 2185 M98090_JACK_STATE_HEADSET) { 2186 2187 dev_dbg(component->dev, 2188 "Headset Button Down Detected\n"); 2189 2190 /* 2191 * max98090_headset_button_event(codec) 2192 * could be defined, then called here. 2193 */ 2194 2195 status |= SND_JACK_HEADSET; 2196 status |= SND_JACK_BTN_0; 2197 2198 break; 2199 } 2200 2201 /* Line is reported as Headphone */ 2202 /* Nokia Headset is reported as Headphone */ 2203 /* Mono Headphone is reported as Headphone */ 2204 dev_dbg(component->dev, "Headphone Detected\n"); 2205 2206 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2207 2208 status |= SND_JACK_HEADPHONE; 2209 2210 break; 2211 2212 case M98090_JKSNS_MASK: 2213 dev_dbg(component->dev, "Headset Detected\n"); 2214 2215 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2216 2217 status |= SND_JACK_HEADSET; 2218 2219 break; 2220 2221 default: 2222 dev_dbg(component->dev, "Unrecognized Jack Status\n"); 2223 break; 2224 } 2225 2226 snd_soc_jack_report(max98090->jack, status, 2227 SND_JACK_HEADSET | SND_JACK_BTN_0); 2228 } 2229 2230 static irqreturn_t max98090_interrupt(int irq, void *data) 2231 { 2232 struct max98090_priv *max98090 = data; 2233 struct snd_soc_component *component = max98090->component; 2234 int ret; 2235 unsigned int mask; 2236 unsigned int active; 2237 2238 /* Treat interrupt before codec is initialized as spurious */ 2239 if (component == NULL) 2240 return IRQ_NONE; 2241 2242 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); 2243 2244 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2245 2246 if (ret != 0) { 2247 dev_err(component->dev, 2248 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2249 ret); 2250 return IRQ_NONE; 2251 } 2252 2253 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2254 2255 if (ret != 0) { 2256 dev_err(component->dev, 2257 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2258 ret); 2259 return IRQ_NONE; 2260 } 2261 2262 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2263 active, mask, active & mask); 2264 2265 active &= mask; 2266 2267 if (!active) 2268 return IRQ_NONE; 2269 2270 if (active & M98090_CLD_MASK) 2271 dev_err(component->dev, "M98090_CLD_MASK\n"); 2272 2273 if (active & M98090_SLD_MASK) 2274 dev_dbg(component->dev, "M98090_SLD_MASK\n"); 2275 2276 if (active & M98090_ULK_MASK) { 2277 dev_dbg(component->dev, "M98090_ULK_MASK\n"); 2278 max98090_pll_work(max98090); 2279 } 2280 2281 if (active & M98090_JDET_MASK) { 2282 dev_dbg(component->dev, "M98090_JDET_MASK\n"); 2283 2284 pm_wakeup_event(component->dev, 100); 2285 2286 queue_delayed_work(system_power_efficient_wq, 2287 &max98090->jack_work, 2288 msecs_to_jiffies(100)); 2289 } 2290 2291 if (active & M98090_DRCACT_MASK) 2292 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); 2293 2294 if (active & M98090_DRCCLP_MASK) 2295 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); 2296 2297 return IRQ_HANDLED; 2298 } 2299 2300 /** 2301 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2302 * 2303 * @component: MAX98090 component 2304 * @jack: jack to report detection events on 2305 * 2306 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2307 * being used to bring out signals to the processor then only platform 2308 * data configuration is needed for MAX98090 and processor GPIOs should 2309 * be configured using snd_soc_jack_add_gpios() instead. 2310 * 2311 * If no jack is supplied detection will be disabled. 2312 */ 2313 int max98090_mic_detect(struct snd_soc_component *component, 2314 struct snd_soc_jack *jack) 2315 { 2316 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2317 2318 dev_dbg(component->dev, "max98090_mic_detect\n"); 2319 2320 max98090->jack = jack; 2321 if (jack) { 2322 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2323 M98090_IJDET_MASK, 2324 1 << M98090_IJDET_SHIFT); 2325 } else { 2326 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2327 M98090_IJDET_MASK, 2328 0); 2329 } 2330 2331 /* Send an initial empty report */ 2332 snd_soc_jack_report(max98090->jack, 0, 2333 SND_JACK_HEADSET | SND_JACK_BTN_0); 2334 2335 queue_delayed_work(system_power_efficient_wq, 2336 &max98090->jack_work, 2337 msecs_to_jiffies(100)); 2338 2339 return 0; 2340 } 2341 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2342 2343 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2344 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2345 2346 static const struct snd_soc_dai_ops max98090_dai_ops = { 2347 .startup = max98090_dai_startup, 2348 .set_sysclk = max98090_dai_set_sysclk, 2349 .set_fmt = max98090_dai_set_fmt, 2350 .set_tdm_slot = max98090_set_tdm_slot, 2351 .hw_params = max98090_dai_hw_params, 2352 .mute_stream = max98090_dai_mute, 2353 .trigger = max98090_dai_trigger, 2354 .no_capture_mute = 1, 2355 }; 2356 2357 static struct snd_soc_dai_driver max98090_dai[] = { 2358 { 2359 .name = "HiFi", 2360 .playback = { 2361 .stream_name = "HiFi Playback", 2362 .channels_min = 2, 2363 .channels_max = 2, 2364 .rates = MAX98090_RATES, 2365 .formats = MAX98090_FORMATS, 2366 }, 2367 .capture = { 2368 .stream_name = "HiFi Capture", 2369 .channels_min = 1, 2370 .channels_max = 2, 2371 .rates = MAX98090_RATES, 2372 .formats = MAX98090_FORMATS, 2373 }, 2374 .ops = &max98090_dai_ops, 2375 } 2376 }; 2377 2378 static int max98090_probe(struct snd_soc_component *component) 2379 { 2380 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2381 struct max98090_cdata *cdata; 2382 enum max98090_type devtype; 2383 int ret = 0; 2384 int err; 2385 unsigned int micbias; 2386 2387 dev_dbg(component->dev, "max98090_probe\n"); 2388 2389 max98090->mclk = devm_clk_get(component->dev, "mclk"); 2390 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) 2391 return -EPROBE_DEFER; 2392 2393 max98090->component = component; 2394 2395 /* Reset the codec, the DSP core, and disable all interrupts */ 2396 max98090_reset(max98090); 2397 2398 /* Initialize private data */ 2399 2400 max98090->sysclk = (unsigned)-1; 2401 max98090->pclk = (unsigned)-1; 2402 max98090->master = false; 2403 2404 cdata = &max98090->dai[0]; 2405 cdata->rate = (unsigned)-1; 2406 cdata->fmt = (unsigned)-1; 2407 2408 max98090->lin_state = 0; 2409 max98090->pa1en = 0; 2410 max98090->pa2en = 0; 2411 2412 ret = snd_soc_component_read(component, M98090_REG_REVISION_ID); 2413 if (ret < 0) { 2414 dev_err(component->dev, "Failed to read device revision: %d\n", 2415 ret); 2416 goto err_access; 2417 } 2418 2419 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2420 devtype = MAX98090; 2421 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); 2422 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2423 devtype = MAX98091; 2424 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); 2425 } else { 2426 devtype = MAX98090; 2427 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); 2428 } 2429 2430 if (max98090->devtype != devtype) { 2431 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); 2432 max98090->devtype = devtype; 2433 } 2434 2435 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2436 2437 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2438 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, 2439 max98090_pll_det_enable_work); 2440 INIT_WORK(&max98090->pll_det_disable_work, 2441 max98090_pll_det_disable_work); 2442 2443 /* Enable jack detection */ 2444 snd_soc_component_write(component, M98090_REG_JACK_DETECT, 2445 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2446 2447 /* 2448 * Clear any old interrupts. 2449 * An old interrupt ocurring prior to installing the ISR 2450 * can keep a new interrupt from generating a trigger. 2451 */ 2452 snd_soc_component_read(component, M98090_REG_DEVICE_STATUS); 2453 2454 /* High Performance is default */ 2455 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2456 M98090_DACHP_MASK, 2457 1 << M98090_DACHP_SHIFT); 2458 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2459 M98090_PERFMODE_MASK, 2460 0 << M98090_PERFMODE_SHIFT); 2461 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL, 2462 M98090_ADCHP_MASK, 2463 1 << M98090_ADCHP_SHIFT); 2464 2465 /* Turn on VCM bandgap reference */ 2466 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, 2467 M98090_VCM_MODE_MASK); 2468 2469 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); 2470 if (err) { 2471 micbias = M98090_MBVSEL_2V8; 2472 dev_info(component->dev, "use default 2.8v micbias\n"); 2473 } else if (micbias > M98090_MBVSEL_2V8) { 2474 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); 2475 micbias = M98090_MBVSEL_2V8; 2476 } 2477 2478 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE, 2479 M98090_MBVSEL_MASK, micbias); 2480 2481 max98090_add_widgets(component); 2482 2483 err_access: 2484 return ret; 2485 } 2486 2487 static void max98090_remove(struct snd_soc_component *component) 2488 { 2489 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2490 2491 cancel_delayed_work_sync(&max98090->jack_work); 2492 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2493 cancel_work_sync(&max98090->pll_det_disable_work); 2494 max98090->component = NULL; 2495 } 2496 2497 static void max98090_seq_notifier(struct snd_soc_component *component, 2498 enum snd_soc_dapm_type event, int subseq) 2499 { 2500 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2501 2502 if (max98090->shdn_pending) { 2503 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2504 M98090_SHDNN_MASK, 0); 2505 msleep(40); 2506 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2507 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2508 max98090->shdn_pending = false; 2509 } 2510 } 2511 2512 static const struct snd_soc_component_driver soc_component_dev_max98090 = { 2513 .probe = max98090_probe, 2514 .remove = max98090_remove, 2515 .seq_notifier = max98090_seq_notifier, 2516 .set_bias_level = max98090_set_bias_level, 2517 .idle_bias_on = 1, 2518 .use_pmdown_time = 1, 2519 .endianness = 1, 2520 .non_legacy_dai_naming = 1, 2521 }; 2522 2523 static const struct regmap_config max98090_regmap = { 2524 .reg_bits = 8, 2525 .val_bits = 8, 2526 2527 .max_register = MAX98090_MAX_REGISTER, 2528 .reg_defaults = max98090_reg, 2529 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2530 .volatile_reg = max98090_volatile_register, 2531 .readable_reg = max98090_readable_register, 2532 .cache_type = REGCACHE_RBTREE, 2533 }; 2534 2535 static int max98090_i2c_probe(struct i2c_client *i2c, 2536 const struct i2c_device_id *i2c_id) 2537 { 2538 struct max98090_priv *max98090; 2539 const struct acpi_device_id *acpi_id; 2540 kernel_ulong_t driver_data = 0; 2541 int ret; 2542 2543 pr_debug("max98090_i2c_probe\n"); 2544 2545 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2546 GFP_KERNEL); 2547 if (max98090 == NULL) 2548 return -ENOMEM; 2549 2550 if (ACPI_HANDLE(&i2c->dev)) { 2551 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2552 &i2c->dev); 2553 if (!acpi_id) { 2554 dev_err(&i2c->dev, "No driver data\n"); 2555 return -EINVAL; 2556 } 2557 driver_data = acpi_id->driver_data; 2558 } else if (i2c_id) { 2559 driver_data = i2c_id->driver_data; 2560 } 2561 2562 max98090->devtype = driver_data; 2563 i2c_set_clientdata(i2c, max98090); 2564 max98090->pdata = i2c->dev.platform_data; 2565 2566 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", 2567 &max98090->dmic_freq); 2568 if (ret < 0) 2569 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; 2570 2571 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2572 if (IS_ERR(max98090->regmap)) { 2573 ret = PTR_ERR(max98090->regmap); 2574 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2575 goto err_enable; 2576 } 2577 2578 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2579 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2580 "max98090_interrupt", max98090); 2581 if (ret < 0) { 2582 dev_err(&i2c->dev, "request_irq failed: %d\n", 2583 ret); 2584 return ret; 2585 } 2586 2587 ret = devm_snd_soc_register_component(&i2c->dev, 2588 &soc_component_dev_max98090, max98090_dai, 2589 ARRAY_SIZE(max98090_dai)); 2590 err_enable: 2591 return ret; 2592 } 2593 2594 static void max98090_i2c_shutdown(struct i2c_client *i2c) 2595 { 2596 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); 2597 2598 /* 2599 * Enable volume smoothing, disable zero cross. This will cause 2600 * a quick 40ms ramp to mute on shutdown. 2601 */ 2602 regmap_write(max98090->regmap, 2603 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK); 2604 regmap_write(max98090->regmap, 2605 M98090_REG_DEVICE_SHUTDOWN, 0x00); 2606 msleep(40); 2607 } 2608 2609 static int max98090_i2c_remove(struct i2c_client *client) 2610 { 2611 max98090_i2c_shutdown(client); 2612 2613 return 0; 2614 } 2615 2616 #ifdef CONFIG_PM 2617 static int max98090_runtime_resume(struct device *dev) 2618 { 2619 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2620 2621 regcache_cache_only(max98090->regmap, false); 2622 2623 max98090_reset(max98090); 2624 2625 regcache_sync(max98090->regmap); 2626 2627 return 0; 2628 } 2629 2630 static int max98090_runtime_suspend(struct device *dev) 2631 { 2632 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2633 2634 regcache_cache_only(max98090->regmap, true); 2635 2636 return 0; 2637 } 2638 #endif 2639 2640 #ifdef CONFIG_PM_SLEEP 2641 static int max98090_resume(struct device *dev) 2642 { 2643 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2644 unsigned int status; 2645 2646 regcache_mark_dirty(max98090->regmap); 2647 2648 max98090_reset(max98090); 2649 2650 /* clear IRQ status */ 2651 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2652 2653 regcache_sync(max98090->regmap); 2654 2655 return 0; 2656 } 2657 #endif 2658 2659 static const struct dev_pm_ops max98090_pm = { 2660 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2661 max98090_runtime_resume, NULL) 2662 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume) 2663 }; 2664 2665 static const struct i2c_device_id max98090_i2c_id[] = { 2666 { "max98090", MAX98090 }, 2667 { "max98091", MAX98091 }, 2668 { } 2669 }; 2670 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2671 2672 #ifdef CONFIG_OF 2673 static const struct of_device_id max98090_of_match[] = { 2674 { .compatible = "maxim,max98090", }, 2675 { .compatible = "maxim,max98091", }, 2676 { } 2677 }; 2678 MODULE_DEVICE_TABLE(of, max98090_of_match); 2679 #endif 2680 2681 #ifdef CONFIG_ACPI 2682 static const struct acpi_device_id max98090_acpi_match[] = { 2683 { "193C9890", MAX98090 }, 2684 { } 2685 }; 2686 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2687 #endif 2688 2689 static struct i2c_driver max98090_i2c_driver = { 2690 .driver = { 2691 .name = "max98090", 2692 .pm = &max98090_pm, 2693 .of_match_table = of_match_ptr(max98090_of_match), 2694 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2695 }, 2696 .probe = max98090_i2c_probe, 2697 .shutdown = max98090_i2c_shutdown, 2698 .remove = max98090_i2c_remove, 2699 .id_table = max98090_i2c_id, 2700 }; 2701 2702 module_i2c_driver(max98090_i2c_driver); 2703 2704 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2705 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2706 MODULE_LICENSE("GPL"); 2707