1 // SPDX-License-Identifier: GPL-2.0 2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver 3 // Copyright 2017 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/regmap.h> 9 #include <linux/i2c.h> 10 #include <linux/err.h> 11 #include <linux/string.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/mutex.h> 15 #include <sound/tlv.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dapm.h> 19 20 #include "tscs42xx.h" 21 22 #define COEFF_SIZE 3 23 #define BIQUAD_COEFF_COUNT 5 24 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 25 26 #define COEFF_RAM_MAX_ADDR 0xcd 27 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 28 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 29 30 struct tscs42xx { 31 32 int bclk_ratio; 33 int samplerate; 34 unsigned int blrcm; 35 struct mutex audio_params_lock; 36 37 u8 coeff_ram[COEFF_RAM_SIZE]; 38 bool coeff_ram_synced; 39 struct mutex coeff_ram_lock; 40 41 struct mutex pll_lock; 42 43 struct regmap *regmap; 44 45 struct device *dev; 46 }; 47 48 struct coeff_ram_ctl { 49 unsigned int addr; 50 struct soc_bytes_ext bytes_ext; 51 }; 52 53 static bool tscs42xx_volatile(struct device *dev, unsigned int reg) 54 { 55 switch (reg) { 56 case R_DACCRWRL: 57 case R_DACCRWRM: 58 case R_DACCRWRH: 59 case R_DACCRRDL: 60 case R_DACCRRDM: 61 case R_DACCRRDH: 62 case R_DACCRSTAT: 63 case R_DACCRADDR: 64 case R_PLLCTL0: 65 return true; 66 default: 67 return false; 68 }; 69 } 70 71 static bool tscs42xx_precious(struct device *dev, unsigned int reg) 72 { 73 switch (reg) { 74 case R_DACCRWRL: 75 case R_DACCRWRM: 76 case R_DACCRWRH: 77 case R_DACCRRDL: 78 case R_DACCRRDM: 79 case R_DACCRRDH: 80 return true; 81 default: 82 return false; 83 }; 84 } 85 86 static const struct regmap_config tscs42xx_regmap = { 87 .reg_bits = 8, 88 .val_bits = 8, 89 90 .volatile_reg = tscs42xx_volatile, 91 .precious_reg = tscs42xx_precious, 92 .max_register = R_DACMBCREL3H, 93 94 .cache_type = REGCACHE_RBTREE, 95 .can_multi_write = true, 96 }; 97 98 #define MAX_PLL_LOCK_20MS_WAITS 1 99 static bool plls_locked(struct snd_soc_component *component) 100 { 101 int ret; 102 int count = MAX_PLL_LOCK_20MS_WAITS; 103 104 do { 105 ret = snd_soc_component_read32(component, R_PLLCTL0); 106 if (ret < 0) { 107 dev_err(component->dev, 108 "Failed to read PLL lock status (%d)\n", ret); 109 return false; 110 } else if (ret > 0) { 111 return true; 112 } 113 msleep(20); 114 } while (count--); 115 116 return false; 117 } 118 119 static int sample_rate_to_pll_freq_out(int sample_rate) 120 { 121 switch (sample_rate) { 122 case 11025: 123 case 22050: 124 case 44100: 125 case 88200: 126 return 112896000; 127 case 8000: 128 case 16000: 129 case 32000: 130 case 48000: 131 case 96000: 132 return 122880000; 133 default: 134 return -EINVAL; 135 } 136 } 137 138 #define DACCRSTAT_MAX_TRYS 10 139 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 140 unsigned int addr, unsigned int coeff_cnt) 141 { 142 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 143 int cnt; 144 int trys; 145 int ret; 146 147 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) { 148 149 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 150 ret = snd_soc_component_read32(component, R_DACCRSTAT); 151 if (ret < 0) { 152 dev_err(component->dev, 153 "Failed to read stat (%d)\n", ret); 154 return ret; 155 } 156 if (!ret) 157 break; 158 } 159 160 if (trys == DACCRSTAT_MAX_TRYS) { 161 ret = -EIO; 162 dev_err(component->dev, 163 "dac coefficient write error (%d)\n", ret); 164 return ret; 165 } 166 167 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr); 168 if (ret < 0) { 169 dev_err(component->dev, 170 "Failed to write dac ram address (%d)\n", ret); 171 return ret; 172 } 173 174 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL, 175 &coeff_ram[addr * COEFF_SIZE], 176 COEFF_SIZE); 177 if (ret < 0) { 178 dev_err(component->dev, 179 "Failed to write dac ram (%d)\n", ret); 180 return ret; 181 } 182 } 183 184 return 0; 185 } 186 187 static int power_up_audio_plls(struct snd_soc_component *component) 188 { 189 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 190 int freq_out; 191 int ret; 192 unsigned int mask; 193 unsigned int val; 194 195 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate); 196 switch (freq_out) { 197 case 122880000: /* 48k */ 198 mask = RM_PLLCTL1C_PDB_PLL1; 199 val = RV_PLLCTL1C_PDB_PLL1_ENABLE; 200 break; 201 case 112896000: /* 44.1k */ 202 mask = RM_PLLCTL1C_PDB_PLL2; 203 val = RV_PLLCTL1C_PDB_PLL2_ENABLE; 204 break; 205 default: 206 ret = -EINVAL; 207 dev_err(component->dev, 208 "Unrecognized PLL output freq (%d)\n", ret); 209 return ret; 210 } 211 212 mutex_lock(&tscs42xx->pll_lock); 213 214 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); 215 if (ret < 0) { 216 dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret); 217 goto exit; 218 } 219 220 if (!plls_locked(component)) { 221 dev_err(component->dev, "Failed to lock plls\n"); 222 ret = -ENOMSG; 223 goto exit; 224 } 225 226 ret = 0; 227 exit: 228 mutex_unlock(&tscs42xx->pll_lock); 229 230 return ret; 231 } 232 233 static int power_down_audio_plls(struct snd_soc_component *component) 234 { 235 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 236 int ret; 237 238 mutex_lock(&tscs42xx->pll_lock); 239 240 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 241 RM_PLLCTL1C_PDB_PLL1, 242 RV_PLLCTL1C_PDB_PLL1_DISABLE); 243 if (ret < 0) { 244 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 245 goto exit; 246 } 247 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 248 RM_PLLCTL1C_PDB_PLL2, 249 RV_PLLCTL1C_PDB_PLL2_DISABLE); 250 if (ret < 0) { 251 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 252 goto exit; 253 } 254 255 ret = 0; 256 exit: 257 mutex_unlock(&tscs42xx->pll_lock); 258 259 return ret; 260 } 261 262 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 263 struct snd_ctl_elem_value *ucontrol) 264 { 265 struct snd_soc_component *component = 266 snd_soc_kcontrol_component(kcontrol); 267 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 268 struct coeff_ram_ctl *ctl = 269 (struct coeff_ram_ctl *)kcontrol->private_value; 270 struct soc_bytes_ext *params = &ctl->bytes_ext; 271 272 mutex_lock(&tscs42xx->coeff_ram_lock); 273 274 memcpy(ucontrol->value.bytes.data, 275 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max); 276 277 mutex_unlock(&tscs42xx->coeff_ram_lock); 278 279 return 0; 280 } 281 282 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284 { 285 struct snd_soc_component *component = 286 snd_soc_kcontrol_component(kcontrol); 287 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 288 struct coeff_ram_ctl *ctl = 289 (struct coeff_ram_ctl *)kcontrol->private_value; 290 struct soc_bytes_ext *params = &ctl->bytes_ext; 291 unsigned int coeff_cnt = params->max / COEFF_SIZE; 292 int ret; 293 294 mutex_lock(&tscs42xx->coeff_ram_lock); 295 296 tscs42xx->coeff_ram_synced = false; 297 298 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], 299 ucontrol->value.bytes.data, params->max); 300 301 mutex_lock(&tscs42xx->pll_lock); 302 303 if (plls_locked(component)) { 304 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 305 ctl->addr, coeff_cnt); 306 if (ret < 0) { 307 dev_err(component->dev, 308 "Failed to flush coeff ram cache (%d)\n", ret); 309 goto exit; 310 } 311 tscs42xx->coeff_ram_synced = true; 312 } 313 314 ret = 0; 315 exit: 316 mutex_unlock(&tscs42xx->pll_lock); 317 318 mutex_unlock(&tscs42xx->coeff_ram_lock); 319 320 return ret; 321 } 322 323 /* Input L Capture Route */ 324 static char const * const input_select_text[] = { 325 "Line 1", "Line 2", "Line 3", "D2S" 326 }; 327 328 static const struct soc_enum left_input_select_enum = 329 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text), 330 input_select_text); 331 332 static const struct snd_kcontrol_new left_input_select = 333 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum); 334 335 /* Input R Capture Route */ 336 static const struct soc_enum right_input_select_enum = 337 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text), 338 input_select_text); 339 340 static const struct snd_kcontrol_new right_input_select = 341 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum); 342 343 /* Input Channel Mapping */ 344 static char const * const ch_map_select_text[] = { 345 "Normal", "Left to Right", "Right to Left", "Swap" 346 }; 347 348 static const struct soc_enum ch_map_select_enum = 349 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text), 350 ch_map_select_text); 351 352 static int dapm_vref_event(struct snd_soc_dapm_widget *w, 353 struct snd_kcontrol *kcontrol, int event) 354 { 355 msleep(20); 356 return 0; 357 } 358 359 static int dapm_micb_event(struct snd_soc_dapm_widget *w, 360 struct snd_kcontrol *kcontrol, int event) 361 { 362 msleep(20); 363 return 0; 364 } 365 366 static int pll_event(struct snd_soc_dapm_widget *w, 367 struct snd_kcontrol *kcontrol, int event) 368 { 369 struct snd_soc_component *component = 370 snd_soc_dapm_to_component(w->dapm); 371 int ret; 372 373 if (SND_SOC_DAPM_EVENT_ON(event)) 374 ret = power_up_audio_plls(component); 375 else 376 ret = power_down_audio_plls(component); 377 378 return ret; 379 } 380 381 static int dac_event(struct snd_soc_dapm_widget *w, 382 struct snd_kcontrol *kcontrol, int event) 383 { 384 struct snd_soc_component *component = 385 snd_soc_dapm_to_component(w->dapm); 386 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 387 int ret; 388 389 mutex_lock(&tscs42xx->coeff_ram_lock); 390 391 if (tscs42xx->coeff_ram_synced == false) { 392 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00, 393 COEFF_RAM_COEFF_COUNT); 394 if (ret < 0) 395 goto exit; 396 tscs42xx->coeff_ram_synced = true; 397 } 398 399 ret = 0; 400 exit: 401 mutex_unlock(&tscs42xx->coeff_ram_lock); 402 403 return ret; 404 } 405 406 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = { 407 /* Vref */ 408 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0, 409 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 410 411 /* PLL */ 412 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event, 413 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 414 415 /* Headphone */ 416 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0, 417 dac_event, SND_SOC_DAPM_POST_PMU), 418 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0, 419 dac_event, SND_SOC_DAPM_POST_PMU), 420 SND_SOC_DAPM_OUTPUT("Headphone L"), 421 SND_SOC_DAPM_OUTPUT("Headphone R"), 422 423 /* Speaker */ 424 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback", 425 R_PWRM2, FB_PWRM2_SPKL, 0, 426 dac_event, SND_SOC_DAPM_POST_PMU), 427 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback", 428 R_PWRM2, FB_PWRM2_SPKR, 0, 429 dac_event, SND_SOC_DAPM_POST_PMU), 430 SND_SOC_DAPM_OUTPUT("Speaker L"), 431 SND_SOC_DAPM_OUTPUT("Speaker R"), 432 433 /* Capture */ 434 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0), 435 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0), 436 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0), 437 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0), 438 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0), 439 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0), 440 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0), 441 442 /* Capture Input */ 443 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2, 444 FB_PWRM2_INSELL, 0, &left_input_select), 445 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2, 446 FB_PWRM2_INSELR, 0, &right_input_select), 447 448 /* Digital Mic */ 449 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL, 450 FB_DMICCTL_DMICEN, 0, NULL, 451 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 452 453 /* Analog Mic */ 454 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB, 455 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 456 457 /* Line In */ 458 SND_SOC_DAPM_INPUT("Line In 1 L"), 459 SND_SOC_DAPM_INPUT("Line In 1 R"), 460 SND_SOC_DAPM_INPUT("Line In 2 L"), 461 SND_SOC_DAPM_INPUT("Line In 2 R"), 462 SND_SOC_DAPM_INPUT("Line In 3 L"), 463 SND_SOC_DAPM_INPUT("Line In 3 R"), 464 }; 465 466 static const struct snd_soc_dapm_route tscs42xx_intercon[] = { 467 {"DAC L", NULL, "PLL"}, 468 {"DAC R", NULL, "PLL"}, 469 {"DAC L", NULL, "Vref"}, 470 {"DAC R", NULL, "Vref"}, 471 {"Headphone L", NULL, "DAC L"}, 472 {"Headphone R", NULL, "DAC R"}, 473 474 {"ClassD L", NULL, "PLL"}, 475 {"ClassD R", NULL, "PLL"}, 476 {"ClassD L", NULL, "Vref"}, 477 {"ClassD R", NULL, "Vref"}, 478 {"Speaker L", NULL, "ClassD L"}, 479 {"Speaker R", NULL, "ClassD R"}, 480 481 {"Input L Capture Route", NULL, "Vref"}, 482 {"Input R Capture Route", NULL, "Vref"}, 483 484 {"Mic Bias", NULL, "Vref"}, 485 486 {"Input L Capture Route", "Line 1", "Line In 1 L"}, 487 {"Input R Capture Route", "Line 1", "Line In 1 R"}, 488 {"Input L Capture Route", "Line 2", "Line In 2 L"}, 489 {"Input R Capture Route", "Line 2", "Line In 2 R"}, 490 {"Input L Capture Route", "Line 3", "Line In 3 L"}, 491 {"Input R Capture Route", "Line 3", "Line In 3 R"}, 492 493 {"Analog In PGA L", NULL, "Input L Capture Route"}, 494 {"Analog In PGA R", NULL, "Input R Capture Route"}, 495 {"Analog Boost L", NULL, "Analog In PGA L"}, 496 {"Analog Boost R", NULL, "Analog In PGA R"}, 497 {"ADC Mute", NULL, "Analog Boost L"}, 498 {"ADC Mute", NULL, "Analog Boost R"}, 499 {"ADC L", NULL, "PLL"}, 500 {"ADC R", NULL, "PLL"}, 501 {"ADC L", NULL, "ADC Mute"}, 502 {"ADC R", NULL, "ADC Mute"}, 503 }; 504 505 /************ 506 * CONTROLS * 507 ************/ 508 509 static char const * const eq_band_enable_text[] = { 510 "Prescale only", 511 "Band1", 512 "Band1:2", 513 "Band1:3", 514 "Band1:4", 515 "Band1:5", 516 "Band1:6", 517 }; 518 519 static char const * const level_detection_text[] = { 520 "Average", 521 "Peak", 522 }; 523 524 static char const * const level_detection_window_text[] = { 525 "512 Samples", 526 "64 Samples", 527 }; 528 529 static char const * const compressor_ratio_text[] = { 530 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 531 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 532 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1", 533 }; 534 535 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0); 536 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0); 537 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0); 538 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0); 539 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0); 540 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0); 541 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650); 542 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0); 543 544 static const struct soc_enum eq1_band_enable_enum = 545 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE, 546 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 547 548 static const struct soc_enum eq2_band_enable_enum = 549 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE, 550 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 551 552 static const struct soc_enum cle_level_detection_enum = 553 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE, 554 ARRAY_SIZE(level_detection_text), 555 level_detection_text); 556 557 static const struct soc_enum cle_level_detection_window_enum = 558 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL, 559 ARRAY_SIZE(level_detection_window_text), 560 level_detection_window_text); 561 562 static const struct soc_enum mbc_level_detection_enums[] = { 563 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 564 ARRAY_SIZE(level_detection_text), 565 level_detection_text), 566 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 567 ARRAY_SIZE(level_detection_text), 568 level_detection_text), 569 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 570 ARRAY_SIZE(level_detection_text), 571 level_detection_text), 572 }; 573 574 static const struct soc_enum mbc_level_detection_window_enums[] = { 575 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 576 ARRAY_SIZE(level_detection_window_text), 577 level_detection_window_text), 578 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 579 ARRAY_SIZE(level_detection_window_text), 580 level_detection_window_text), 581 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 582 ARRAY_SIZE(level_detection_window_text), 583 level_detection_window_text), 584 }; 585 586 static const struct soc_enum compressor_ratio_enum = 587 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT, 588 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 589 590 static const struct soc_enum dac_mbc1_compressor_ratio_enum = 591 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO, 592 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 593 594 static const struct soc_enum dac_mbc2_compressor_ratio_enum = 595 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO, 596 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 597 598 static const struct soc_enum dac_mbc3_compressor_ratio_enum = 599 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO, 600 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 601 602 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 603 struct snd_ctl_elem_info *ucontrol) 604 { 605 struct coeff_ram_ctl *ctl = 606 (struct coeff_ram_ctl *)kcontrol->private_value; 607 struct soc_bytes_ext *params = &ctl->bytes_ext; 608 609 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 610 ucontrol->count = params->max; 611 612 return 0; 613 } 614 615 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 616 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 617 .info = bytes_info_ext, \ 618 .get = coeff_ram_get, .put = coeff_ram_put, \ 619 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 620 .addr = xaddr, \ 621 .bytes_ext = {.max = xcount, }, \ 622 } \ 623 } 624 625 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = { 626 /* Volumes */ 627 SOC_DOUBLE_R_TLV("Headphone Playback Volume", R_HPVOLL, R_HPVOLR, 628 FB_HPVOLL, 0x7F, 0, hpvol_scale), 629 SOC_DOUBLE_R_TLV("Speaker Playback Volume", R_SPKVOLL, R_SPKVOLR, 630 FB_SPKVOLL, 0x7F, 0, spkvol_scale), 631 SOC_DOUBLE_R_TLV("Master Playback Volume", R_DACVOLL, R_DACVOLR, 632 FB_DACVOLL, 0xFF, 0, dacvol_scale), 633 SOC_DOUBLE_R_TLV("PCM Capture Volume", R_ADCVOLL, R_ADCVOLR, 634 FB_ADCVOLL, 0xFF, 0, adcvol_scale), 635 SOC_DOUBLE_R_TLV("Master Capture Volume", R_INVOLL, R_INVOLR, 636 FB_INVOLL, 0x3F, 0, invol_scale), 637 638 /* INSEL */ 639 SOC_DOUBLE_R_TLV("Mic Boost Capture Volume", R_INSELL, R_INSELR, 640 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB, 641 0, mic_boost_scale), 642 643 /* Input Channel Map */ 644 SOC_ENUM("Input Channel Map", ch_map_select_enum), 645 646 /* Coefficient Ram */ 647 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00), 648 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05), 649 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a), 650 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f), 651 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14), 652 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19), 653 654 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20), 655 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25), 656 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a), 657 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f), 658 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34), 659 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39), 660 661 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f), 662 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f), 663 664 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40), 665 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45), 666 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a), 667 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f), 668 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54), 669 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59), 670 671 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60), 672 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65), 673 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a), 674 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f), 675 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74), 676 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79), 677 678 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f), 679 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f), 680 681 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80), 682 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85), 683 684 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 685 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 686 687 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 688 689 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 690 691 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96), 692 693 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97), 694 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c), 695 696 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 697 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 698 699 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 700 701 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 702 703 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad), 704 705 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae), 706 707 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf), 708 709 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0), 710 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5), 711 712 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba), 713 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf), 714 715 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4), 716 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9), 717 718 /* EQ */ 719 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0), 720 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0), 721 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum), 722 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum), 723 724 /* CLE */ 725 SOC_ENUM("CLE Level Detect", 726 cle_level_detection_enum), 727 SOC_ENUM("CLE Level Detect Win", 728 cle_level_detection_window_enum), 729 SOC_SINGLE("Expander Switch", 730 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0), 731 SOC_SINGLE("Limiter Switch", 732 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0), 733 SOC_SINGLE("Comp Switch", 734 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0), 735 SOC_SINGLE_TLV("CLE Make-Up Gain Playback Volume", 736 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale), 737 SOC_SINGLE_TLV("Comp Thresh Playback Volume", 738 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale), 739 SOC_ENUM("Comp Ratio", compressor_ratio_enum), 740 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2), 741 742 /* Effects */ 743 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0), 744 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0), 745 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0), 746 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0), 747 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0), 748 749 /* MBC */ 750 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 751 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 752 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 753 SOC_ENUM("MBC Band1 Level Detect", 754 mbc_level_detection_enums[0]), 755 SOC_ENUM("MBC Band2 Level Detect", 756 mbc_level_detection_enums[1]), 757 SOC_ENUM("MBC Band3 Level Detect", 758 mbc_level_detection_enums[2]), 759 SOC_ENUM("MBC Band1 Level Detect Win", 760 mbc_level_detection_window_enums[0]), 761 SOC_ENUM("MBC Band2 Level Detect Win", 762 mbc_level_detection_window_enums[1]), 763 SOC_ENUM("MBC Band3 Level Detect Win", 764 mbc_level_detection_window_enums[2]), 765 766 SOC_SINGLE("MBC1 Phase Invert Switch", 767 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0), 768 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Playback Volume", 769 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale), 770 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Playback Volume", 771 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale), 772 SOC_ENUM("DAC MBC1 Comp Ratio", 773 dac_mbc1_compressor_ratio_enum), 774 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2), 775 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const", 776 R_DACMBCREL1L, 2), 777 778 SOC_SINGLE("MBC2 Phase Invert Switch", 779 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0), 780 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Playback Volume", 781 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale), 782 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Playback Volume", 783 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale), 784 SOC_ENUM("DAC MBC2 Comp Ratio", 785 dac_mbc2_compressor_ratio_enum), 786 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2), 787 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const", 788 R_DACMBCREL2L, 2), 789 790 SOC_SINGLE("MBC3 Phase Invert Switch", 791 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0), 792 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Playback Volume", 793 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale), 794 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Playback Volume", 795 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale), 796 SOC_ENUM("DAC MBC3 Comp Ratio", 797 dac_mbc3_compressor_ratio_enum), 798 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2), 799 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const", 800 R_DACMBCREL3L, 2), 801 }; 802 803 static int setup_sample_format(struct snd_soc_component *component, 804 snd_pcm_format_t format) 805 { 806 unsigned int width; 807 int ret; 808 809 switch (format) { 810 case SNDRV_PCM_FORMAT_S16_LE: 811 width = RV_AIC1_WL_16; 812 break; 813 case SNDRV_PCM_FORMAT_S20_3LE: 814 width = RV_AIC1_WL_20; 815 break; 816 case SNDRV_PCM_FORMAT_S24_LE: 817 width = RV_AIC1_WL_24; 818 break; 819 case SNDRV_PCM_FORMAT_S32_LE: 820 width = RV_AIC1_WL_32; 821 break; 822 default: 823 ret = -EINVAL; 824 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 825 return ret; 826 } 827 ret = snd_soc_component_update_bits(component, 828 R_AIC1, RM_AIC1_WL, width); 829 if (ret < 0) { 830 dev_err(component->dev, 831 "Failed to set sample width (%d)\n", ret); 832 return ret; 833 } 834 835 return 0; 836 } 837 838 static int setup_sample_rate(struct snd_soc_component *component, 839 unsigned int rate) 840 { 841 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 842 unsigned int br, bm; 843 int ret; 844 845 switch (rate) { 846 case 8000: 847 br = RV_DACSR_DBR_32; 848 bm = RV_DACSR_DBM_PT25; 849 break; 850 case 16000: 851 br = RV_DACSR_DBR_32; 852 bm = RV_DACSR_DBM_PT5; 853 break; 854 case 24000: 855 br = RV_DACSR_DBR_48; 856 bm = RV_DACSR_DBM_PT5; 857 break; 858 case 32000: 859 br = RV_DACSR_DBR_32; 860 bm = RV_DACSR_DBM_1; 861 break; 862 case 48000: 863 br = RV_DACSR_DBR_48; 864 bm = RV_DACSR_DBM_1; 865 break; 866 case 96000: 867 br = RV_DACSR_DBR_48; 868 bm = RV_DACSR_DBM_2; 869 break; 870 case 11025: 871 br = RV_DACSR_DBR_44_1; 872 bm = RV_DACSR_DBM_PT25; 873 break; 874 case 22050: 875 br = RV_DACSR_DBR_44_1; 876 bm = RV_DACSR_DBM_PT5; 877 break; 878 case 44100: 879 br = RV_DACSR_DBR_44_1; 880 bm = RV_DACSR_DBM_1; 881 break; 882 case 88200: 883 br = RV_DACSR_DBR_44_1; 884 bm = RV_DACSR_DBM_2; 885 break; 886 default: 887 dev_err(component->dev, "Unsupported sample rate %d\n", rate); 888 return -EINVAL; 889 } 890 891 /* DAC and ADC share bit and frame clock */ 892 ret = snd_soc_component_update_bits(component, 893 R_DACSR, RM_DACSR_DBR, br); 894 if (ret < 0) { 895 dev_err(component->dev, 896 "Failed to update register (%d)\n", ret); 897 return ret; 898 } 899 ret = snd_soc_component_update_bits(component, 900 R_DACSR, RM_DACSR_DBM, bm); 901 if (ret < 0) { 902 dev_err(component->dev, 903 "Failed to update register (%d)\n", ret); 904 return ret; 905 } 906 ret = snd_soc_component_update_bits(component, 907 R_ADCSR, RM_DACSR_DBR, br); 908 if (ret < 0) { 909 dev_err(component->dev, 910 "Failed to update register (%d)\n", ret); 911 return ret; 912 } 913 ret = snd_soc_component_update_bits(component, 914 R_ADCSR, RM_DACSR_DBM, bm); 915 if (ret < 0) { 916 dev_err(component->dev, 917 "Failed to update register (%d)\n", ret); 918 return ret; 919 } 920 921 mutex_lock(&tscs42xx->audio_params_lock); 922 923 tscs42xx->samplerate = rate; 924 925 mutex_unlock(&tscs42xx->audio_params_lock); 926 927 return 0; 928 } 929 930 struct reg_setting { 931 unsigned int addr; 932 unsigned int val; 933 unsigned int mask; 934 }; 935 936 #define PLL_REG_SETTINGS_COUNT 13 937 struct pll_ctl { 938 int input_freq; 939 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 940 }; 941 942 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \ 943 rc, r12, r1b_h, re, rf, r10, r11) \ 944 { \ 945 .input_freq = f, \ 946 .settings = { \ 947 {R_TIMEBASE, rt, 0xFF}, \ 948 {R_PLLCTLD, rd, 0xFF}, \ 949 {R_PLLCTL1B, r1b_l, 0x0F}, \ 950 {R_PLLCTL9, r9, 0xFF}, \ 951 {R_PLLCTLA, ra, 0xFF}, \ 952 {R_PLLCTLB, rb, 0xFF}, \ 953 {R_PLLCTLC, rc, 0xFF}, \ 954 {R_PLLCTL12, r12, 0xFF}, \ 955 {R_PLLCTL1B, r1b_h, 0xF0}, \ 956 {R_PLLCTLE, re, 0xFF}, \ 957 {R_PLLCTLF, rf, 0xFF}, \ 958 {R_PLLCTL10, r10, 0xFF}, \ 959 {R_PLLCTL11, r11, 0xFF}, \ 960 }, \ 961 } 962 963 static const struct pll_ctl pll_ctls[] = { 964 PLL_CTL(1411200, 0x05, 965 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04, 966 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02), 967 PLL_CTL(1536000, 0x05, 968 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01, 969 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01), 970 PLL_CTL(2822400, 0x0A, 971 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04, 972 0x22, 0x10, 0x05, 0x03, 0x58, 0x02), 973 PLL_CTL(3072000, 0x0B, 974 0x22, 0x04, 0x07, 0x03, 0x48, 0x03, 975 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01), 976 PLL_CTL(5644800, 0x15, 977 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04, 978 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01), 979 PLL_CTL(6144000, 0x17, 980 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01, 981 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01), 982 PLL_CTL(12000000, 0x2E, 983 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03, 984 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04), 985 PLL_CTL(19200000, 0x4A, 986 0x13, 0x04, 0x14, 0x03, 0x80, 0x01, 987 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01), 988 PLL_CTL(22000000, 0x55, 989 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06, 990 0x22, 0x10, 0x26, 0x03, 0x49, 0x02), 991 PLL_CTL(22579200, 0x57, 992 0x22, 0x04, 0x31, 0x03, 0x20, 0x03, 993 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01), 994 PLL_CTL(24000000, 0x5D, 995 0x13, 0x04, 0x19, 0x03, 0x80, 0x01, 996 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02), 997 PLL_CTL(24576000, 0x5F, 998 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01, 999 0x22, 0x10, 0x40, 0x03, 0x72, 0x03), 1000 PLL_CTL(27000000, 0x68, 1001 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04, 1002 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06), 1003 PLL_CTL(36000000, 0x8C, 1004 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03, 1005 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04), 1006 PLL_CTL(25000000, 0x61, 1007 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03, 1008 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02), 1009 PLL_CTL(26000000, 0x65, 1010 0x23, 0x04, 0x41, 0x05, 0x00, 0x06, 1011 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01), 1012 PLL_CTL(12288000, 0x2F, 1013 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02, 1014 0x22, 0x10, 0x20, 0x03, 0x72, 0x03), 1015 PLL_CTL(40000000, 0x9B, 1016 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04, 1017 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06), 1018 PLL_CTL(512000, 0x01, 1019 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02, 1020 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03), 1021 PLL_CTL(705600, 0x02, 1022 0x22, 0x04, 0x02, 0x03, 0x15, 0x04, 1023 0x22, 0x10, 0x01, 0x04, 0x80, 0x02), 1024 PLL_CTL(1024000, 0x03, 1025 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02, 1026 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03), 1027 PLL_CTL(2048000, 0x07, 1028 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02, 1029 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03), 1030 PLL_CTL(2400000, 0x08, 1031 0x22, 0x04, 0x05, 0x03, 0x00, 0x03, 1032 0x23, 0x10, 0x05, 0x05, 0x98, 0x04), 1033 }; 1034 1035 static const struct pll_ctl *get_pll_ctl(int input_freq) 1036 { 1037 int i; 1038 const struct pll_ctl *pll_ctl = NULL; 1039 1040 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 1041 if (input_freq == pll_ctls[i].input_freq) { 1042 pll_ctl = &pll_ctls[i]; 1043 break; 1044 } 1045 1046 return pll_ctl; 1047 } 1048 1049 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component, 1050 const int input_freq) 1051 { 1052 int ret; 1053 int i; 1054 const struct pll_ctl *pll_ctl; 1055 1056 pll_ctl = get_pll_ctl(input_freq); 1057 if (!pll_ctl) { 1058 ret = -EINVAL; 1059 dev_err(component->dev, "No PLL input entry for %d (%d)\n", 1060 input_freq, ret); 1061 return ret; 1062 } 1063 1064 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 1065 ret = snd_soc_component_update_bits(component, 1066 pll_ctl->settings[i].addr, 1067 pll_ctl->settings[i].mask, 1068 pll_ctl->settings[i].val); 1069 if (ret < 0) { 1070 dev_err(component->dev, "Failed to set pll ctl (%d)\n", 1071 ret); 1072 return ret; 1073 } 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int tscs42xx_hw_params(struct snd_pcm_substream *substream, 1080 struct snd_pcm_hw_params *params, 1081 struct snd_soc_dai *codec_dai) 1082 { 1083 struct snd_soc_component *component = codec_dai->component; 1084 int ret; 1085 1086 ret = setup_sample_format(component, params_format(params)); 1087 if (ret < 0) { 1088 dev_err(component->dev, "Failed to setup sample format (%d)\n", 1089 ret); 1090 return ret; 1091 } 1092 1093 ret = setup_sample_rate(component, params_rate(params)); 1094 if (ret < 0) { 1095 dev_err(component->dev, 1096 "Failed to setup sample rate (%d)\n", ret); 1097 return ret; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static inline int dac_mute(struct snd_soc_component *component) 1104 { 1105 int ret; 1106 1107 ret = snd_soc_component_update_bits(component, 1108 R_CNVRTR1, RM_CNVRTR1_DACMU, 1109 RV_CNVRTR1_DACMU_ENABLE); 1110 if (ret < 0) { 1111 dev_err(component->dev, "Failed to mute DAC (%d)\n", 1112 ret); 1113 return ret; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static inline int dac_unmute(struct snd_soc_component *component) 1120 { 1121 int ret; 1122 1123 ret = snd_soc_component_update_bits(component, 1124 R_CNVRTR1, RM_CNVRTR1_DACMU, 1125 RV_CNVRTR1_DACMU_DISABLE); 1126 if (ret < 0) { 1127 dev_err(component->dev, "Failed to unmute DAC (%d)\n", 1128 ret); 1129 return ret; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static inline int adc_mute(struct snd_soc_component *component) 1136 { 1137 int ret; 1138 1139 ret = snd_soc_component_update_bits(component, 1140 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE); 1141 if (ret < 0) { 1142 dev_err(component->dev, "Failed to mute ADC (%d)\n", 1143 ret); 1144 return ret; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static inline int adc_unmute(struct snd_soc_component *component) 1151 { 1152 int ret; 1153 1154 ret = snd_soc_component_update_bits(component, 1155 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE); 1156 if (ret < 0) { 1157 dev_err(component->dev, "Failed to unmute ADC (%d)\n", 1158 ret); 1159 return ret; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1166 { 1167 struct snd_soc_component *component = dai->component; 1168 int ret; 1169 1170 if (mute) 1171 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1172 ret = dac_mute(component); 1173 else 1174 ret = adc_mute(component); 1175 else 1176 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1177 ret = dac_unmute(component); 1178 else 1179 ret = adc_unmute(component); 1180 1181 return ret; 1182 } 1183 1184 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1185 unsigned int fmt) 1186 { 1187 struct snd_soc_component *component = codec_dai->component; 1188 int ret; 1189 1190 /* Slave mode not supported since it needs always-on frame clock */ 1191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1192 case SND_SOC_DAIFMT_CBM_CFM: 1193 ret = snd_soc_component_update_bits(component, 1194 R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER); 1195 if (ret < 0) { 1196 dev_err(component->dev, 1197 "Failed to set codec DAI master (%d)\n", ret); 1198 return ret; 1199 } 1200 break; 1201 default: 1202 ret = -EINVAL; 1203 dev_err(component->dev, "Unsupported format (%d)\n", ret); 1204 return ret; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, 1211 unsigned int ratio) 1212 { 1213 struct snd_soc_component *component = codec_dai->component; 1214 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1215 unsigned int value; 1216 int ret = 0; 1217 1218 switch (ratio) { 1219 case 32: 1220 value = RV_DACSR_DBCM_32; 1221 break; 1222 case 40: 1223 value = RV_DACSR_DBCM_40; 1224 break; 1225 case 64: 1226 value = RV_DACSR_DBCM_64; 1227 break; 1228 default: 1229 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 1230 return -EINVAL; 1231 } 1232 1233 ret = snd_soc_component_update_bits(component, 1234 R_DACSR, RM_DACSR_DBCM, value); 1235 if (ret < 0) { 1236 dev_err(component->dev, 1237 "Failed to set DAC BCLK ratio (%d)\n", ret); 1238 return ret; 1239 } 1240 ret = snd_soc_component_update_bits(component, 1241 R_ADCSR, RM_ADCSR_ABCM, value); 1242 if (ret < 0) { 1243 dev_err(component->dev, 1244 "Failed to set ADC BCLK ratio (%d)\n", ret); 1245 return ret; 1246 } 1247 1248 mutex_lock(&tscs42xx->audio_params_lock); 1249 1250 tscs42xx->bclk_ratio = ratio; 1251 1252 mutex_unlock(&tscs42xx->audio_params_lock); 1253 1254 return 0; 1255 } 1256 1257 static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1258 int clk_id, unsigned int freq, int dir) 1259 { 1260 struct snd_soc_component *component = codec_dai->component; 1261 int ret; 1262 1263 switch (clk_id) { 1264 case TSCS42XX_PLL_SRC_XTAL: 1265 case TSCS42XX_PLL_SRC_MCLK1: 1266 ret = snd_soc_component_write(component, R_PLLREFSEL, 1267 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 | 1268 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1); 1269 if (ret < 0) { 1270 dev_err(component->dev, 1271 "Failed to set pll reference input (%d)\n", 1272 ret); 1273 return ret; 1274 } 1275 break; 1276 case TSCS42XX_PLL_SRC_MCLK2: 1277 ret = snd_soc_component_write(component, R_PLLREFSEL, 1278 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 | 1279 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2); 1280 if (ret < 0) { 1281 dev_err(component->dev, 1282 "Failed to set PLL reference (%d)\n", ret); 1283 return ret; 1284 } 1285 break; 1286 default: 1287 dev_err(component->dev, "pll src is unsupported\n"); 1288 return -EINVAL; 1289 } 1290 1291 ret = set_pll_ctl_from_input_freq(component, freq); 1292 if (ret < 0) { 1293 dev_err(component->dev, 1294 "Failed to setup PLL input freq (%d)\n", ret); 1295 return ret; 1296 } 1297 1298 return 0; 1299 } 1300 1301 static const struct snd_soc_dai_ops tscs42xx_dai_ops = { 1302 .hw_params = tscs42xx_hw_params, 1303 .mute_stream = tscs42xx_mute_stream, 1304 .set_fmt = tscs42xx_set_dai_fmt, 1305 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, 1306 .set_sysclk = tscs42xx_set_dai_sysclk, 1307 }; 1308 1309 static int part_is_valid(struct tscs42xx *tscs42xx) 1310 { 1311 int val; 1312 int ret; 1313 unsigned int reg; 1314 1315 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); 1316 if (ret < 0) 1317 return ret; 1318 1319 val = reg << 8; 1320 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); 1321 if (ret < 0) 1322 return ret; 1323 1324 val |= reg; 1325 1326 switch (val) { 1327 case 0x4A74: 1328 case 0x4A73: 1329 return true; 1330 default: 1331 return false; 1332 }; 1333 } 1334 1335 static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = { 1336 .dapm_widgets = tscs42xx_dapm_widgets, 1337 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), 1338 .dapm_routes = tscs42xx_intercon, 1339 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon), 1340 .controls = tscs42xx_snd_controls, 1341 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls), 1342 .idle_bias_on = 1, 1343 .use_pmdown_time = 1, 1344 .endianness = 1, 1345 .non_legacy_dai_naming = 1, 1346 }; 1347 1348 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx) 1349 { 1350 static const u8 norm_addrs[] = { 1351 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a, 1352 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 1353 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85, 1354 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0, 1355 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 1356 }; 1357 u8 *coeff_ram = tscs42xx->coeff_ram; 1358 int i; 1359 1360 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 1361 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 1362 } 1363 1364 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000 1365 1366 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1367 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1368 1369 static struct snd_soc_dai_driver tscs42xx_dai = { 1370 .name = "tscs42xx-HiFi", 1371 .playback = { 1372 .stream_name = "HiFi Playback", 1373 .channels_min = 2, 1374 .channels_max = 2, 1375 .rates = TSCS42XX_RATES, 1376 .formats = TSCS42XX_FORMATS,}, 1377 .capture = { 1378 .stream_name = "HiFi Capture", 1379 .channels_min = 2, 1380 .channels_max = 2, 1381 .rates = TSCS42XX_RATES, 1382 .formats = TSCS42XX_FORMATS,}, 1383 .ops = &tscs42xx_dai_ops, 1384 .symmetric_rates = 1, 1385 .symmetric_channels = 1, 1386 .symmetric_samplebits = 1, 1387 }; 1388 1389 static const struct reg_sequence tscs42xx_patch[] = { 1390 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, 1391 }; 1392 1393 static int tscs42xx_i2c_probe(struct i2c_client *i2c, 1394 const struct i2c_device_id *id) 1395 { 1396 struct tscs42xx *tscs42xx; 1397 int ret = 0; 1398 1399 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); 1400 if (!tscs42xx) { 1401 ret = -ENOMEM; 1402 dev_err(&i2c->dev, 1403 "Failed to allocate memory for data (%d)\n", ret); 1404 return ret; 1405 } 1406 i2c_set_clientdata(i2c, tscs42xx); 1407 tscs42xx->dev = &i2c->dev; 1408 1409 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); 1410 if (IS_ERR(tscs42xx->regmap)) { 1411 ret = PTR_ERR(tscs42xx->regmap); 1412 dev_err(tscs42xx->dev, "Failed to allocate regmap (%d)\n", ret); 1413 return ret; 1414 } 1415 1416 init_coeff_ram_cache(tscs42xx); 1417 1418 ret = part_is_valid(tscs42xx); 1419 if (ret <= 0) { 1420 dev_err(tscs42xx->dev, "No valid part (%d)\n", ret); 1421 ret = -ENODEV; 1422 return ret; 1423 } 1424 1425 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); 1426 if (ret < 0) { 1427 dev_err(tscs42xx->dev, "Failed to reset device (%d)\n", ret); 1428 return ret; 1429 } 1430 1431 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, 1432 ARRAY_SIZE(tscs42xx_patch)); 1433 if (ret < 0) { 1434 dev_err(tscs42xx->dev, "Failed to apply patch (%d)\n", ret); 1435 return ret; 1436 } 1437 1438 mutex_init(&tscs42xx->audio_params_lock); 1439 mutex_init(&tscs42xx->coeff_ram_lock); 1440 mutex_init(&tscs42xx->pll_lock); 1441 1442 ret = devm_snd_soc_register_component(tscs42xx->dev, 1443 &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1); 1444 if (ret) { 1445 dev_err(tscs42xx->dev, "Failed to register codec (%d)\n", ret); 1446 return ret; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static const struct i2c_device_id tscs42xx_i2c_id[] = { 1453 { "tscs42A1", 0 }, 1454 { "tscs42A2", 0 }, 1455 { } 1456 }; 1457 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id); 1458 1459 static const struct of_device_id tscs42xx_of_match[] = { 1460 { .compatible = "tempo,tscs42A1", }, 1461 { .compatible = "tempo,tscs42A2", }, 1462 { } 1463 }; 1464 MODULE_DEVICE_TABLE(of, tscs42xx_of_match); 1465 1466 static struct i2c_driver tscs42xx_i2c_driver = { 1467 .driver = { 1468 .name = "tscs42xx", 1469 .of_match_table = tscs42xx_of_match, 1470 }, 1471 .probe = tscs42xx_i2c_probe, 1472 .id_table = tscs42xx_i2c_id, 1473 }; 1474 1475 module_i2c_driver(tscs42xx_i2c_driver); 1476 1477 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 1478 MODULE_DESCRIPTION("ASoC TSCS42xx driver"); 1479 MODULE_LICENSE("GPL"); 1480