1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * Derived mostly from Intel HDA driver with following copyrights: 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 12 * 13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 14 */ 15 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/delay.h> 22 #include <sound/pcm.h> 23 #include <sound/soc-acpi.h> 24 #include <sound/soc-acpi-intel-match.h> 25 #include <sound/hda_register.h> 26 #include <sound/hdaudio.h> 27 #include <sound/hda_i915.h> 28 #include <sound/hda_codec.h> 29 #include "skl.h" 30 #include "skl-sst-dsp.h" 31 #include "skl-sst-ipc.h" 32 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 33 #include "../../../soc/codecs/hdac_hda.h" 34 #endif 35 static int skl_pci_binding; 36 module_param_named(pci_binding, skl_pci_binding, int, 0444); 37 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); 38 39 /* 40 * initialize the PCI registers 41 */ 42 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 43 unsigned char mask, unsigned char val) 44 { 45 unsigned char data; 46 47 pci_read_config_byte(pci, reg, &data); 48 data &= ~mask; 49 data |= (val & mask); 50 pci_write_config_byte(pci, reg, data); 51 } 52 53 static void skl_init_pci(struct skl *skl) 54 { 55 struct hdac_bus *bus = skl_to_bus(skl); 56 57 /* 58 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 59 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 60 * Ensuring these bits are 0 clears playback static on some HD Audio 61 * codecs. 62 * The PCI register TCSEL is defined in the Intel manuals. 63 */ 64 dev_dbg(bus->dev, "Clearing TCSEL\n"); 65 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 66 } 67 68 static void update_pci_dword(struct pci_dev *pci, 69 unsigned int reg, u32 mask, u32 val) 70 { 71 u32 data = 0; 72 73 pci_read_config_dword(pci, reg, &data); 74 data &= ~mask; 75 data |= (val & mask); 76 pci_write_config_dword(pci, reg, data); 77 } 78 79 /* 80 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 81 * 82 * @dev: device pointer 83 * @enable: enable/disable flag 84 */ 85 static void skl_enable_miscbdcge(struct device *dev, bool enable) 86 { 87 struct pci_dev *pci = to_pci_dev(dev); 88 u32 val; 89 90 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 91 92 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 93 } 94 95 /** 96 * skl_clock_power_gating: Enable/Disable clock and power gating 97 * 98 * @dev: Device pointer 99 * @enable: Enable/Disable flag 100 */ 101 static void skl_clock_power_gating(struct device *dev, bool enable) 102 { 103 struct pci_dev *pci = to_pci_dev(dev); 104 struct hdac_bus *bus = pci_get_drvdata(pci); 105 u32 val; 106 107 /* Update PDCGE bit of CGCTL register */ 108 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 109 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 110 111 /* Update L1SEN bit of EM2 register */ 112 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 113 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 114 115 /* Update ADSPPGD bit of PGCTL register */ 116 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 117 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 118 } 119 120 /* 121 * While performing reset, controller may not come back properly causing 122 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 123 * (init chip) and then again set CGCTL.MISCBDCGE to 1 124 */ 125 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 126 { 127 struct hdac_ext_link *hlink; 128 int ret; 129 130 skl_enable_miscbdcge(bus->dev, false); 131 ret = snd_hdac_bus_init_chip(bus, full_reset); 132 133 /* Reset stream-to-link mapping */ 134 list_for_each_entry(hlink, &bus->hlink_list, list) 135 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 136 137 skl_enable_miscbdcge(bus->dev, true); 138 139 return ret; 140 } 141 142 void skl_update_d0i3c(struct device *dev, bool enable) 143 { 144 struct pci_dev *pci = to_pci_dev(dev); 145 struct hdac_bus *bus = pci_get_drvdata(pci); 146 u8 reg; 147 int timeout = 50; 148 149 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 150 /* Do not write to D0I3C until command in progress bit is cleared */ 151 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 152 udelay(10); 153 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 154 } 155 156 /* Highly unlikely. But if it happens, flag error explicitly */ 157 if (!timeout) { 158 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 159 return; 160 } 161 162 if (enable) 163 reg = reg | AZX_REG_VS_D0I3C_I3; 164 else 165 reg = reg & (~AZX_REG_VS_D0I3C_I3); 166 167 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 168 169 timeout = 50; 170 /* Wait for cmd in progress to be cleared before exiting the function */ 171 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 172 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 173 udelay(10); 174 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 175 } 176 177 /* Highly unlikely. But if it happens, flag error explicitly */ 178 if (!timeout) { 179 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 180 return; 181 } 182 183 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 184 snd_hdac_chip_readb(bus, VS_D0I3C)); 185 } 186 187 /* called from IRQ */ 188 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 189 { 190 snd_pcm_period_elapsed(hstr->substream); 191 } 192 193 static irqreturn_t skl_interrupt(int irq, void *dev_id) 194 { 195 struct hdac_bus *bus = dev_id; 196 u32 status; 197 198 if (!pm_runtime_active(bus->dev)) 199 return IRQ_NONE; 200 201 spin_lock(&bus->reg_lock); 202 203 status = snd_hdac_chip_readl(bus, INTSTS); 204 if (status == 0 || status == 0xffffffff) { 205 spin_unlock(&bus->reg_lock); 206 return IRQ_NONE; 207 } 208 209 /* clear rirb int */ 210 status = snd_hdac_chip_readb(bus, RIRBSTS); 211 if (status & RIRB_INT_MASK) { 212 if (status & RIRB_INT_RESPONSE) 213 snd_hdac_bus_update_rirb(bus); 214 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 215 } 216 217 spin_unlock(&bus->reg_lock); 218 219 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 220 } 221 222 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 223 { 224 struct hdac_bus *bus = dev_id; 225 u32 status; 226 227 status = snd_hdac_chip_readl(bus, INTSTS); 228 229 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 230 231 return IRQ_HANDLED; 232 } 233 234 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 235 { 236 struct skl *skl = bus_to_skl(bus); 237 int ret; 238 239 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 240 skl_threaded_handler, 241 IRQF_SHARED, 242 KBUILD_MODNAME, bus); 243 if (ret) { 244 dev_err(bus->dev, 245 "unable to grab IRQ %d, disabling device\n", 246 skl->pci->irq); 247 return ret; 248 } 249 250 bus->irq = skl->pci->irq; 251 pci_intx(skl->pci, 1); 252 253 return 0; 254 } 255 256 static int skl_suspend_late(struct device *dev) 257 { 258 struct pci_dev *pci = to_pci_dev(dev); 259 struct hdac_bus *bus = pci_get_drvdata(pci); 260 struct skl *skl = bus_to_skl(bus); 261 262 return skl_suspend_late_dsp(skl); 263 } 264 265 #ifdef CONFIG_PM 266 static int _skl_suspend(struct hdac_bus *bus) 267 { 268 struct skl *skl = bus_to_skl(bus); 269 struct pci_dev *pci = to_pci_dev(bus->dev); 270 int ret; 271 272 snd_hdac_ext_bus_link_power_down_all(bus); 273 274 ret = skl_suspend_dsp(skl); 275 if (ret < 0) 276 return ret; 277 278 snd_hdac_bus_stop_chip(bus); 279 update_pci_dword(pci, AZX_PCIREG_PGCTL, 280 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 281 skl_enable_miscbdcge(bus->dev, false); 282 snd_hdac_bus_enter_link_reset(bus); 283 skl_enable_miscbdcge(bus->dev, true); 284 skl_cleanup_resources(skl); 285 286 return 0; 287 } 288 289 static int _skl_resume(struct hdac_bus *bus) 290 { 291 struct skl *skl = bus_to_skl(bus); 292 293 skl_init_pci(skl); 294 skl_init_chip(bus, true); 295 296 return skl_resume_dsp(skl); 297 } 298 #endif 299 300 #ifdef CONFIG_PM_SLEEP 301 /* 302 * power management 303 */ 304 static int skl_suspend(struct device *dev) 305 { 306 struct pci_dev *pci = to_pci_dev(dev); 307 struct hdac_bus *bus = pci_get_drvdata(pci); 308 struct skl *skl = bus_to_skl(bus); 309 int ret; 310 311 /* 312 * Do not suspend if streams which are marked ignore suspend are 313 * running, we need to save the state for these and continue 314 */ 315 if (skl->supend_active) { 316 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 317 snd_hdac_ext_bus_link_power_down_all(bus); 318 319 if (bus->cmd_dma_state) 320 snd_hdac_bus_stop_cmd_io(bus); 321 322 enable_irq_wake(bus->irq); 323 pci_save_state(pci); 324 } else { 325 ret = _skl_suspend(bus); 326 if (ret < 0) 327 return ret; 328 skl->skl_sst->fw_loaded = false; 329 } 330 331 return 0; 332 } 333 334 static int skl_resume(struct device *dev) 335 { 336 struct pci_dev *pci = to_pci_dev(dev); 337 struct hdac_bus *bus = pci_get_drvdata(pci); 338 struct skl *skl = bus_to_skl(bus); 339 struct hdac_ext_link *hlink = NULL; 340 int ret; 341 342 /* 343 * resume only when we are not in suspend active, otherwise need to 344 * restore the device 345 */ 346 if (skl->supend_active) { 347 pci_restore_state(pci); 348 snd_hdac_ext_bus_link_power_up_all(bus); 349 disable_irq_wake(bus->irq); 350 /* 351 * turn On the links which are On before active suspend 352 * and start the CORB/RIRB DMA if On before 353 * active suspend. 354 */ 355 list_for_each_entry(hlink, &bus->hlink_list, list) { 356 if (hlink->ref_count) 357 snd_hdac_ext_bus_link_power_up(hlink); 358 } 359 360 ret = 0; 361 if (bus->cmd_dma_state) 362 snd_hdac_bus_init_cmd_io(bus); 363 } else { 364 ret = _skl_resume(bus); 365 366 /* turn off the links which are off before suspend */ 367 list_for_each_entry(hlink, &bus->hlink_list, list) { 368 if (!hlink->ref_count) 369 snd_hdac_ext_bus_link_power_down(hlink); 370 } 371 372 if (!bus->cmd_dma_state) 373 snd_hdac_bus_stop_cmd_io(bus); 374 } 375 376 return ret; 377 } 378 #endif /* CONFIG_PM_SLEEP */ 379 380 #ifdef CONFIG_PM 381 static int skl_runtime_suspend(struct device *dev) 382 { 383 struct pci_dev *pci = to_pci_dev(dev); 384 struct hdac_bus *bus = pci_get_drvdata(pci); 385 386 dev_dbg(bus->dev, "in %s\n", __func__); 387 388 return _skl_suspend(bus); 389 } 390 391 static int skl_runtime_resume(struct device *dev) 392 { 393 struct pci_dev *pci = to_pci_dev(dev); 394 struct hdac_bus *bus = pci_get_drvdata(pci); 395 396 dev_dbg(bus->dev, "in %s\n", __func__); 397 398 return _skl_resume(bus); 399 } 400 #endif /* CONFIG_PM */ 401 402 static const struct dev_pm_ops skl_pm = { 403 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 404 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 405 .suspend_late = skl_suspend_late, 406 }; 407 408 /* 409 * destructor 410 */ 411 static int skl_free(struct hdac_bus *bus) 412 { 413 struct skl *skl = bus_to_skl(bus); 414 415 skl->init_done = 0; /* to be sure */ 416 417 snd_hdac_ext_stop_streams(bus); 418 419 if (bus->irq >= 0) 420 free_irq(bus->irq, (void *)bus); 421 snd_hdac_bus_free_stream_pages(bus); 422 snd_hdac_stream_free_all(bus); 423 snd_hdac_link_free_all(bus); 424 425 if (bus->remap_addr) 426 iounmap(bus->remap_addr); 427 428 pci_release_regions(skl->pci); 429 pci_disable_device(skl->pci); 430 431 snd_hdac_ext_bus_exit(bus); 432 433 cancel_work_sync(&skl->probe_work); 434 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 435 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 436 snd_hdac_i915_exit(bus); 437 } 438 439 return 0; 440 } 441 442 /* 443 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 444 * e.g. for ssp0, clocks will be named as 445 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 446 * So for skl+, there are 6 ssps, so 18 clocks will be created. 447 */ 448 static struct skl_ssp_clk skl_ssp_clks[] = { 449 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 450 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 451 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 452 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 453 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 454 {.name = "ssp2_sclkfs"}, 455 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 456 {.name = "ssp5_sclkfs"}, 457 }; 458 459 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl *skl, 460 struct snd_soc_acpi_mach *machines) 461 { 462 struct hdac_bus *bus = skl_to_bus(skl); 463 struct snd_soc_acpi_mach *mach; 464 465 /* check if we have any codecs detected on bus */ 466 if (bus->codec_mask == 0) 467 return NULL; 468 469 /* point to common table */ 470 mach = snd_soc_acpi_intel_hda_machines; 471 472 /* all entries in the machine table use the same firmware */ 473 mach->fw_filename = machines->fw_filename; 474 475 return mach; 476 } 477 478 static int skl_find_machine(struct skl *skl, void *driver_data) 479 { 480 struct hdac_bus *bus = skl_to_bus(skl); 481 struct snd_soc_acpi_mach *mach = driver_data; 482 struct skl_machine_pdata *pdata; 483 484 mach = snd_soc_acpi_find_machine(mach); 485 if (!mach) { 486 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 487 mach = skl_find_hda_machine(skl, driver_data); 488 if (!mach) { 489 dev_err(bus->dev, "No matching machine driver found\n"); 490 return -ENODEV; 491 } 492 } 493 494 skl->mach = mach; 495 skl->fw_name = mach->fw_filename; 496 pdata = mach->pdata; 497 498 if (pdata) { 499 skl->use_tplg_pcm = pdata->use_tplg_pcm; 500 mach->mach_params.dmic_num = skl_get_dmic_geo(skl); 501 } 502 503 return 0; 504 } 505 506 static int skl_machine_device_register(struct skl *skl) 507 { 508 struct snd_soc_acpi_mach *mach = skl->mach; 509 struct hdac_bus *bus = skl_to_bus(skl); 510 struct platform_device *pdev; 511 int ret; 512 513 pdev = platform_device_alloc(mach->drv_name, -1); 514 if (pdev == NULL) { 515 dev_err(bus->dev, "platform device alloc failed\n"); 516 return -EIO; 517 } 518 519 mach->mach_params.platform = dev_name(bus->dev); 520 mach->mach_params.codec_mask = bus->codec_mask; 521 522 ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); 523 if (ret) { 524 dev_err(bus->dev, "failed to add machine device platform data\n"); 525 platform_device_put(pdev); 526 return ret; 527 } 528 529 ret = platform_device_add(pdev); 530 if (ret) { 531 dev_err(bus->dev, "failed to add machine device\n"); 532 platform_device_put(pdev); 533 return -EIO; 534 } 535 536 537 skl->i2s_dev = pdev; 538 539 return 0; 540 } 541 542 static void skl_machine_device_unregister(struct skl *skl) 543 { 544 if (skl->i2s_dev) 545 platform_device_unregister(skl->i2s_dev); 546 } 547 548 static int skl_dmic_device_register(struct skl *skl) 549 { 550 struct hdac_bus *bus = skl_to_bus(skl); 551 struct platform_device *pdev; 552 int ret; 553 554 /* SKL has one dmic port, so allocate dmic device for this */ 555 pdev = platform_device_alloc("dmic-codec", -1); 556 if (!pdev) { 557 dev_err(bus->dev, "failed to allocate dmic device\n"); 558 return -ENOMEM; 559 } 560 561 ret = platform_device_add(pdev); 562 if (ret) { 563 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 564 platform_device_put(pdev); 565 return ret; 566 } 567 skl->dmic_dev = pdev; 568 569 return 0; 570 } 571 572 static void skl_dmic_device_unregister(struct skl *skl) 573 { 574 if (skl->dmic_dev) 575 platform_device_unregister(skl->dmic_dev); 576 } 577 578 static struct skl_clk_parent_src skl_clk_src[] = { 579 { .clk_id = SKL_XTAL, .name = "xtal" }, 580 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 581 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 582 }; 583 584 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 585 { 586 unsigned int i; 587 588 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 589 if (skl_clk_src[i].clk_id == clk_id) 590 return &skl_clk_src[i]; 591 } 592 593 return NULL; 594 } 595 596 static void init_skl_xtal_rate(int pci_id) 597 { 598 switch (pci_id) { 599 case 0x9d70: 600 case 0x9d71: 601 skl_clk_src[0].rate = 24000000; 602 return; 603 604 default: 605 skl_clk_src[0].rate = 19200000; 606 return; 607 } 608 } 609 610 static int skl_clock_device_register(struct skl *skl) 611 { 612 struct platform_device_info pdevinfo = {NULL}; 613 struct skl_clk_pdata *clk_pdata; 614 615 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 616 GFP_KERNEL); 617 if (!clk_pdata) 618 return -ENOMEM; 619 620 init_skl_xtal_rate(skl->pci->device); 621 622 clk_pdata->parent_clks = skl_clk_src; 623 clk_pdata->ssp_clks = skl_ssp_clks; 624 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 625 626 /* Query NHLT to fill the rates and parent */ 627 skl_get_clks(skl, clk_pdata->ssp_clks); 628 clk_pdata->pvt_data = skl; 629 630 /* Register Platform device */ 631 pdevinfo.parent = &skl->pci->dev; 632 pdevinfo.id = -1; 633 pdevinfo.name = "skl-ssp-clk"; 634 pdevinfo.data = clk_pdata; 635 pdevinfo.size_data = sizeof(*clk_pdata); 636 skl->clk_dev = platform_device_register_full(&pdevinfo); 637 return PTR_ERR_OR_ZERO(skl->clk_dev); 638 } 639 640 static void skl_clock_device_unregister(struct skl *skl) 641 { 642 if (skl->clk_dev) 643 platform_device_unregister(skl->clk_dev); 644 } 645 646 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 647 648 #define IDISP_INTEL_VENDOR_ID 0x80860000 649 650 /* 651 * load the legacy codec driver 652 */ 653 static void load_codec_module(struct hda_codec *codec) 654 { 655 #ifdef MODULE 656 char modalias[MODULE_NAME_LEN]; 657 const char *mod = NULL; 658 659 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 660 mod = modalias; 661 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 662 request_module(mod); 663 #endif 664 } 665 666 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 667 668 /* 669 * Probe the given codec address 670 */ 671 static int probe_codec(struct hdac_bus *bus, int addr) 672 { 673 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 674 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 675 unsigned int res = -1; 676 struct skl *skl = bus_to_skl(bus); 677 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 678 struct hdac_hda_priv *hda_codec; 679 int err; 680 #endif 681 struct hdac_device *hdev; 682 683 mutex_lock(&bus->cmd_mutex); 684 snd_hdac_bus_send_cmd(bus, cmd); 685 snd_hdac_bus_get_response(bus, addr, &res); 686 mutex_unlock(&bus->cmd_mutex); 687 if (res == -1) 688 return -EIO; 689 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 690 691 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 692 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 693 GFP_KERNEL); 694 if (!hda_codec) 695 return -ENOMEM; 696 697 hda_codec->codec.bus = skl_to_hbus(skl); 698 hdev = &hda_codec->codec.core; 699 700 err = snd_hdac_ext_bus_device_init(bus, addr, hdev); 701 if (err < 0) 702 return err; 703 704 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 705 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 706 hdev->type = HDA_DEV_LEGACY; 707 load_codec_module(&hda_codec->codec); 708 } 709 return 0; 710 #else 711 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); 712 if (!hdev) 713 return -ENOMEM; 714 715 return snd_hdac_ext_bus_device_init(bus, addr, hdev); 716 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 717 } 718 719 /* Codec initialization */ 720 static void skl_codec_create(struct hdac_bus *bus) 721 { 722 int c, max_slots; 723 724 max_slots = HDA_MAX_CODECS; 725 726 /* First try to probe all given codec slots */ 727 for (c = 0; c < max_slots; c++) { 728 if ((bus->codec_mask & (1 << c))) { 729 if (probe_codec(bus, c) < 0) { 730 /* 731 * Some BIOSen give you wrong codec addresses 732 * that don't exist 733 */ 734 dev_warn(bus->dev, 735 "Codec #%d probe error; disabling it...\n", c); 736 bus->codec_mask &= ~(1 << c); 737 /* 738 * More badly, accessing to a non-existing 739 * codec often screws up the controller bus, 740 * and disturbs the further communications. 741 * Thus if an error occurs during probing, 742 * better to reset the controller bus to get 743 * back to the sanity state. 744 */ 745 snd_hdac_bus_stop_chip(bus); 746 skl_init_chip(bus, true); 747 } 748 } 749 } 750 } 751 752 static const struct hdac_bus_ops bus_core_ops = { 753 .command = snd_hdac_bus_send_cmd, 754 .get_response = snd_hdac_bus_get_response, 755 }; 756 757 static int skl_i915_init(struct hdac_bus *bus) 758 { 759 int err; 760 761 /* 762 * The HDMI codec is in GPU so we need to ensure that it is powered 763 * up and ready for probe 764 */ 765 err = snd_hdac_i915_init(bus); 766 if (err < 0) 767 return err; 768 769 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 770 771 return 0; 772 } 773 774 static void skl_probe_work(struct work_struct *work) 775 { 776 struct skl *skl = container_of(work, struct skl, probe_work); 777 struct hdac_bus *bus = skl_to_bus(skl); 778 struct hdac_ext_link *hlink = NULL; 779 int err; 780 781 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 782 err = skl_i915_init(bus); 783 if (err < 0) 784 return; 785 } 786 787 err = skl_init_chip(bus, true); 788 if (err < 0) { 789 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 790 goto out_err; 791 } 792 793 /* codec detection */ 794 if (!bus->codec_mask) 795 dev_info(bus->dev, "no hda codecs found!\n"); 796 797 /* create codec instances */ 798 skl_codec_create(bus); 799 800 /* register platform dai and controls */ 801 err = skl_platform_register(bus->dev); 802 if (err < 0) { 803 dev_err(bus->dev, "platform register failed: %d\n", err); 804 goto out_err; 805 } 806 807 err = skl_machine_device_register(skl); 808 if (err < 0) { 809 dev_err(bus->dev, "machine register failed: %d\n", err); 810 goto out_err; 811 } 812 813 /* 814 * we are done probing so decrement link counts 815 */ 816 list_for_each_entry(hlink, &bus->hlink_list, list) 817 snd_hdac_ext_bus_link_put(bus, hlink); 818 819 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 820 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 821 822 /* configure PM */ 823 pm_runtime_put_noidle(bus->dev); 824 pm_runtime_allow(bus->dev); 825 skl->init_done = 1; 826 827 return; 828 829 out_err: 830 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 831 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 832 } 833 834 /* 835 * constructor 836 */ 837 static int skl_create(struct pci_dev *pci, 838 const struct hdac_io_ops *io_ops, 839 struct skl **rskl) 840 { 841 struct hdac_ext_bus_ops *ext_ops = NULL; 842 struct skl *skl; 843 struct hdac_bus *bus; 844 struct hda_bus *hbus; 845 int err; 846 847 *rskl = NULL; 848 849 err = pci_enable_device(pci); 850 if (err < 0) 851 return err; 852 853 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 854 if (!skl) { 855 pci_disable_device(pci); 856 return -ENOMEM; 857 } 858 859 hbus = skl_to_hbus(skl); 860 bus = skl_to_bus(skl); 861 862 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 863 ext_ops = snd_soc_hdac_hda_get_ops(); 864 #endif 865 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, ext_ops); 866 bus->use_posbuf = 1; 867 skl->pci = pci; 868 INIT_WORK(&skl->probe_work, skl_probe_work); 869 bus->bdl_pos_adj = 0; 870 871 mutex_init(&hbus->prepare_mutex); 872 hbus->pci = pci; 873 hbus->mixer_assigned = -1; 874 hbus->modelname = "sklbus"; 875 876 *rskl = skl; 877 878 return 0; 879 } 880 881 static int skl_first_init(struct hdac_bus *bus) 882 { 883 struct skl *skl = bus_to_skl(bus); 884 struct pci_dev *pci = skl->pci; 885 int err; 886 unsigned short gcap; 887 int cp_streams, pb_streams, start_idx; 888 889 err = pci_request_regions(pci, "Skylake HD audio"); 890 if (err < 0) 891 return err; 892 893 bus->addr = pci_resource_start(pci, 0); 894 bus->remap_addr = pci_ioremap_bar(pci, 0); 895 if (bus->remap_addr == NULL) { 896 dev_err(bus->dev, "ioremap error\n"); 897 return -ENXIO; 898 } 899 900 snd_hdac_bus_reset_link(bus, true); 901 902 snd_hdac_bus_parse_capabilities(bus); 903 904 /* check if PPCAP exists */ 905 if (!bus->ppcap) { 906 dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n"); 907 return -ENODEV; 908 } 909 910 if (skl_acquire_irq(bus, 0) < 0) 911 return -EBUSY; 912 913 pci_set_master(pci); 914 synchronize_irq(bus->irq); 915 916 gcap = snd_hdac_chip_readw(bus, GCAP); 917 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 918 919 /* read number of streams from GCAP register */ 920 cp_streams = (gcap >> 8) & 0x0f; 921 pb_streams = (gcap >> 12) & 0x0f; 922 923 if (!pb_streams && !cp_streams) { 924 dev_err(bus->dev, "no streams found in GCAP definitions?\n"); 925 return -EIO; 926 } 927 928 bus->num_streams = cp_streams + pb_streams; 929 930 /* allow 64bit DMA address if supported by H/W */ 931 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 932 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 933 } else { 934 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 935 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 936 } 937 938 /* initialize streams */ 939 snd_hdac_ext_stream_init_all 940 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 941 start_idx = cp_streams; 942 snd_hdac_ext_stream_init_all 943 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 944 945 err = snd_hdac_bus_alloc_stream_pages(bus); 946 if (err < 0) 947 return err; 948 949 /* initialize chip */ 950 skl_init_pci(skl); 951 952 return skl_init_chip(bus, true); 953 } 954 955 static int skl_probe(struct pci_dev *pci, 956 const struct pci_device_id *pci_id) 957 { 958 struct skl *skl; 959 struct hdac_bus *bus = NULL; 960 int err; 961 962 switch (skl_pci_binding) { 963 case SND_SKL_PCI_BIND_AUTO: 964 /* 965 * detect DSP by checking class/subclass/prog-id information 966 * class=04 subclass 03 prog-if 00: no DSP, use legacy driver 967 * class=04 subclass 01 prog-if 00: DSP is present 968 * (and may be required e.g. for DMIC or SSP support) 969 * class=04 subclass 03 prog-if 80: use DSP or legacy mode 970 */ 971 if (pci->class == 0x040300) { 972 dev_info(&pci->dev, "The DSP is not enabled on this platform, aborting probe\n"); 973 return -ENODEV; 974 } 975 if (pci->class != 0x040100 && pci->class != 0x040380) { 976 dev_err(&pci->dev, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci->class); 977 return -ENODEV; 978 } 979 dev_info(&pci->dev, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci->class); 980 break; 981 case SND_SKL_PCI_BIND_LEGACY: 982 dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n"); 983 return -ENODEV; 984 case SND_SKL_PCI_BIND_ASOC: 985 dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); 986 break; 987 default: 988 dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); 989 break; 990 } 991 992 /* we use ext core ops, so provide NULL for ops here */ 993 err = skl_create(pci, NULL, &skl); 994 if (err < 0) 995 return err; 996 997 bus = skl_to_bus(skl); 998 999 err = skl_first_init(bus); 1000 if (err < 0) { 1001 dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); 1002 goto out_free; 1003 } 1004 1005 skl->pci_id = pci->device; 1006 1007 device_disable_async_suspend(bus->dev); 1008 1009 skl->nhlt = skl_nhlt_init(bus->dev); 1010 1011 if (skl->nhlt == NULL) { 1012 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 1013 dev_err(bus->dev, "no nhlt info found\n"); 1014 err = -ENODEV; 1015 goto out_free; 1016 #else 1017 dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n"); 1018 #endif 1019 } else { 1020 1021 err = skl_nhlt_create_sysfs(skl); 1022 if (err < 0) { 1023 dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); 1024 goto out_nhlt_free; 1025 } 1026 1027 skl_nhlt_update_topology_bin(skl); 1028 1029 /* create device for dsp clk */ 1030 err = skl_clock_device_register(skl); 1031 if (err < 0) { 1032 dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); 1033 goto out_clk_free; 1034 } 1035 } 1036 1037 pci_set_drvdata(skl->pci, bus); 1038 1039 1040 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1041 if (err < 0) { 1042 dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); 1043 goto out_nhlt_free; 1044 } 1045 1046 err = skl_init_dsp(skl); 1047 if (err < 0) { 1048 dev_dbg(bus->dev, "error failed to register dsp\n"); 1049 goto out_nhlt_free; 1050 } 1051 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 1052 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 1053 1054 if (bus->mlcap) 1055 snd_hdac_ext_bus_get_ml_capabilities(bus); 1056 1057 snd_hdac_bus_stop_chip(bus); 1058 1059 /* create device for soc dmic */ 1060 err = skl_dmic_device_register(skl); 1061 if (err < 0) { 1062 dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); 1063 goto out_dsp_free; 1064 } 1065 1066 schedule_work(&skl->probe_work); 1067 1068 return 0; 1069 1070 out_dsp_free: 1071 skl_free_dsp(skl); 1072 out_clk_free: 1073 skl_clock_device_unregister(skl); 1074 out_nhlt_free: 1075 skl_nhlt_free(skl->nhlt); 1076 out_free: 1077 skl_free(bus); 1078 1079 return err; 1080 } 1081 1082 static void skl_shutdown(struct pci_dev *pci) 1083 { 1084 struct hdac_bus *bus = pci_get_drvdata(pci); 1085 struct hdac_stream *s; 1086 struct hdac_ext_stream *stream; 1087 struct skl *skl; 1088 1089 if (!bus) 1090 return; 1091 1092 skl = bus_to_skl(bus); 1093 1094 if (!skl->init_done) 1095 return; 1096 1097 snd_hdac_ext_stop_streams(bus); 1098 list_for_each_entry(s, &bus->stream_list, list) { 1099 stream = stream_to_hdac_ext_stream(s); 1100 snd_hdac_ext_stream_decouple(bus, stream, false); 1101 } 1102 1103 snd_hdac_bus_stop_chip(bus); 1104 } 1105 1106 static void skl_remove(struct pci_dev *pci) 1107 { 1108 struct hdac_bus *bus = pci_get_drvdata(pci); 1109 struct skl *skl = bus_to_skl(bus); 1110 1111 release_firmware(skl->tplg); 1112 1113 pm_runtime_get_noresume(&pci->dev); 1114 1115 /* codec removal, invoke bus_device_remove */ 1116 snd_hdac_ext_bus_device_remove(bus); 1117 1118 skl->debugfs = NULL; 1119 skl_platform_unregister(&pci->dev); 1120 skl_free_dsp(skl); 1121 skl_machine_device_unregister(skl); 1122 skl_dmic_device_unregister(skl); 1123 skl_clock_device_unregister(skl); 1124 skl_nhlt_remove_sysfs(skl); 1125 skl_nhlt_free(skl->nhlt); 1126 skl_free(bus); 1127 dev_set_drvdata(&pci->dev, NULL); 1128 } 1129 1130 /* PCI IDs */ 1131 static const struct pci_device_id skl_ids[] = { 1132 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) 1133 /* Sunrise Point-LP */ 1134 { PCI_DEVICE(0x8086, 0x9d70), 1135 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1136 #endif 1137 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) 1138 /* BXT-P */ 1139 { PCI_DEVICE(0x8086, 0x5a98), 1140 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1141 #endif 1142 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) 1143 /* KBL */ 1144 { PCI_DEVICE(0x8086, 0x9D71), 1145 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1146 #endif 1147 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) 1148 /* GLK */ 1149 { PCI_DEVICE(0x8086, 0x3198), 1150 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1151 #endif 1152 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) 1153 /* CNL */ 1154 { PCI_DEVICE(0x8086, 0x9dc8), 1155 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1156 #endif 1157 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) 1158 /* CFL */ 1159 { PCI_DEVICE(0x8086, 0xa348), 1160 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1161 #endif 1162 { 0, } 1163 }; 1164 MODULE_DEVICE_TABLE(pci, skl_ids); 1165 1166 /* pci_driver definition */ 1167 static struct pci_driver skl_driver = { 1168 .name = KBUILD_MODNAME, 1169 .id_table = skl_ids, 1170 .probe = skl_probe, 1171 .remove = skl_remove, 1172 .shutdown = skl_shutdown, 1173 .driver = { 1174 .pm = &skl_pm, 1175 }, 1176 }; 1177 module_pci_driver(skl_driver); 1178 1179 MODULE_LICENSE("GPL v2"); 1180 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1181