1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Mediatek ALSA SoC AFE platform driver for 8183 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/pm_runtime.h> 14 15 #include "mt8183-afe-common.h" 16 #include "mt8183-afe-clk.h" 17 #include "mt8183-interconnection.h" 18 #include "mt8183-reg.h" 19 #include "../common/mtk-afe-platform-driver.h" 20 #include "../common/mtk-afe-fe-dai.h" 21 22 enum { 23 MTK_AFE_RATE_8K = 0, 24 MTK_AFE_RATE_11K = 1, 25 MTK_AFE_RATE_12K = 2, 26 MTK_AFE_RATE_384K = 3, 27 MTK_AFE_RATE_16K = 4, 28 MTK_AFE_RATE_22K = 5, 29 MTK_AFE_RATE_24K = 6, 30 MTK_AFE_RATE_130K = 7, 31 MTK_AFE_RATE_32K = 8, 32 MTK_AFE_RATE_44K = 9, 33 MTK_AFE_RATE_48K = 10, 34 MTK_AFE_RATE_88K = 11, 35 MTK_AFE_RATE_96K = 12, 36 MTK_AFE_RATE_176K = 13, 37 MTK_AFE_RATE_192K = 14, 38 MTK_AFE_RATE_260K = 15, 39 }; 40 41 enum { 42 MTK_AFE_DAI_MEMIF_RATE_8K = 0, 43 MTK_AFE_DAI_MEMIF_RATE_16K = 1, 44 MTK_AFE_DAI_MEMIF_RATE_32K = 2, 45 MTK_AFE_DAI_MEMIF_RATE_48K = 3, 46 }; 47 48 enum { 49 MTK_AFE_PCM_RATE_8K = 0, 50 MTK_AFE_PCM_RATE_16K = 1, 51 MTK_AFE_PCM_RATE_32K = 2, 52 MTK_AFE_PCM_RATE_48K = 3, 53 }; 54 55 unsigned int mt8183_general_rate_transform(struct device *dev, 56 unsigned int rate) 57 { 58 switch (rate) { 59 case 8000: 60 return MTK_AFE_RATE_8K; 61 case 11025: 62 return MTK_AFE_RATE_11K; 63 case 12000: 64 return MTK_AFE_RATE_12K; 65 case 16000: 66 return MTK_AFE_RATE_16K; 67 case 22050: 68 return MTK_AFE_RATE_22K; 69 case 24000: 70 return MTK_AFE_RATE_24K; 71 case 32000: 72 return MTK_AFE_RATE_32K; 73 case 44100: 74 return MTK_AFE_RATE_44K; 75 case 48000: 76 return MTK_AFE_RATE_48K; 77 case 88200: 78 return MTK_AFE_RATE_88K; 79 case 96000: 80 return MTK_AFE_RATE_96K; 81 case 130000: 82 return MTK_AFE_RATE_130K; 83 case 176400: 84 return MTK_AFE_RATE_176K; 85 case 192000: 86 return MTK_AFE_RATE_192K; 87 case 260000: 88 return MTK_AFE_RATE_260K; 89 default: 90 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 91 __func__, rate, MTK_AFE_RATE_48K); 92 return MTK_AFE_RATE_48K; 93 } 94 } 95 96 static unsigned int dai_memif_rate_transform(struct device *dev, 97 unsigned int rate) 98 { 99 switch (rate) { 100 case 8000: 101 return MTK_AFE_DAI_MEMIF_RATE_8K; 102 case 16000: 103 return MTK_AFE_DAI_MEMIF_RATE_16K; 104 case 32000: 105 return MTK_AFE_DAI_MEMIF_RATE_32K; 106 case 48000: 107 return MTK_AFE_DAI_MEMIF_RATE_48K; 108 default: 109 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 110 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K); 111 return MTK_AFE_DAI_MEMIF_RATE_16K; 112 } 113 } 114 115 unsigned int mt8183_rate_transform(struct device *dev, 116 unsigned int rate, int aud_blk) 117 { 118 switch (aud_blk) { 119 case MT8183_MEMIF_MOD_DAI: 120 return dai_memif_rate_transform(dev, rate); 121 default: 122 return mt8183_general_rate_transform(dev, rate); 123 } 124 } 125 126 static const struct snd_pcm_hardware mt8183_afe_hardware = { 127 .info = SNDRV_PCM_INFO_MMAP | 128 SNDRV_PCM_INFO_INTERLEAVED | 129 SNDRV_PCM_INFO_MMAP_VALID, 130 .formats = SNDRV_PCM_FMTBIT_S16_LE | 131 SNDRV_PCM_FMTBIT_S24_LE | 132 SNDRV_PCM_FMTBIT_S32_LE, 133 .period_bytes_min = 256, 134 .period_bytes_max = 4 * 48 * 1024, 135 .periods_min = 2, 136 .periods_max = 256, 137 .buffer_bytes_max = 8 * 48 * 1024, 138 .fifo_size = 0, 139 }; 140 141 static int mt8183_memif_fs(struct snd_pcm_substream *substream, 142 unsigned int rate) 143 { 144 struct snd_soc_pcm_runtime *rtd = substream->private_data; 145 struct snd_soc_component *component = 146 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 148 int id = rtd->cpu_dai->id; 149 150 return mt8183_rate_transform(afe->dev, rate, id); 151 } 152 153 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 154 { 155 struct snd_soc_pcm_runtime *rtd = substream->private_data; 156 struct snd_soc_component *component = 157 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 158 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 159 160 return mt8183_general_rate_transform(afe->dev, rate); 161 } 162 163 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 164 SNDRV_PCM_RATE_88200 |\ 165 SNDRV_PCM_RATE_96000 |\ 166 SNDRV_PCM_RATE_176400 |\ 167 SNDRV_PCM_RATE_192000) 168 169 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 170 SNDRV_PCM_RATE_16000 |\ 171 SNDRV_PCM_RATE_32000 |\ 172 SNDRV_PCM_RATE_48000) 173 174 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 175 SNDRV_PCM_FMTBIT_S24_LE |\ 176 SNDRV_PCM_FMTBIT_S32_LE) 177 178 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = { 179 /* FE DAIs: memory intefaces to CPU */ 180 { 181 .name = "DL1", 182 .id = MT8183_MEMIF_DL1, 183 .playback = { 184 .stream_name = "DL1", 185 .channels_min = 1, 186 .channels_max = 2, 187 .rates = MTK_PCM_RATES, 188 .formats = MTK_PCM_FORMATS, 189 }, 190 .ops = &mtk_afe_fe_ops, 191 }, 192 { 193 .name = "DL2", 194 .id = MT8183_MEMIF_DL2, 195 .playback = { 196 .stream_name = "DL2", 197 .channels_min = 1, 198 .channels_max = 2, 199 .rates = MTK_PCM_RATES, 200 .formats = MTK_PCM_FORMATS, 201 }, 202 .ops = &mtk_afe_fe_ops, 203 }, 204 { 205 .name = "DL3", 206 .id = MT8183_MEMIF_DL3, 207 .playback = { 208 .stream_name = "DL3", 209 .channels_min = 1, 210 .channels_max = 2, 211 .rates = MTK_PCM_RATES, 212 .formats = MTK_PCM_FORMATS, 213 }, 214 .ops = &mtk_afe_fe_ops, 215 }, 216 { 217 .name = "UL1", 218 .id = MT8183_MEMIF_VUL12, 219 .capture = { 220 .stream_name = "UL1", 221 .channels_min = 1, 222 .channels_max = 2, 223 .rates = MTK_PCM_RATES, 224 .formats = MTK_PCM_FORMATS, 225 }, 226 .ops = &mtk_afe_fe_ops, 227 }, 228 { 229 .name = "UL2", 230 .id = MT8183_MEMIF_AWB, 231 .capture = { 232 .stream_name = "UL2", 233 .channels_min = 1, 234 .channels_max = 2, 235 .rates = MTK_PCM_RATES, 236 .formats = MTK_PCM_FORMATS, 237 }, 238 .ops = &mtk_afe_fe_ops, 239 }, 240 { 241 .name = "UL3", 242 .id = MT8183_MEMIF_VUL2, 243 .capture = { 244 .stream_name = "UL3", 245 .channels_min = 1, 246 .channels_max = 2, 247 .rates = MTK_PCM_RATES, 248 .formats = MTK_PCM_FORMATS, 249 }, 250 .ops = &mtk_afe_fe_ops, 251 }, 252 { 253 .name = "UL4", 254 .id = MT8183_MEMIF_AWB2, 255 .capture = { 256 .stream_name = "UL4", 257 .channels_min = 1, 258 .channels_max = 2, 259 .rates = MTK_PCM_RATES, 260 .formats = MTK_PCM_FORMATS, 261 }, 262 .ops = &mtk_afe_fe_ops, 263 }, 264 { 265 .name = "UL_MONO_1", 266 .id = MT8183_MEMIF_MOD_DAI, 267 .capture = { 268 .stream_name = "UL_MONO_1", 269 .channels_min = 1, 270 .channels_max = 1, 271 .rates = MTK_PCM_DAI_RATES, 272 .formats = MTK_PCM_FORMATS, 273 }, 274 .ops = &mtk_afe_fe_ops, 275 }, 276 { 277 .name = "HDMI", 278 .id = MT8183_MEMIF_HDMI, 279 .playback = { 280 .stream_name = "HDMI", 281 .channels_min = 2, 282 .channels_max = 8, 283 .rates = MTK_PCM_RATES, 284 .formats = MTK_PCM_FORMATS, 285 }, 286 .ops = &mtk_afe_fe_ops, 287 }, 288 }; 289 290 /* dma widget & routes*/ 291 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 292 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21, 293 I_ADDA_UL_CH1, 1, 0), 294 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21, 295 I_I2S0_CH1, 1, 0), 296 }; 297 298 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 299 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22, 300 I_ADDA_UL_CH2, 1, 0), 301 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21, 302 I_I2S0_CH2, 1, 0), 303 }; 304 305 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 306 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5, 307 I_ADDA_UL_CH1, 1, 0), 308 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5, 309 I_DL1_CH1, 1, 0), 310 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5, 311 I_DL2_CH1, 1, 0), 312 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5, 313 I_DL3_CH1, 1, 0), 314 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5, 315 I_I2S2_CH1, 1, 0), 316 }; 317 318 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 319 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6, 320 I_ADDA_UL_CH2, 1, 0), 321 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6, 322 I_DL1_CH2, 1, 0), 323 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6, 324 I_DL2_CH2, 1, 0), 325 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6, 326 I_DL3_CH2, 1, 0), 327 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6, 328 I_I2S2_CH2, 1, 0), 329 }; 330 331 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 332 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32, 333 I_ADDA_UL_CH1, 1, 0), 334 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32, 335 I_I2S2_CH1, 1, 0), 336 }; 337 338 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 339 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33, 340 I_ADDA_UL_CH2, 1, 0), 341 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33, 342 I_I2S2_CH2, 1, 0), 343 }; 344 345 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { 346 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38, 347 I_ADDA_UL_CH1, 1, 0), 348 }; 349 350 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { 351 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39, 352 I_ADDA_UL_CH2, 1, 0), 353 }; 354 355 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = { 356 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12, 357 I_ADDA_UL_CH1, 1, 0), 358 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12, 359 I_ADDA_UL_CH2, 1, 0), 360 }; 361 362 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = { 363 /* memif */ 364 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 365 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 366 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 367 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 368 369 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 370 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 371 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 372 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 373 374 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 375 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 376 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 377 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 378 379 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, 380 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), 381 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, 382 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), 383 384 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0, 385 memif_ul_mono_1_mix, 386 ARRAY_SIZE(memif_ul_mono_1_mix)), 387 }; 388 389 static const struct snd_soc_dapm_route mt8183_memif_routes[] = { 390 /* capture */ 391 {"UL1", NULL, "UL1_CH1"}, 392 {"UL1", NULL, "UL1_CH2"}, 393 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 394 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 395 {"UL1_CH1", "I2S0_CH1", "I2S0"}, 396 {"UL1_CH2", "I2S0_CH2", "I2S0"}, 397 398 {"UL2", NULL, "UL2_CH1"}, 399 {"UL2", NULL, "UL2_CH2"}, 400 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 401 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 402 {"UL2_CH1", "I2S2_CH1", "I2S2"}, 403 {"UL2_CH2", "I2S2_CH2", "I2S2"}, 404 405 {"UL3", NULL, "UL3_CH1"}, 406 {"UL3", NULL, "UL3_CH2"}, 407 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 408 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 409 {"UL3_CH1", "I2S2_CH1", "I2S2"}, 410 {"UL3_CH2", "I2S2_CH2", "I2S2"}, 411 412 {"UL4", NULL, "UL4_CH1"}, 413 {"UL4", NULL, "UL4_CH2"}, 414 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 415 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 416 417 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"}, 418 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 419 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"}, 420 }; 421 422 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = { 423 .name = "mt8183-afe-pcm-dai", 424 }; 425 426 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { 427 [MT8183_MEMIF_DL1] = { 428 .name = "DL1", 429 .id = MT8183_MEMIF_DL1, 430 .reg_ofs_base = AFE_DL1_BASE, 431 .reg_ofs_cur = AFE_DL1_CUR, 432 .fs_reg = AFE_DAC_CON1, 433 .fs_shift = DL1_MODE_SFT, 434 .fs_maskbit = DL1_MODE_MASK, 435 .mono_reg = AFE_DAC_CON1, 436 .mono_shift = DL1_DATA_SFT, 437 .enable_reg = AFE_DAC_CON0, 438 .enable_shift = DL1_ON_SFT, 439 .hd_reg = AFE_MEMIF_HD_MODE, 440 .hd_shift = DL1_HD_SFT, 441 .agent_disable_reg = -1, 442 .agent_disable_shift = -1, 443 .msb_reg = -1, 444 .msb_shift = -1, 445 }, 446 [MT8183_MEMIF_DL2] = { 447 .name = "DL2", 448 .id = MT8183_MEMIF_DL2, 449 .reg_ofs_base = AFE_DL2_BASE, 450 .reg_ofs_cur = AFE_DL2_CUR, 451 .fs_reg = AFE_DAC_CON1, 452 .fs_shift = DL2_MODE_SFT, 453 .fs_maskbit = DL2_MODE_MASK, 454 .mono_reg = AFE_DAC_CON1, 455 .mono_shift = DL2_DATA_SFT, 456 .enable_reg = AFE_DAC_CON0, 457 .enable_shift = DL2_ON_SFT, 458 .hd_reg = AFE_MEMIF_HD_MODE, 459 .hd_shift = DL2_HD_SFT, 460 .agent_disable_reg = -1, 461 .agent_disable_shift = -1, 462 .msb_reg = -1, 463 .msb_shift = -1, 464 }, 465 [MT8183_MEMIF_DL3] = { 466 .name = "DL3", 467 .id = MT8183_MEMIF_DL3, 468 .reg_ofs_base = AFE_DL3_BASE, 469 .reg_ofs_cur = AFE_DL3_CUR, 470 .fs_reg = AFE_DAC_CON2, 471 .fs_shift = DL3_MODE_SFT, 472 .fs_maskbit = DL3_MODE_MASK, 473 .mono_reg = AFE_DAC_CON1, 474 .mono_shift = DL3_DATA_SFT, 475 .enable_reg = AFE_DAC_CON0, 476 .enable_shift = DL3_ON_SFT, 477 .hd_reg = AFE_MEMIF_HD_MODE, 478 .hd_shift = DL3_HD_SFT, 479 .agent_disable_reg = -1, 480 .agent_disable_shift = -1, 481 .msb_reg = -1, 482 .msb_shift = -1, 483 }, 484 [MT8183_MEMIF_VUL2] = { 485 .name = "VUL2", 486 .id = MT8183_MEMIF_VUL2, 487 .reg_ofs_base = AFE_VUL2_BASE, 488 .reg_ofs_cur = AFE_VUL2_CUR, 489 .fs_reg = AFE_DAC_CON2, 490 .fs_shift = VUL2_MODE_SFT, 491 .fs_maskbit = VUL2_MODE_MASK, 492 .mono_reg = AFE_DAC_CON2, 493 .mono_shift = VUL2_DATA_SFT, 494 .enable_reg = AFE_DAC_CON0, 495 .enable_shift = VUL2_ON_SFT, 496 .hd_reg = AFE_MEMIF_HD_MODE, 497 .hd_shift = VUL2_HD_SFT, 498 .agent_disable_reg = -1, 499 .agent_disable_shift = -1, 500 .msb_reg = -1, 501 .msb_shift = -1, 502 }, 503 [MT8183_MEMIF_AWB] = { 504 .name = "AWB", 505 .id = MT8183_MEMIF_AWB, 506 .reg_ofs_base = AFE_AWB_BASE, 507 .reg_ofs_cur = AFE_AWB_CUR, 508 .fs_reg = AFE_DAC_CON1, 509 .fs_shift = AWB_MODE_SFT, 510 .fs_maskbit = AWB_MODE_MASK, 511 .mono_reg = AFE_DAC_CON1, 512 .mono_shift = AWB_DATA_SFT, 513 .enable_reg = AFE_DAC_CON0, 514 .enable_shift = AWB_ON_SFT, 515 .hd_reg = AFE_MEMIF_HD_MODE, 516 .hd_shift = AWB_HD_SFT, 517 .agent_disable_reg = -1, 518 .agent_disable_shift = -1, 519 .msb_reg = -1, 520 .msb_shift = -1, 521 }, 522 [MT8183_MEMIF_AWB2] = { 523 .name = "AWB2", 524 .id = MT8183_MEMIF_AWB2, 525 .reg_ofs_base = AFE_AWB2_BASE, 526 .reg_ofs_cur = AFE_AWB2_CUR, 527 .fs_reg = AFE_DAC_CON2, 528 .fs_shift = AWB2_MODE_SFT, 529 .fs_maskbit = AWB2_MODE_MASK, 530 .mono_reg = AFE_DAC_CON2, 531 .mono_shift = AWB2_DATA_SFT, 532 .enable_reg = AFE_DAC_CON0, 533 .enable_shift = AWB2_ON_SFT, 534 .hd_reg = AFE_MEMIF_HD_MODE, 535 .hd_shift = AWB2_HD_SFT, 536 .agent_disable_reg = -1, 537 .agent_disable_shift = -1, 538 .msb_reg = -1, 539 .msb_shift = -1, 540 }, 541 [MT8183_MEMIF_VUL12] = { 542 .name = "VUL12", 543 .id = MT8183_MEMIF_VUL12, 544 .reg_ofs_base = AFE_VUL_D2_BASE, 545 .reg_ofs_cur = AFE_VUL_D2_CUR, 546 .fs_reg = AFE_DAC_CON0, 547 .fs_shift = VUL12_MODE_SFT, 548 .fs_maskbit = VUL12_MODE_MASK, 549 .mono_reg = AFE_DAC_CON0, 550 .mono_shift = VUL12_MONO_SFT, 551 .enable_reg = AFE_DAC_CON0, 552 .enable_shift = VUL12_ON_SFT, 553 .hd_reg = AFE_MEMIF_HD_MODE, 554 .hd_shift = VUL12_HD_SFT, 555 .agent_disable_reg = -1, 556 .agent_disable_shift = -1, 557 .msb_reg = -1, 558 .msb_shift = -1, 559 }, 560 [MT8183_MEMIF_MOD_DAI] = { 561 .name = "MOD_DAI", 562 .id = MT8183_MEMIF_MOD_DAI, 563 .reg_ofs_base = AFE_MOD_DAI_BASE, 564 .reg_ofs_cur = AFE_MOD_DAI_CUR, 565 .fs_reg = AFE_DAC_CON1, 566 .fs_shift = MOD_DAI_MODE_SFT, 567 .fs_maskbit = MOD_DAI_MODE_MASK, 568 .mono_reg = -1, 569 .mono_shift = 0, 570 .enable_reg = AFE_DAC_CON0, 571 .enable_shift = MOD_DAI_ON_SFT, 572 .hd_reg = AFE_MEMIF_HD_MODE, 573 .hd_shift = MOD_DAI_HD_SFT, 574 .agent_disable_reg = -1, 575 .agent_disable_shift = -1, 576 .msb_reg = -1, 577 .msb_shift = -1, 578 }, 579 [MT8183_MEMIF_HDMI] = { 580 .name = "HDMI", 581 .id = MT8183_MEMIF_HDMI, 582 .reg_ofs_base = AFE_HDMI_OUT_BASE, 583 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 584 .fs_reg = -1, 585 .fs_shift = -1, 586 .fs_maskbit = -1, 587 .mono_reg = -1, 588 .mono_shift = -1, 589 .enable_reg = -1, /* control in tdm for sync start */ 590 .enable_shift = -1, 591 .hd_reg = AFE_MEMIF_HD_MODE, 592 .hd_shift = HDMI_HD_SFT, 593 .agent_disable_reg = -1, 594 .agent_disable_shift = -1, 595 .msb_reg = -1, 596 .msb_shift = -1, 597 }, 598 }; 599 600 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = { 601 [MT8183_IRQ_0] = { 602 .id = MT8183_IRQ_0, 603 .irq_cnt_reg = AFE_IRQ_MCU_CNT0, 604 .irq_cnt_shift = 0, 605 .irq_cnt_maskbit = 0x3ffff, 606 .irq_fs_reg = AFE_IRQ_MCU_CON1, 607 .irq_fs_shift = IRQ0_MCU_MODE_SFT, 608 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK, 609 .irq_en_reg = AFE_IRQ_MCU_CON0, 610 .irq_en_shift = IRQ0_MCU_ON_SFT, 611 .irq_clr_reg = AFE_IRQ_MCU_CLR, 612 .irq_clr_shift = IRQ0_MCU_CLR_SFT, 613 }, 614 [MT8183_IRQ_1] = { 615 .id = MT8183_IRQ_1, 616 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 617 .irq_cnt_shift = 0, 618 .irq_cnt_maskbit = 0x3ffff, 619 .irq_fs_reg = AFE_IRQ_MCU_CON1, 620 .irq_fs_shift = IRQ1_MCU_MODE_SFT, 621 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK, 622 .irq_en_reg = AFE_IRQ_MCU_CON0, 623 .irq_en_shift = IRQ1_MCU_ON_SFT, 624 .irq_clr_reg = AFE_IRQ_MCU_CLR, 625 .irq_clr_shift = IRQ1_MCU_CLR_SFT, 626 }, 627 [MT8183_IRQ_2] = { 628 .id = MT8183_IRQ_2, 629 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 630 .irq_cnt_shift = 0, 631 .irq_cnt_maskbit = 0x3ffff, 632 .irq_fs_reg = AFE_IRQ_MCU_CON1, 633 .irq_fs_shift = IRQ2_MCU_MODE_SFT, 634 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK, 635 .irq_en_reg = AFE_IRQ_MCU_CON0, 636 .irq_en_shift = IRQ2_MCU_ON_SFT, 637 .irq_clr_reg = AFE_IRQ_MCU_CLR, 638 .irq_clr_shift = IRQ2_MCU_CLR_SFT, 639 }, 640 [MT8183_IRQ_3] = { 641 .id = MT8183_IRQ_3, 642 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 643 .irq_cnt_shift = 0, 644 .irq_cnt_maskbit = 0x3ffff, 645 .irq_fs_reg = AFE_IRQ_MCU_CON1, 646 .irq_fs_shift = IRQ3_MCU_MODE_SFT, 647 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK, 648 .irq_en_reg = AFE_IRQ_MCU_CON0, 649 .irq_en_shift = IRQ3_MCU_ON_SFT, 650 .irq_clr_reg = AFE_IRQ_MCU_CLR, 651 .irq_clr_shift = IRQ3_MCU_CLR_SFT, 652 }, 653 [MT8183_IRQ_4] = { 654 .id = MT8183_IRQ_4, 655 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 656 .irq_cnt_shift = 0, 657 .irq_cnt_maskbit = 0x3ffff, 658 .irq_fs_reg = AFE_IRQ_MCU_CON1, 659 .irq_fs_shift = IRQ4_MCU_MODE_SFT, 660 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK, 661 .irq_en_reg = AFE_IRQ_MCU_CON0, 662 .irq_en_shift = IRQ4_MCU_ON_SFT, 663 .irq_clr_reg = AFE_IRQ_MCU_CLR, 664 .irq_clr_shift = IRQ4_MCU_CLR_SFT, 665 }, 666 [MT8183_IRQ_5] = { 667 .id = MT8183_IRQ_5, 668 .irq_cnt_reg = AFE_IRQ_MCU_CNT5, 669 .irq_cnt_shift = 0, 670 .irq_cnt_maskbit = 0x3ffff, 671 .irq_fs_reg = AFE_IRQ_MCU_CON1, 672 .irq_fs_shift = IRQ5_MCU_MODE_SFT, 673 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK, 674 .irq_en_reg = AFE_IRQ_MCU_CON0, 675 .irq_en_shift = IRQ5_MCU_ON_SFT, 676 .irq_clr_reg = AFE_IRQ_MCU_CLR, 677 .irq_clr_shift = IRQ5_MCU_CLR_SFT, 678 }, 679 [MT8183_IRQ_6] = { 680 .id = MT8183_IRQ_6, 681 .irq_cnt_reg = AFE_IRQ_MCU_CNT6, 682 .irq_cnt_shift = 0, 683 .irq_cnt_maskbit = 0x3ffff, 684 .irq_fs_reg = AFE_IRQ_MCU_CON1, 685 .irq_fs_shift = IRQ6_MCU_MODE_SFT, 686 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK, 687 .irq_en_reg = AFE_IRQ_MCU_CON0, 688 .irq_en_shift = IRQ6_MCU_ON_SFT, 689 .irq_clr_reg = AFE_IRQ_MCU_CLR, 690 .irq_clr_shift = IRQ6_MCU_CLR_SFT, 691 }, 692 [MT8183_IRQ_7] = { 693 .id = MT8183_IRQ_7, 694 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 695 .irq_cnt_shift = 0, 696 .irq_cnt_maskbit = 0x3ffff, 697 .irq_fs_reg = AFE_IRQ_MCU_CON1, 698 .irq_fs_shift = IRQ7_MCU_MODE_SFT, 699 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK, 700 .irq_en_reg = AFE_IRQ_MCU_CON0, 701 .irq_en_shift = IRQ7_MCU_ON_SFT, 702 .irq_clr_reg = AFE_IRQ_MCU_CLR, 703 .irq_clr_shift = IRQ7_MCU_CLR_SFT, 704 }, 705 [MT8183_IRQ_8] = { 706 .id = MT8183_IRQ_8, 707 .irq_cnt_reg = AFE_IRQ_MCU_CNT8, 708 .irq_cnt_shift = 0, 709 .irq_cnt_maskbit = 0x3ffff, 710 .irq_fs_reg = -1, 711 .irq_fs_shift = -1, 712 .irq_fs_maskbit = -1, 713 .irq_en_reg = AFE_IRQ_MCU_CON0, 714 .irq_en_shift = IRQ8_MCU_ON_SFT, 715 .irq_clr_reg = AFE_IRQ_MCU_CLR, 716 .irq_clr_shift = IRQ8_MCU_CLR_SFT, 717 }, 718 [MT8183_IRQ_11] = { 719 .id = MT8183_IRQ_11, 720 .irq_cnt_reg = AFE_IRQ_MCU_CNT11, 721 .irq_cnt_shift = 0, 722 .irq_cnt_maskbit = 0x3ffff, 723 .irq_fs_reg = AFE_IRQ_MCU_CON2, 724 .irq_fs_shift = IRQ11_MCU_MODE_SFT, 725 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK, 726 .irq_en_reg = AFE_IRQ_MCU_CON0, 727 .irq_en_shift = IRQ11_MCU_ON_SFT, 728 .irq_clr_reg = AFE_IRQ_MCU_CLR, 729 .irq_clr_shift = IRQ11_MCU_CLR_SFT, 730 }, 731 [MT8183_IRQ_12] = { 732 .id = MT8183_IRQ_12, 733 .irq_cnt_reg = AFE_IRQ_MCU_CNT12, 734 .irq_cnt_shift = 0, 735 .irq_cnt_maskbit = 0x3ffff, 736 .irq_fs_reg = AFE_IRQ_MCU_CON2, 737 .irq_fs_shift = IRQ12_MCU_MODE_SFT, 738 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK, 739 .irq_en_reg = AFE_IRQ_MCU_CON0, 740 .irq_en_shift = IRQ12_MCU_ON_SFT, 741 .irq_clr_reg = AFE_IRQ_MCU_CLR, 742 .irq_clr_shift = IRQ12_MCU_CLR_SFT, 743 }, 744 }; 745 746 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg) 747 { 748 /* these auto-gen reg has read-only bit, so put it as volatile */ 749 /* volatile reg cannot be cached, so cannot be set when power off */ 750 switch (reg) { 751 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */ 752 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */ 753 case AUDIO_TOP_CON3: 754 case AFE_DL1_CUR: 755 case AFE_DL1_END: 756 case AFE_DL2_CUR: 757 case AFE_DL2_END: 758 case AFE_AWB_END: 759 case AFE_AWB_CUR: 760 case AFE_VUL_END: 761 case AFE_VUL_CUR: 762 case AFE_MEMIF_MON0: 763 case AFE_MEMIF_MON1: 764 case AFE_MEMIF_MON2: 765 case AFE_MEMIF_MON3: 766 case AFE_MEMIF_MON4: 767 case AFE_MEMIF_MON5: 768 case AFE_MEMIF_MON6: 769 case AFE_MEMIF_MON7: 770 case AFE_MEMIF_MON8: 771 case AFE_MEMIF_MON9: 772 case AFE_ADDA_SRC_DEBUG_MON0: 773 case AFE_ADDA_SRC_DEBUG_MON1: 774 case AFE_ADDA_UL_SRC_MON0: 775 case AFE_ADDA_UL_SRC_MON1: 776 case AFE_SIDETONE_MON: 777 case AFE_SIDETONE_CON0: 778 case AFE_SIDETONE_COEFF: 779 case AFE_BUS_MON0: 780 case AFE_MRGIF_MON0: 781 case AFE_MRGIF_MON1: 782 case AFE_MRGIF_MON2: 783 case AFE_I2S_MON: 784 case AFE_DAC_MON: 785 case AFE_VUL2_END: 786 case AFE_VUL2_CUR: 787 case AFE_IRQ0_MCU_CNT_MON: 788 case AFE_IRQ6_MCU_CNT_MON: 789 case AFE_MOD_DAI_END: 790 case AFE_MOD_DAI_CUR: 791 case AFE_VUL_D2_END: 792 case AFE_VUL_D2_CUR: 793 case AFE_DL3_CUR: 794 case AFE_DL3_END: 795 case AFE_HDMI_OUT_CON0: 796 case AFE_HDMI_OUT_CUR: 797 case AFE_HDMI_OUT_END: 798 case AFE_IRQ3_MCU_CNT_MON: 799 case AFE_IRQ4_MCU_CNT_MON: 800 case AFE_IRQ_MCU_STATUS: 801 case AFE_IRQ_MCU_CLR: 802 case AFE_IRQ_MCU_MON2: 803 case AFE_IRQ1_MCU_CNT_MON: 804 case AFE_IRQ2_MCU_CNT_MON: 805 case AFE_IRQ1_MCU_EN_CNT_MON: 806 case AFE_IRQ5_MCU_CNT_MON: 807 case AFE_IRQ7_MCU_CNT_MON: 808 case AFE_GAIN1_CUR: 809 case AFE_GAIN2_CUR: 810 case AFE_SRAM_DELSEL_CON0: 811 case AFE_SRAM_DELSEL_CON2: 812 case AFE_SRAM_DELSEL_CON3: 813 case AFE_ASRC_2CH_CON12: 814 case AFE_ASRC_2CH_CON13: 815 case PCM_INTF_CON2: 816 case FPGA_CFG0: 817 case FPGA_CFG1: 818 case FPGA_CFG2: 819 case FPGA_CFG3: 820 case AUDIO_TOP_DBG_MON0: 821 case AUDIO_TOP_DBG_MON1: 822 case AFE_IRQ8_MCU_CNT_MON: 823 case AFE_IRQ11_MCU_CNT_MON: 824 case AFE_IRQ12_MCU_CNT_MON: 825 case AFE_CBIP_MON0: 826 case AFE_CBIP_SLV_MUX_MON0: 827 case AFE_CBIP_SLV_DECODER_MON0: 828 case AFE_ADDA6_SRC_DEBUG_MON0: 829 case AFE_ADD6A_UL_SRC_MON0: 830 case AFE_ADDA6_UL_SRC_MON1: 831 case AFE_DL1_CUR_MSB: 832 case AFE_DL2_CUR_MSB: 833 case AFE_AWB_CUR_MSB: 834 case AFE_VUL_CUR_MSB: 835 case AFE_VUL2_CUR_MSB: 836 case AFE_MOD_DAI_CUR_MSB: 837 case AFE_VUL_D2_CUR_MSB: 838 case AFE_DL3_CUR_MSB: 839 case AFE_HDMI_OUT_CUR_MSB: 840 case AFE_AWB2_END: 841 case AFE_AWB2_CUR: 842 case AFE_AWB2_CUR_MSB: 843 case AFE_ADDA_DL_SDM_FIFO_MON: 844 case AFE_ADDA_DL_SRC_LCH_MON: 845 case AFE_ADDA_DL_SRC_RCH_MON: 846 case AFE_ADDA_DL_SDM_OUT_MON: 847 case AFE_CONNSYS_I2S_MON: 848 case AFE_ASRC_2CH_CON0: 849 case AFE_ASRC_2CH_CON2: 850 case AFE_ASRC_2CH_CON3: 851 case AFE_ASRC_2CH_CON4: 852 case AFE_ASRC_2CH_CON5: 853 case AFE_ASRC_2CH_CON7: 854 case AFE_ASRC_2CH_CON8: 855 case AFE_MEMIF_MON12: 856 case AFE_MEMIF_MON13: 857 case AFE_MEMIF_MON14: 858 case AFE_MEMIF_MON15: 859 case AFE_MEMIF_MON16: 860 case AFE_MEMIF_MON17: 861 case AFE_MEMIF_MON18: 862 case AFE_MEMIF_MON19: 863 case AFE_MEMIF_MON20: 864 case AFE_MEMIF_MON21: 865 case AFE_MEMIF_MON22: 866 case AFE_MEMIF_MON23: 867 case AFE_MEMIF_MON24: 868 case AFE_ADDA_MTKAIF_MON0: 869 case AFE_ADDA_MTKAIF_MON1: 870 case AFE_AUD_PAD_TOP: 871 case AFE_GENERAL1_ASRC_2CH_CON0: 872 case AFE_GENERAL1_ASRC_2CH_CON2: 873 case AFE_GENERAL1_ASRC_2CH_CON3: 874 case AFE_GENERAL1_ASRC_2CH_CON4: 875 case AFE_GENERAL1_ASRC_2CH_CON5: 876 case AFE_GENERAL1_ASRC_2CH_CON7: 877 case AFE_GENERAL1_ASRC_2CH_CON8: 878 case AFE_GENERAL1_ASRC_2CH_CON12: 879 case AFE_GENERAL1_ASRC_2CH_CON13: 880 case AFE_GENERAL2_ASRC_2CH_CON0: 881 case AFE_GENERAL2_ASRC_2CH_CON2: 882 case AFE_GENERAL2_ASRC_2CH_CON3: 883 case AFE_GENERAL2_ASRC_2CH_CON4: 884 case AFE_GENERAL2_ASRC_2CH_CON5: 885 case AFE_GENERAL2_ASRC_2CH_CON7: 886 case AFE_GENERAL2_ASRC_2CH_CON8: 887 case AFE_GENERAL2_ASRC_2CH_CON12: 888 case AFE_GENERAL2_ASRC_2CH_CON13: 889 return true; 890 default: 891 return false; 892 }; 893 } 894 895 static const struct regmap_config mt8183_afe_regmap_config = { 896 .reg_bits = 32, 897 .reg_stride = 4, 898 .val_bits = 32, 899 900 .volatile_reg = mt8183_is_volatile_reg, 901 902 .max_register = AFE_MAX_REGISTER, 903 .num_reg_defaults_raw = AFE_MAX_REGISTER, 904 905 .cache_type = REGCACHE_FLAT, 906 }; 907 908 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev) 909 { 910 struct mtk_base_afe *afe = dev; 911 struct mtk_base_afe_irq *irq; 912 unsigned int status; 913 unsigned int status_mcu; 914 unsigned int mcu_en; 915 int ret; 916 int i; 917 irqreturn_t irq_ret = IRQ_HANDLED; 918 919 /* get irq that is sent to MCU */ 920 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 921 922 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 923 /* only care IRQ which is sent to MCU */ 924 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; 925 926 if (ret || status_mcu == 0) { 927 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", 928 __func__, ret, status, mcu_en); 929 930 irq_ret = IRQ_NONE; 931 goto err_irq; 932 } 933 934 for (i = 0; i < MT8183_MEMIF_NUM; i++) { 935 struct mtk_base_afe_memif *memif = &afe->memif[i]; 936 937 if (!memif->substream) 938 continue; 939 940 if (memif->irq_usage < 0) 941 continue; 942 943 irq = &afe->irqs[memif->irq_usage]; 944 945 if (status_mcu & (1 << irq->irq_data->irq_en_shift)) 946 snd_pcm_period_elapsed(memif->substream); 947 } 948 949 err_irq: 950 /* clear irq */ 951 regmap_write(afe->regmap, 952 AFE_IRQ_MCU_CLR, 953 status_mcu); 954 955 return irq_ret; 956 } 957 958 static int mt8183_afe_runtime_suspend(struct device *dev) 959 { 960 struct mtk_base_afe *afe = dev_get_drvdata(dev); 961 struct mt8183_afe_private *afe_priv = afe->platform_priv; 962 unsigned int value; 963 int ret; 964 965 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 966 goto skip_regmap; 967 968 /* disable AFE */ 969 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0); 970 971 ret = regmap_read_poll_timeout(afe->regmap, 972 AFE_DAC_MON, 973 value, 974 (value & AFE_ON_RETM_MASK_SFT) == 0, 975 20, 976 1 * 1000 * 1000); 977 if (ret) 978 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret); 979 980 /* make sure all irq status are cleared, twice intended */ 981 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); 982 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); 983 984 /* cache only */ 985 regcache_cache_only(afe->regmap, true); 986 regcache_mark_dirty(afe->regmap); 987 988 skip_regmap: 989 return mt8183_afe_disable_clock(afe); 990 } 991 992 static int mt8183_afe_runtime_resume(struct device *dev) 993 { 994 struct mtk_base_afe *afe = dev_get_drvdata(dev); 995 struct mt8183_afe_private *afe_priv = afe->platform_priv; 996 int ret; 997 998 ret = mt8183_afe_enable_clock(afe); 999 if (ret) 1000 return ret; 1001 1002 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 1003 goto skip_regmap; 1004 1005 regcache_cache_only(afe->regmap, false); 1006 regcache_sync(afe->regmap); 1007 1008 /* enable audio sys DCM for power saving */ 1009 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29); 1010 1011 /* force cpu use 8_24 format when writing 32bit data */ 1012 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB, 1013 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); 1014 1015 /* set all output port to 24bit */ 1016 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff); 1017 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff); 1018 1019 /* enable AFE */ 1020 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 1021 1022 skip_regmap: 1023 return 0; 1024 } 1025 1026 static int mt8183_afe_component_probe(struct snd_soc_component *component) 1027 { 1028 return mtk_afe_add_sub_dai_control(component); 1029 } 1030 1031 static const struct snd_soc_component_driver mt8183_afe_component = { 1032 .name = AFE_PCM_NAME, 1033 .ops = &mtk_afe_pcm_ops, 1034 .pcm_new = mtk_afe_pcm_new, 1035 .pcm_free = mtk_afe_pcm_free, 1036 .probe = mt8183_afe_component_probe, 1037 }; 1038 1039 static int mt8183_dai_memif_register(struct mtk_base_afe *afe) 1040 { 1041 struct mtk_base_afe_dai *dai; 1042 1043 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1044 if (!dai) 1045 return -ENOMEM; 1046 1047 list_add(&dai->list, &afe->sub_dais); 1048 1049 dai->dai_drivers = mt8183_memif_dai_driver; 1050 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver); 1051 1052 dai->dapm_widgets = mt8183_memif_widgets; 1053 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets); 1054 dai->dapm_routes = mt8183_memif_routes; 1055 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes); 1056 return 0; 1057 } 1058 1059 typedef int (*dai_register_cb)(struct mtk_base_afe *); 1060 static const dai_register_cb dai_register_cbs[] = { 1061 mt8183_dai_adda_register, 1062 mt8183_dai_i2s_register, 1063 mt8183_dai_pcm_register, 1064 mt8183_dai_tdm_register, 1065 mt8183_dai_hostless_register, 1066 mt8183_dai_memif_register, 1067 }; 1068 1069 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) 1070 { 1071 struct mtk_base_afe *afe; 1072 struct mt8183_afe_private *afe_priv; 1073 struct device *dev; 1074 int i, irq_id, ret; 1075 1076 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1077 if (!afe) 1078 return -ENOMEM; 1079 platform_set_drvdata(pdev, afe); 1080 1081 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1082 GFP_KERNEL); 1083 if (!afe->platform_priv) 1084 return -ENOMEM; 1085 1086 afe_priv = afe->platform_priv; 1087 afe->dev = &pdev->dev; 1088 dev = afe->dev; 1089 1090 /* initial audio related clock */ 1091 ret = mt8183_init_clock(afe); 1092 if (ret) { 1093 dev_err(dev, "init clock error\n"); 1094 return ret; 1095 } 1096 1097 pm_runtime_enable(dev); 1098 1099 /* regmap init */ 1100 afe->regmap = syscon_node_to_regmap(dev->parent->of_node); 1101 if (IS_ERR(afe->regmap)) { 1102 dev_err(dev, "could not get regmap from parent\n"); 1103 return PTR_ERR(afe->regmap); 1104 } 1105 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config); 1106 if (ret) { 1107 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret); 1108 return ret; 1109 } 1110 1111 /* enable clock for regcache get default value from hw */ 1112 afe_priv->pm_runtime_bypass_reg_ctl = true; 1113 pm_runtime_get_sync(&pdev->dev); 1114 1115 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config); 1116 if (ret) { 1117 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret); 1118 return ret; 1119 } 1120 1121 pm_runtime_put_sync(&pdev->dev); 1122 afe_priv->pm_runtime_bypass_reg_ctl = false; 1123 1124 regcache_cache_only(afe->regmap, true); 1125 regcache_mark_dirty(afe->regmap); 1126 1127 pm_runtime_get_sync(&pdev->dev); 1128 1129 /* init memif */ 1130 afe->memif_size = MT8183_MEMIF_NUM; 1131 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 1132 GFP_KERNEL); 1133 if (!afe->memif) 1134 return -ENOMEM; 1135 1136 for (i = 0; i < afe->memif_size; i++) { 1137 afe->memif[i].data = &memif_data[i]; 1138 afe->memif[i].irq_usage = -1; 1139 } 1140 1141 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8; 1142 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1; 1143 1144 mutex_init(&afe->irq_alloc_lock); 1145 1146 /* init memif */ 1147 /* irq initialize */ 1148 afe->irqs_size = MT8183_IRQ_NUM; 1149 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 1150 GFP_KERNEL); 1151 if (!afe->irqs) 1152 return -ENOMEM; 1153 1154 for (i = 0; i < afe->irqs_size; i++) 1155 afe->irqs[i].irq_data = &irq_data[i]; 1156 1157 /* request irq */ 1158 irq_id = platform_get_irq(pdev, 0); 1159 if (!irq_id) { 1160 dev_err(dev, "%pOFn no irq found\n", dev->of_node); 1161 return -ENXIO; 1162 } 1163 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler, 1164 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 1165 if (ret) { 1166 dev_err(dev, "could not request_irq for asys-isr\n"); 1167 return ret; 1168 } 1169 1170 /* init sub_dais */ 1171 INIT_LIST_HEAD(&afe->sub_dais); 1172 1173 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 1174 ret = dai_register_cbs[i](afe); 1175 if (ret) { 1176 dev_warn(afe->dev, "dai register i %d fail, ret %d\n", 1177 i, ret); 1178 return ret; 1179 } 1180 } 1181 1182 /* init dai_driver and component_driver */ 1183 ret = mtk_afe_combine_sub_dai(afe); 1184 if (ret) { 1185 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 1186 ret); 1187 return ret; 1188 } 1189 1190 afe->mtk_afe_hardware = &mt8183_afe_hardware; 1191 afe->memif_fs = mt8183_memif_fs; 1192 afe->irq_fs = mt8183_irq_fs; 1193 1194 afe->runtime_resume = mt8183_afe_runtime_resume; 1195 afe->runtime_suspend = mt8183_afe_runtime_suspend; 1196 1197 /* register component */ 1198 ret = devm_snd_soc_register_component(&pdev->dev, 1199 &mt8183_afe_component, 1200 NULL, 0); 1201 if (ret) { 1202 dev_warn(dev, "err_platform\n"); 1203 return ret; 1204 } 1205 1206 ret = devm_snd_soc_register_component(afe->dev, 1207 &mt8183_afe_pcm_dai_component, 1208 afe->dai_drivers, 1209 afe->num_dai_drivers); 1210 if (ret) { 1211 dev_warn(dev, "err_dai_component\n"); 1212 return ret; 1213 } 1214 1215 return ret; 1216 } 1217 1218 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev) 1219 { 1220 pm_runtime_put_sync(&pdev->dev); 1221 1222 pm_runtime_disable(&pdev->dev); 1223 if (!pm_runtime_status_suspended(&pdev->dev)) 1224 mt8183_afe_runtime_suspend(&pdev->dev); 1225 return 0; 1226 } 1227 1228 static const struct of_device_id mt8183_afe_pcm_dt_match[] = { 1229 { .compatible = "mediatek,mt8183-audio", }, 1230 {}, 1231 }; 1232 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match); 1233 1234 static const struct dev_pm_ops mt8183_afe_pm_ops = { 1235 SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend, 1236 mt8183_afe_runtime_resume, NULL) 1237 }; 1238 1239 static struct platform_driver mt8183_afe_pcm_driver = { 1240 .driver = { 1241 .name = "mt8183-audio", 1242 .of_match_table = mt8183_afe_pcm_dt_match, 1243 #ifdef CONFIG_PM 1244 .pm = &mt8183_afe_pm_ops, 1245 #endif 1246 }, 1247 .probe = mt8183_afe_pcm_dev_probe, 1248 .remove = mt8183_afe_pcm_dev_remove, 1249 }; 1250 1251 module_platform_driver(mt8183_afe_pcm_driver); 1252 1253 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183"); 1254 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 1255 MODULE_LICENSE("GPL v2"); 1256