197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cd59f138SKenneth Westfield /* 37cb37b7bSV Sujith Kumar Reddy * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved. 4cd59f138SKenneth Westfield * 5cd59f138SKenneth Westfield * lpass.h - Definitions for the QTi LPASS 6cd59f138SKenneth Westfield */ 7cd59f138SKenneth Westfield 8cd59f138SKenneth Westfield #ifndef __LPASS_H__ 9cd59f138SKenneth Westfield #define __LPASS_H__ 10cd59f138SKenneth Westfield 11cd59f138SKenneth Westfield #include <linux/clk.h> 12cd59f138SKenneth Westfield #include <linux/compiler.h> 13cd59f138SKenneth Westfield #include <linux/platform_device.h> 14cd59f138SKenneth Westfield #include <linux/regmap.h> 15cd3484f7SSrinivas Kandagatla #include <dt-bindings/sound/qcom,lpass.h> 167cb37b7bSV Sujith Kumar Reddy #include "lpass-hdmi.h" 17cd59f138SKenneth Westfield 18cd59f138SKenneth Westfield #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 1977d0ffefSSrinivasa Rao Mandadapu #define LPASS_MAX_PORTS (LPASS_CDC_DMA_VA_TX8 + 1) 209a127cffSSrinivas Kandagatla #define LPASS_MAX_MI2S_PORTS (8) 214f629e4bSSrinivas Kandagatla #define LPASS_MAX_DMA_CHANNELS (8) 227cb37b7bSV Sujith Kumar Reddy #define LPASS_MAX_HDMI_DMA_CHANNELS (4) 237cb37b7bSV Sujith Kumar Reddy 247cb37b7bSV Sujith Kumar Reddy #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \ 257cb37b7bSV Sujith Kumar Reddy do { \ 267cb37b7bSV Sujith Kumar Reddy mf = devm_regmap_field_alloc(d, m, f); \ 277cb37b7bSV Sujith Kumar Reddy if (IS_ERR(mf)) \ 287cb37b7bSV Sujith Kumar Reddy return -EINVAL; \ 297cb37b7bSV Sujith Kumar Reddy } while (0) 30cd59f138SKenneth Westfield 31b5022a36SRohit kumar struct lpaif_i2sctl { 32b5022a36SRohit kumar struct regmap_field *loopback; 33b5022a36SRohit kumar struct regmap_field *spken; 34b5022a36SRohit kumar struct regmap_field *spkmode; 35b5022a36SRohit kumar struct regmap_field *spkmono; 36b5022a36SRohit kumar struct regmap_field *micen; 37b5022a36SRohit kumar struct regmap_field *micmode; 38b5022a36SRohit kumar struct regmap_field *micmono; 39b5022a36SRohit kumar struct regmap_field *wssrc; 40b5022a36SRohit kumar struct regmap_field *bitwidth; 41b5022a36SRohit kumar }; 42b5022a36SRohit kumar 43b5022a36SRohit kumar 44b5022a36SRohit kumar struct lpaif_dmactl { 45d9e8e612SV Sujith Kumar Reddy struct regmap_field *intf; 46b5022a36SRohit kumar struct regmap_field *bursten; 47b5022a36SRohit kumar struct regmap_field *wpscnt; 48b5022a36SRohit kumar struct regmap_field *fifowm; 49b5022a36SRohit kumar struct regmap_field *enable; 50b5022a36SRohit kumar struct regmap_field *dyncclk; 517cb37b7bSV Sujith Kumar Reddy struct regmap_field *burst8; 527cb37b7bSV Sujith Kumar Reddy struct regmap_field *burst16; 537cb37b7bSV Sujith Kumar Reddy struct regmap_field *dynburst; 54b5022a36SRohit kumar }; 55b5022a36SRohit kumar 56cd59f138SKenneth Westfield /* Both the CPU DAI and platform drivers will access this data */ 57cd59f138SKenneth Westfield struct lpass_data { 58cd59f138SKenneth Westfield 59cd59f138SKenneth Westfield /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ 60cd59f138SKenneth Westfield struct clk *ahbix_clk; 61cd59f138SKenneth Westfield 62cd59f138SKenneth Westfield /* MI2S system clock */ 639a127cffSSrinivas Kandagatla struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; 64cd59f138SKenneth Westfield 65cd59f138SKenneth Westfield /* MI2S bit clock (derived from system clock by a divider */ 669a127cffSSrinivas Kandagatla struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; 67cd59f138SKenneth Westfield 684ff028f6SStephan Gerhold /* MI2S SD lines to use for playback/capture */ 694ff028f6SStephan Gerhold unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS]; 704ff028f6SStephan Gerhold unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS]; 71c8a4556dSSrinivasa Rao Mandadapu 72c8a4556dSSrinivasa Rao Mandadapu /* The state of MI2S prepare dai_ops was called */ 73c8a4556dSSrinivasa Rao Mandadapu bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS]; 74c8a4556dSSrinivasa Rao Mandadapu 757cb37b7bSV Sujith Kumar Reddy int hdmi_port_enable; 764ff028f6SStephan Gerhold 77cd59f138SKenneth Westfield /* low-power audio interface (LPAIF) registers */ 78cd59f138SKenneth Westfield void __iomem *lpaif; 797cb37b7bSV Sujith Kumar Reddy void __iomem *hdmiif; 80cd59f138SKenneth Westfield 81cd59f138SKenneth Westfield /* regmap backed by the low-power audio interface (LPAIF) registers */ 82cd59f138SKenneth Westfield struct regmap *lpaif_map; 837cb37b7bSV Sujith Kumar Reddy struct regmap *hdmiif_map; 84cd59f138SKenneth Westfield 85cd59f138SKenneth Westfield /* interrupts from the low-power audio interface (LPAIF) */ 86cd59f138SKenneth Westfield int lpaif_irq; 877cb37b7bSV Sujith Kumar Reddy int hdmiif_irq; 889bae4880SSrinivas Kandagatla /* SOC specific variations in the LPASS IP integration */ 899bae4880SSrinivas Kandagatla struct lpass_variant *variant; 904f629e4bSSrinivas Kandagatla 9189cdfa06SSrinivas Kandagatla /* bit map to keep track of static channel allocations */ 924d809fb1SSrinivas Kandagatla unsigned long dma_ch_bit_map; 937cb37b7bSV Sujith Kumar Reddy unsigned long hdmi_dma_ch_bit_map; 9489cdfa06SSrinivas Kandagatla 954f629e4bSSrinivas Kandagatla /* used it for handling interrupt per dma channel */ 964f629e4bSSrinivas Kandagatla struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; 977cb37b7bSV Sujith Kumar Reddy struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS]; 98dc1ebd18SSrinivas Kandagatla 991220f6a7SAjit Pandey /* SOC specific clock list */ 1001220f6a7SAjit Pandey struct clk_bulk_data *clks; 1011220f6a7SAjit Pandey int num_clks; 1026adcbdcdSKuninori Morimoto 103b5022a36SRohit kumar /* Regmap fields of I2SCTL & DMACTL registers bitfields */ 104b5022a36SRohit kumar struct lpaif_i2sctl *i2sctl; 105b5022a36SRohit kumar struct lpaif_dmactl *rd_dmactl; 106b5022a36SRohit kumar struct lpaif_dmactl *wr_dmactl; 1077cb37b7bSV Sujith Kumar Reddy struct lpaif_dmactl *hdmi_rd_dmactl; 1087cb37b7bSV Sujith Kumar Reddy /* Regmap fields of HDMI_CTRL registers*/ 1097cb37b7bSV Sujith Kumar Reddy struct regmap_field *hdmitx_legacy_en; 1107cb37b7bSV Sujith Kumar Reddy struct regmap_field *hdmitx_parity_calc_en; 1117cb37b7bSV Sujith Kumar Reddy struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS]; 1127cb37b7bSV Sujith Kumar Reddy struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS]; 1137cb37b7bSV Sujith Kumar Reddy struct lpass_hdmi_tx_ctl *tx_ctl; 1147cb37b7bSV Sujith Kumar Reddy struct lpass_vbit_ctrl *vbit_ctl; 1157cb37b7bSV Sujith Kumar Reddy struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS]; 1167cb37b7bSV Sujith Kumar Reddy struct lpass_dp_metadata_ctl *meta_ctl; 1177cb37b7bSV Sujith Kumar Reddy struct lpass_sstream_ctl *sstream_ctl; 1189bae4880SSrinivas Kandagatla }; 1199bae4880SSrinivas Kandagatla 1209bae4880SSrinivas Kandagatla /* Vairant data per each SOC */ 1219bae4880SSrinivas Kandagatla struct lpass_variant { 1229bae4880SSrinivas Kandagatla u32 irq_reg_base; 1239bae4880SSrinivas Kandagatla u32 irq_reg_stride; 1249bae4880SSrinivas Kandagatla u32 irq_ports; 1259bae4880SSrinivas Kandagatla u32 rdma_reg_base; 1269bae4880SSrinivas Kandagatla u32 rdma_reg_stride; 1279bae4880SSrinivas Kandagatla u32 rdma_channels; 1287cb37b7bSV Sujith Kumar Reddy u32 hdmi_rdma_reg_base; 1297cb37b7bSV Sujith Kumar Reddy u32 hdmi_rdma_reg_stride; 1307cb37b7bSV Sujith Kumar Reddy u32 hdmi_rdma_channels; 131ffc1325eSSrinivas Kandagatla u32 wrdma_reg_base; 132ffc1325eSSrinivas Kandagatla u32 wrdma_reg_stride; 133ffc1325eSSrinivas Kandagatla u32 wrdma_channels; 1347cb37b7bSV Sujith Kumar Reddy u32 i2sctrl_reg_base; 1357cb37b7bSV Sujith Kumar Reddy u32 i2sctrl_reg_stride; 1367cb37b7bSV Sujith Kumar Reddy u32 i2s_ports; 1379bae4880SSrinivas Kandagatla 138b5022a36SRohit kumar /* I2SCTL Register fields */ 139b5022a36SRohit kumar struct reg_field loopback; 140b5022a36SRohit kumar struct reg_field spken; 141b5022a36SRohit kumar struct reg_field spkmode; 142b5022a36SRohit kumar struct reg_field spkmono; 143b5022a36SRohit kumar struct reg_field micen; 144b5022a36SRohit kumar struct reg_field micmode; 145b5022a36SRohit kumar struct reg_field micmono; 146b5022a36SRohit kumar struct reg_field wssrc; 147b5022a36SRohit kumar struct reg_field bitwidth; 148b5022a36SRohit kumar 1497cb37b7bSV Sujith Kumar Reddy u32 hdmi_irq_reg_base; 1507cb37b7bSV Sujith Kumar Reddy u32 hdmi_irq_reg_stride; 1517cb37b7bSV Sujith Kumar Reddy u32 hdmi_irq_ports; 1527cb37b7bSV Sujith Kumar Reddy 1537cb37b7bSV Sujith Kumar Reddy /* HDMI specific controls */ 1547cb37b7bSV Sujith Kumar Reddy u32 hdmi_tx_ctl_addr; 1557cb37b7bSV Sujith Kumar Reddy u32 hdmi_legacy_addr; 1567cb37b7bSV Sujith Kumar Reddy u32 hdmi_vbit_addr; 1577cb37b7bSV Sujith Kumar Reddy u32 hdmi_ch_lsb_addr; 1587cb37b7bSV Sujith Kumar Reddy u32 hdmi_ch_msb_addr; 1597cb37b7bSV Sujith Kumar Reddy u32 ch_stride; 1607cb37b7bSV Sujith Kumar Reddy u32 hdmi_parity_addr; 1617cb37b7bSV Sujith Kumar Reddy u32 hdmi_dmactl_addr; 1627cb37b7bSV Sujith Kumar Reddy u32 hdmi_dma_stride; 1637cb37b7bSV Sujith Kumar Reddy u32 hdmi_DP_addr; 1647cb37b7bSV Sujith Kumar Reddy u32 hdmi_sstream_addr; 1657cb37b7bSV Sujith Kumar Reddy 1667cb37b7bSV Sujith Kumar Reddy /* HDMI SSTREAM CTRL fields */ 1677cb37b7bSV Sujith Kumar Reddy struct reg_field sstream_en; 1687cb37b7bSV Sujith Kumar Reddy struct reg_field dma_sel; 1697cb37b7bSV Sujith Kumar Reddy struct reg_field auto_bbit_en; 1707cb37b7bSV Sujith Kumar Reddy struct reg_field layout; 1717cb37b7bSV Sujith Kumar Reddy struct reg_field layout_sp; 1727cb37b7bSV Sujith Kumar Reddy struct reg_field set_sp_on_en; 1737cb37b7bSV Sujith Kumar Reddy struct reg_field dp_audio; 1747cb37b7bSV Sujith Kumar Reddy struct reg_field dp_staffing_en; 1757cb37b7bSV Sujith Kumar Reddy struct reg_field dp_sp_b_hw_en; 1767cb37b7bSV Sujith Kumar Reddy 1777cb37b7bSV Sujith Kumar Reddy /* HDMI DP METADATA CTL fields */ 1787cb37b7bSV Sujith Kumar Reddy struct reg_field mute; 1797cb37b7bSV Sujith Kumar Reddy struct reg_field as_sdp_cc; 1807cb37b7bSV Sujith Kumar Reddy struct reg_field as_sdp_ct; 1817cb37b7bSV Sujith Kumar Reddy struct reg_field aif_db4; 1827cb37b7bSV Sujith Kumar Reddy struct reg_field frequency; 1837cb37b7bSV Sujith Kumar Reddy struct reg_field mst_index; 1847cb37b7bSV Sujith Kumar Reddy struct reg_field dptx_index; 1857cb37b7bSV Sujith Kumar Reddy 1867cb37b7bSV Sujith Kumar Reddy /* HDMI TX CTRL fields */ 1877cb37b7bSV Sujith Kumar Reddy struct reg_field soft_reset; 1887cb37b7bSV Sujith Kumar Reddy struct reg_field force_reset; 1897cb37b7bSV Sujith Kumar Reddy 1907cb37b7bSV Sujith Kumar Reddy /* HDMI TX DMA CTRL */ 1917cb37b7bSV Sujith Kumar Reddy struct reg_field use_hw_chs; 1927cb37b7bSV Sujith Kumar Reddy struct reg_field use_hw_usr; 1937cb37b7bSV Sujith Kumar Reddy struct reg_field hw_chs_sel; 1947cb37b7bSV Sujith Kumar Reddy struct reg_field hw_usr_sel; 1957cb37b7bSV Sujith Kumar Reddy 1967cb37b7bSV Sujith Kumar Reddy /* HDMI VBIT CTRL */ 1977cb37b7bSV Sujith Kumar Reddy struct reg_field replace_vbit; 1987cb37b7bSV Sujith Kumar Reddy struct reg_field vbit_stream; 1997cb37b7bSV Sujith Kumar Reddy 2007cb37b7bSV Sujith Kumar Reddy /* HDMI TX LEGACY */ 2017cb37b7bSV Sujith Kumar Reddy struct reg_field legacy_en; 2027cb37b7bSV Sujith Kumar Reddy 2037cb37b7bSV Sujith Kumar Reddy /* HDMI TX PARITY */ 2047cb37b7bSV Sujith Kumar Reddy struct reg_field calc_en; 2057cb37b7bSV Sujith Kumar Reddy 2067cb37b7bSV Sujith Kumar Reddy /* HDMI CH LSB */ 2077cb37b7bSV Sujith Kumar Reddy struct reg_field lsb_bits; 2087cb37b7bSV Sujith Kumar Reddy 2097cb37b7bSV Sujith Kumar Reddy /* HDMI CH MSB */ 2107cb37b7bSV Sujith Kumar Reddy struct reg_field msb_bits; 2117cb37b7bSV Sujith Kumar Reddy 2127cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_bursten; 2137cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_wpscnt; 2147cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_fifowm; 2157cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_enable; 2167cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_dyncclk; 2177cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_burst8; 2187cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_burst16; 2197cb37b7bSV Sujith Kumar Reddy struct reg_field hdmi_rdma_dynburst; 2207cb37b7bSV Sujith Kumar Reddy 221b5022a36SRohit kumar /* RD_DMA Register fields */ 222d9e8e612SV Sujith Kumar Reddy struct reg_field rdma_intf; 223b5022a36SRohit kumar struct reg_field rdma_bursten; 224b5022a36SRohit kumar struct reg_field rdma_wpscnt; 225b5022a36SRohit kumar struct reg_field rdma_fifowm; 226b5022a36SRohit kumar struct reg_field rdma_enable; 227b5022a36SRohit kumar struct reg_field rdma_dyncclk; 228b5022a36SRohit kumar 229b5022a36SRohit kumar /* WR_DMA Register fields */ 230d9e8e612SV Sujith Kumar Reddy struct reg_field wrdma_intf; 231b5022a36SRohit kumar struct reg_field wrdma_bursten; 232b5022a36SRohit kumar struct reg_field wrdma_wpscnt; 233b5022a36SRohit kumar struct reg_field wrdma_fifowm; 234b5022a36SRohit kumar struct reg_field wrdma_enable; 235b5022a36SRohit kumar struct reg_field wrdma_dyncclk; 236b5022a36SRohit kumar 2370054055cSSrinivas Kandagatla /** 2380054055cSSrinivas Kandagatla * on SOCs like APQ8016 the channel control bits start 2390054055cSSrinivas Kandagatla * at different offset to ipq806x 2400054055cSSrinivas Kandagatla **/ 241ec5b8287SSrinivas Kandagatla u32 dmactl_audif_start; 242ffc1325eSSrinivas Kandagatla u32 wrdma_channel_start; 243183b8021SMasahiro Yamada /* SOC specific initialization like clocks */ 2449bae4880SSrinivas Kandagatla int (*init)(struct platform_device *pdev); 2459bae4880SSrinivas Kandagatla int (*exit)(struct platform_device *pdev); 2467cb37b7bSV Sujith Kumar Reddy int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id); 2477cb37b7bSV Sujith Kumar Reddy int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id); 2489bae4880SSrinivas Kandagatla 2499bae4880SSrinivas Kandagatla /* SOC specific dais */ 2509bae4880SSrinivas Kandagatla struct snd_soc_dai_driver *dai_driver; 2519bae4880SSrinivas Kandagatla int num_dai; 25297c52eb9SLinus Walleij const char * const *dai_osr_clk_names; 25397c52eb9SLinus Walleij const char * const *dai_bit_clk_names; 2541220f6a7SAjit Pandey 2551220f6a7SAjit Pandey /* SOC specific clocks configuration */ 2561220f6a7SAjit Pandey const char **clk_name; 2571220f6a7SAjit Pandey int num_clks; 258cd59f138SKenneth Westfield }; 259cd59f138SKenneth Westfield 260*74190d7cSSrinivasa Rao Mandadapu struct lpass_pcm_data { 261*74190d7cSSrinivasa Rao Mandadapu int dma_ch; 262*74190d7cSSrinivasa Rao Mandadapu int i2s_port; 263*74190d7cSSrinivasa Rao Mandadapu }; 264*74190d7cSSrinivasa Rao Mandadapu 265cd59f138SKenneth Westfield /* register the platform driver from the CPU DAI driver */ 266cd59f138SKenneth Westfield int asoc_qcom_lpass_platform_register(struct platform_device *); 2679bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev); 26860a97386SV Sujith Kumar Reddy void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev); 2699bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev); 2709bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai); 271618718dcSAxel Lin extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; 272c223f41cSSrinivasa Rao Mandadapu int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd, 273c223f41cSSrinivasa Rao Mandadapu struct snd_soc_dai *dai); 274cd59f138SKenneth Westfield 275cd59f138SKenneth Westfield #endif /* __LPASS_H__ */ 276