1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 22 /* SPDIF-rx Register Map */ 23 #define STM32_SPDIFRX_CR 0x00 24 #define STM32_SPDIFRX_IMR 0x04 25 #define STM32_SPDIFRX_SR 0x08 26 #define STM32_SPDIFRX_IFCR 0x0C 27 #define STM32_SPDIFRX_DR 0x10 28 #define STM32_SPDIFRX_CSR 0x14 29 #define STM32_SPDIFRX_DIR 0x18 30 #define STM32_SPDIFRX_VERR 0x3F4 31 #define STM32_SPDIFRX_IDR 0x3F8 32 #define STM32_SPDIFRX_SIDR 0x3FC 33 34 /* Bit definition for SPDIF_CR register */ 35 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 36 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 37 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 38 39 #define SPDIFRX_CR_RXDMAEN BIT(2) 40 #define SPDIFRX_CR_RXSTEO BIT(3) 41 42 #define SPDIFRX_CR_DRFMT_SHIFT 4 43 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 44 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 45 46 #define SPDIFRX_CR_PMSK BIT(6) 47 #define SPDIFRX_CR_VMSK BIT(7) 48 #define SPDIFRX_CR_CUMSK BIT(8) 49 #define SPDIFRX_CR_PTMSK BIT(9) 50 #define SPDIFRX_CR_CBDMAEN BIT(10) 51 #define SPDIFRX_CR_CHSEL_SHIFT 11 52 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 53 54 #define SPDIFRX_CR_NBTR_SHIFT 12 55 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 56 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 57 58 #define SPDIFRX_CR_WFA BIT(14) 59 60 #define SPDIFRX_CR_INSEL_SHIFT 16 61 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 62 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 63 64 #define SPDIFRX_CR_CKSEN_SHIFT 20 65 #define SPDIFRX_CR_CKSEN BIT(20) 66 #define SPDIFRX_CR_CKSBKPEN BIT(21) 67 68 /* Bit definition for SPDIFRX_IMR register */ 69 #define SPDIFRX_IMR_RXNEI BIT(0) 70 #define SPDIFRX_IMR_CSRNEIE BIT(1) 71 #define SPDIFRX_IMR_PERRIE BIT(2) 72 #define SPDIFRX_IMR_OVRIE BIT(3) 73 #define SPDIFRX_IMR_SBLKIE BIT(4) 74 #define SPDIFRX_IMR_SYNCDIE BIT(5) 75 #define SPDIFRX_IMR_IFEIE BIT(6) 76 77 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 78 79 /* Bit definition for SPDIFRX_SR register */ 80 #define SPDIFRX_SR_RXNE BIT(0) 81 #define SPDIFRX_SR_CSRNE BIT(1) 82 #define SPDIFRX_SR_PERR BIT(2) 83 #define SPDIFRX_SR_OVR BIT(3) 84 #define SPDIFRX_SR_SBD BIT(4) 85 #define SPDIFRX_SR_SYNCD BIT(5) 86 #define SPDIFRX_SR_FERR BIT(6) 87 #define SPDIFRX_SR_SERR BIT(7) 88 #define SPDIFRX_SR_TERR BIT(8) 89 90 #define SPDIFRX_SR_WIDTH5_SHIFT 16 91 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 92 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 93 94 /* Bit definition for SPDIFRX_IFCR register */ 95 #define SPDIFRX_IFCR_PERRCF BIT(2) 96 #define SPDIFRX_IFCR_OVRCF BIT(3) 97 #define SPDIFRX_IFCR_SBDCF BIT(4) 98 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 99 100 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 101 102 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 103 #define SPDIFRX_DR0_DR_SHIFT 0 104 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 105 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 106 107 #define SPDIFRX_DR0_PE BIT(24) 108 109 #define SPDIFRX_DR0_V BIT(25) 110 #define SPDIFRX_DR0_U BIT(26) 111 #define SPDIFRX_DR0_C BIT(27) 112 113 #define SPDIFRX_DR0_PT_SHIFT 28 114 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 115 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 116 117 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 118 #define SPDIFRX_DR1_PE BIT(0) 119 #define SPDIFRX_DR1_V BIT(1) 120 #define SPDIFRX_DR1_U BIT(2) 121 #define SPDIFRX_DR1_C BIT(3) 122 123 #define SPDIFRX_DR1_PT_SHIFT 4 124 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 125 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 126 127 #define SPDIFRX_DR1_DR_SHIFT 8 128 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 129 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 130 131 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 132 #define SPDIFRX_DR1_DRNL1_SHIFT 0 133 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 134 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 135 136 #define SPDIFRX_DR1_DRNL2_SHIFT 16 137 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 138 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 139 140 /* Bit definition for SPDIFRX_CSR register */ 141 #define SPDIFRX_CSR_USR_SHIFT 0 142 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 143 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 144 >> SPDIFRX_CSR_USR_SHIFT) 145 146 #define SPDIFRX_CSR_CS_SHIFT 16 147 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 148 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 149 >> SPDIFRX_CSR_CS_SHIFT) 150 151 #define SPDIFRX_CSR_SOB BIT(24) 152 153 /* Bit definition for SPDIFRX_DIR register */ 154 #define SPDIFRX_DIR_THI_SHIFT 0 155 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 156 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 157 158 #define SPDIFRX_DIR_TLO_SHIFT 16 159 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 160 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 161 162 #define SPDIFRX_SPDIFEN_DISABLE 0x0 163 #define SPDIFRX_SPDIFEN_SYNC 0x1 164 #define SPDIFRX_SPDIFEN_ENABLE 0x3 165 166 /* Bit definition for SPDIFRX_VERR register */ 167 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 168 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 169 170 /* Bit definition for SPDIFRX_IDR register */ 171 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 172 173 /* Bit definition for SPDIFRX_SIDR register */ 174 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 175 176 #define SPDIFRX_IPIDR_NUMBER 0x00130041 177 178 #define SPDIFRX_IN1 0x1 179 #define SPDIFRX_IN2 0x2 180 #define SPDIFRX_IN3 0x3 181 #define SPDIFRX_IN4 0x4 182 #define SPDIFRX_IN5 0x5 183 #define SPDIFRX_IN6 0x6 184 #define SPDIFRX_IN7 0x7 185 #define SPDIFRX_IN8 0x8 186 187 #define SPDIFRX_NBTR_NONE 0x0 188 #define SPDIFRX_NBTR_3 0x1 189 #define SPDIFRX_NBTR_15 0x2 190 #define SPDIFRX_NBTR_63 0x3 191 192 #define SPDIFRX_DRFMT_RIGHT 0x0 193 #define SPDIFRX_DRFMT_LEFT 0x1 194 #define SPDIFRX_DRFMT_PACKED 0x2 195 196 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 197 #define SPDIFRX_CS_BYTES_NB 24 198 #define SPDIFRX_UB_BYTES_NB 48 199 200 /* 201 * CSR register is retrieved as a 32 bits word 202 * It contains 1 channel status byte and 2 user data bytes 203 * 2 S/PDIF frames are acquired to get all CS/UB bits 204 */ 205 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 206 207 /** 208 * struct stm32_spdifrx_data - private data of SPDIFRX 209 * @pdev: device data pointer 210 * @base: mmio register base virtual address 211 * @regmap: SPDIFRX register map pointer 212 * @regmap_conf: SPDIFRX register map configuration pointer 213 * @cs_completion: channel status retrieving completion 214 * @kclk: kernel clock feeding the SPDIFRX clock generator 215 * @dma_params: dma configuration data for rx channel 216 * @substream: PCM substream data pointer 217 * @dmab: dma buffer info pointer 218 * @ctrl_chan: dma channel for S/PDIF control bits 219 * @desc:dma async transaction descriptor 220 * @slave_config: dma slave channel runtime config pointer 221 * @phys_addr: SPDIFRX registers physical base address 222 * @lock: synchronization enabling lock 223 * @cs: channel status buffer 224 * @ub: user data buffer 225 * @irq: SPDIFRX interrupt line 226 * @refcount: keep count of opened DMA channels 227 */ 228 struct stm32_spdifrx_data { 229 struct platform_device *pdev; 230 void __iomem *base; 231 struct regmap *regmap; 232 const struct regmap_config *regmap_conf; 233 struct completion cs_completion; 234 struct clk *kclk; 235 struct snd_dmaengine_dai_dma_data dma_params; 236 struct snd_pcm_substream *substream; 237 struct snd_dma_buffer *dmab; 238 struct dma_chan *ctrl_chan; 239 struct dma_async_tx_descriptor *desc; 240 struct dma_slave_config slave_config; 241 dma_addr_t phys_addr; 242 spinlock_t lock; /* Sync enabling lock */ 243 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 244 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 245 int irq; 246 int refcount; 247 }; 248 249 static void stm32_spdifrx_dma_complete(void *data) 250 { 251 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 252 struct platform_device *pdev = spdifrx->pdev; 253 u32 *p_start = (u32 *)spdifrx->dmab->area; 254 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 255 u32 *ptr = p_start; 256 u16 *ub_ptr = (short *)spdifrx->ub; 257 int i = 0; 258 259 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 260 SPDIFRX_CR_CBDMAEN, 261 (unsigned int)~SPDIFRX_CR_CBDMAEN); 262 263 if (!spdifrx->dmab->area) 264 return; 265 266 while (ptr <= p_end) { 267 if (*ptr & SPDIFRX_CSR_SOB) 268 break; 269 ptr++; 270 } 271 272 if (ptr > p_end) { 273 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 274 return; 275 } 276 277 while (i < SPDIFRX_CS_BYTES_NB) { 278 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 279 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 280 if (ptr > p_end) { 281 dev_err(&pdev->dev, "Failed to get channel status\n"); 282 return; 283 } 284 i++; 285 } 286 287 complete(&spdifrx->cs_completion); 288 } 289 290 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 291 { 292 dma_cookie_t cookie; 293 int err; 294 295 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 296 spdifrx->dmab->addr, 297 SPDIFRX_CSR_BUF_LENGTH, 298 DMA_DEV_TO_MEM, 299 DMA_CTRL_ACK); 300 if (!spdifrx->desc) 301 return -EINVAL; 302 303 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 304 spdifrx->desc->callback_param = spdifrx; 305 cookie = dmaengine_submit(spdifrx->desc); 306 err = dma_submit_error(cookie); 307 if (err) 308 return -EINVAL; 309 310 dma_async_issue_pending(spdifrx->ctrl_chan); 311 312 return 0; 313 } 314 315 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 316 { 317 dmaengine_terminate_async(spdifrx->ctrl_chan); 318 } 319 320 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 321 { 322 int cr, cr_mask, imr, ret; 323 324 /* Enable IRQs */ 325 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 326 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 327 if (ret) 328 return ret; 329 330 spin_lock(&spdifrx->lock); 331 332 spdifrx->refcount++; 333 334 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 335 336 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 337 /* 338 * Start sync if SPDIFRX is still in idle state. 339 * SPDIFRX reception enabled when sync done 340 */ 341 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 342 343 /* 344 * SPDIFRX configuration: 345 * Wait for activity before starting sync process. This avoid 346 * to issue sync errors when spdif signal is missing on input. 347 * Preamble, CS, user, validity and parity error bits not copied 348 * to DR register. 349 */ 350 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 351 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 352 cr_mask = cr; 353 354 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63); 355 cr_mask |= SPDIFRX_CR_NBTR_MASK; 356 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 357 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 358 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 359 cr_mask, cr); 360 if (ret < 0) 361 dev_err(&spdifrx->pdev->dev, 362 "Failed to start synchronization\n"); 363 } 364 365 spin_unlock(&spdifrx->lock); 366 367 return ret; 368 } 369 370 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 371 { 372 int cr, cr_mask, reg; 373 374 spin_lock(&spdifrx->lock); 375 376 if (--spdifrx->refcount) { 377 spin_unlock(&spdifrx->lock); 378 return; 379 } 380 381 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 382 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 383 384 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 385 386 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 387 SPDIFRX_XIMR_MASK, 0); 388 389 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 390 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 391 392 /* dummy read to clear CSRNE and RXNE in status register */ 393 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 394 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 395 396 spin_unlock(&spdifrx->lock); 397 } 398 399 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 400 struct stm32_spdifrx_data *spdifrx) 401 { 402 int ret; 403 404 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 405 if (IS_ERR(spdifrx->ctrl_chan)) { 406 dev_err(dev, "dma_request_slave_channel failed\n"); 407 return PTR_ERR(spdifrx->ctrl_chan); 408 } 409 410 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 411 GFP_KERNEL); 412 if (!spdifrx->dmab) 413 return -ENOMEM; 414 415 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 416 spdifrx->dmab->dev.dev = dev; 417 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 418 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 419 if (ret < 0) { 420 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 421 return ret; 422 } 423 424 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 425 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 426 STM32_SPDIFRX_CSR); 427 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 428 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 429 spdifrx->slave_config.src_maxburst = 1; 430 431 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 432 &spdifrx->slave_config); 433 if (ret < 0) { 434 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 435 spdifrx->ctrl_chan = NULL; 436 } 437 438 return ret; 439 }; 440 441 static const char * const spdifrx_enum_input[] = { 442 "in0", "in1", "in2", "in3" 443 }; 444 445 /* By default CS bits are retrieved from channel A */ 446 static const char * const spdifrx_enum_cs_channel[] = { 447 "A", "B" 448 }; 449 450 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 451 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 452 spdifrx_enum_input); 453 454 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 455 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 456 spdifrx_enum_cs_channel); 457 458 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 459 struct snd_ctl_elem_info *uinfo) 460 { 461 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 462 uinfo->count = 1; 463 464 return 0; 465 } 466 467 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 468 struct snd_ctl_elem_info *uinfo) 469 { 470 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 471 uinfo->count = 1; 472 473 return 0; 474 } 475 476 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 477 { 478 int ret = 0; 479 480 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 481 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 482 483 pinctrl_pm_select_default_state(&spdifrx->pdev->dev); 484 485 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 486 if (ret < 0) 487 return ret; 488 489 ret = clk_prepare_enable(spdifrx->kclk); 490 if (ret) { 491 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 492 return ret; 493 } 494 495 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 496 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 497 if (ret < 0) 498 goto end; 499 500 ret = stm32_spdifrx_start_sync(spdifrx); 501 if (ret < 0) 502 goto end; 503 504 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 505 msecs_to_jiffies(100)) 506 <= 0) { 507 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n"); 508 ret = -EAGAIN; 509 } 510 511 stm32_spdifrx_stop(spdifrx); 512 stm32_spdifrx_dma_ctrl_stop(spdifrx); 513 514 end: 515 clk_disable_unprepare(spdifrx->kclk); 516 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev); 517 518 return ret; 519 } 520 521 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 522 struct snd_ctl_elem_value *ucontrol) 523 { 524 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 525 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 526 527 stm32_spdifrx_get_ctrl_data(spdifrx); 528 529 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 530 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 531 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 532 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 533 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 534 535 return 0; 536 } 537 538 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 539 struct snd_ctl_elem_value *ucontrol) 540 { 541 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 542 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 543 544 stm32_spdifrx_get_ctrl_data(spdifrx); 545 546 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 547 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 548 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 549 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 550 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 551 552 return 0; 553 } 554 555 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 556 /* Channel status control */ 557 { 558 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 559 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 560 .access = SNDRV_CTL_ELEM_ACCESS_READ | 561 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 562 .info = stm32_spdifrx_info, 563 .get = stm32_spdifrx_capture_get, 564 }, 565 /* User bits control */ 566 { 567 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 568 .name = "IEC958 User Bit Capture Default", 569 .access = SNDRV_CTL_ELEM_ACCESS_READ | 570 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 571 .info = stm32_spdifrx_ub_info, 572 .get = stm32_spdif_user_bits_get, 573 }, 574 }; 575 576 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 577 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 578 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 579 }; 580 581 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 582 { 583 int ret; 584 585 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 586 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 587 if (ret < 0) 588 return ret; 589 590 return snd_soc_add_component_controls(cpu_dai->component, 591 stm32_spdifrx_ctrls, 592 ARRAY_SIZE(stm32_spdifrx_ctrls)); 593 } 594 595 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 596 { 597 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 598 599 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 600 STM32_SPDIFRX_DR); 601 spdifrx->dma_params.maxburst = 1; 602 603 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 604 605 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 606 } 607 608 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 609 { 610 switch (reg) { 611 case STM32_SPDIFRX_CR: 612 case STM32_SPDIFRX_IMR: 613 case STM32_SPDIFRX_SR: 614 case STM32_SPDIFRX_IFCR: 615 case STM32_SPDIFRX_DR: 616 case STM32_SPDIFRX_CSR: 617 case STM32_SPDIFRX_DIR: 618 case STM32_SPDIFRX_VERR: 619 case STM32_SPDIFRX_IDR: 620 case STM32_SPDIFRX_SIDR: 621 return true; 622 default: 623 return false; 624 } 625 } 626 627 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 628 { 629 switch (reg) { 630 case STM32_SPDIFRX_DR: 631 case STM32_SPDIFRX_CSR: 632 case STM32_SPDIFRX_SR: 633 case STM32_SPDIFRX_DIR: 634 return true; 635 default: 636 return false; 637 } 638 } 639 640 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 641 { 642 switch (reg) { 643 case STM32_SPDIFRX_CR: 644 case STM32_SPDIFRX_IMR: 645 case STM32_SPDIFRX_IFCR: 646 return true; 647 default: 648 return false; 649 } 650 } 651 652 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 653 .reg_bits = 32, 654 .reg_stride = 4, 655 .val_bits = 32, 656 .max_register = STM32_SPDIFRX_SIDR, 657 .readable_reg = stm32_spdifrx_readable_reg, 658 .volatile_reg = stm32_spdifrx_volatile_reg, 659 .writeable_reg = stm32_spdifrx_writeable_reg, 660 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 661 .fast_io = true, 662 .cache_type = REGCACHE_FLAT, 663 }; 664 665 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 666 { 667 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 668 struct snd_pcm_substream *substream = spdifrx->substream; 669 struct platform_device *pdev = spdifrx->pdev; 670 unsigned int cr, mask, sr, imr; 671 unsigned int flags, sync_state; 672 int err = 0, err_xrun = 0; 673 674 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 675 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 676 677 mask = imr & SPDIFRX_XIMR_MASK; 678 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 679 if (mask & SPDIFRX_IMR_IFEIE) 680 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 681 682 flags = sr & mask; 683 if (!flags) { 684 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 685 sr, imr); 686 return IRQ_NONE; 687 } 688 689 /* Clear IRQs */ 690 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 691 SPDIFRX_XIFCR_MASK, flags); 692 693 if (flags & SPDIFRX_SR_PERR) { 694 dev_dbg(&pdev->dev, "Parity error\n"); 695 err_xrun = 1; 696 } 697 698 if (flags & SPDIFRX_SR_OVR) { 699 dev_dbg(&pdev->dev, "Overrun error\n"); 700 err_xrun = 1; 701 } 702 703 if (flags & SPDIFRX_SR_SBD) 704 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 705 706 if (flags & SPDIFRX_SR_SYNCD) { 707 dev_dbg(&pdev->dev, "Synchronization done\n"); 708 709 /* Enable spdifrx */ 710 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 711 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 712 SPDIFRX_CR_SPDIFEN_MASK, cr); 713 } 714 715 if (flags & SPDIFRX_SR_FERR) { 716 dev_dbg(&pdev->dev, "Frame error\n"); 717 err = 1; 718 } 719 720 if (flags & SPDIFRX_SR_SERR) { 721 dev_dbg(&pdev->dev, "Synchronization error\n"); 722 err = 1; 723 } 724 725 if (flags & SPDIFRX_SR_TERR) { 726 dev_dbg(&pdev->dev, "Timeout error\n"); 727 err = 1; 728 } 729 730 if (err) { 731 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 732 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) && 733 SPDIFRX_SPDIFEN_SYNC; 734 735 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */ 736 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 737 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 738 SPDIFRX_CR_SPDIFEN_MASK, cr); 739 740 /* If SPDIFRX was in STATE_SYNC, retry synchro */ 741 if (sync_state) { 742 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 743 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 744 SPDIFRX_CR_SPDIFEN_MASK, cr); 745 return IRQ_HANDLED; 746 } 747 748 if (substream) 749 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 750 751 return IRQ_HANDLED; 752 } 753 754 if (err_xrun && substream) 755 snd_pcm_stop_xrun(substream); 756 757 return IRQ_HANDLED; 758 } 759 760 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 761 struct snd_soc_dai *cpu_dai) 762 { 763 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 764 int ret; 765 766 spdifrx->substream = substream; 767 768 ret = clk_prepare_enable(spdifrx->kclk); 769 if (ret) 770 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 771 772 return ret; 773 } 774 775 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 776 struct snd_pcm_hw_params *params, 777 struct snd_soc_dai *cpu_dai) 778 { 779 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 780 int data_size = params_width(params); 781 int fmt; 782 783 switch (data_size) { 784 case 16: 785 fmt = SPDIFRX_DRFMT_PACKED; 786 break; 787 case 32: 788 fmt = SPDIFRX_DRFMT_LEFT; 789 break; 790 default: 791 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 792 return -EINVAL; 793 } 794 795 /* 796 * Set buswidth to 4 bytes for all data formats. 797 * Packed format: transfer 2 x 2 bytes samples 798 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 799 */ 800 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 801 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 802 803 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 804 SPDIFRX_CR_DRFMT_MASK, 805 SPDIFRX_CR_DRFMTSET(fmt)); 806 } 807 808 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 809 struct snd_soc_dai *cpu_dai) 810 { 811 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 812 int ret = 0; 813 814 switch (cmd) { 815 case SNDRV_PCM_TRIGGER_START: 816 case SNDRV_PCM_TRIGGER_RESUME: 817 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 818 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 819 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 820 821 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 822 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 823 824 ret = stm32_spdifrx_start_sync(spdifrx); 825 break; 826 case SNDRV_PCM_TRIGGER_SUSPEND: 827 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 828 case SNDRV_PCM_TRIGGER_STOP: 829 stm32_spdifrx_stop(spdifrx); 830 break; 831 default: 832 return -EINVAL; 833 } 834 835 return ret; 836 } 837 838 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 839 struct snd_soc_dai *cpu_dai) 840 { 841 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 842 843 spdifrx->substream = NULL; 844 clk_disable_unprepare(spdifrx->kclk); 845 } 846 847 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 848 .startup = stm32_spdifrx_startup, 849 .hw_params = stm32_spdifrx_hw_params, 850 .trigger = stm32_spdifrx_trigger, 851 .shutdown = stm32_spdifrx_shutdown, 852 }; 853 854 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 855 { 856 .probe = stm32_spdifrx_dai_probe, 857 .capture = { 858 .stream_name = "CPU-Capture", 859 .channels_min = 1, 860 .channels_max = 2, 861 .rates = SNDRV_PCM_RATE_8000_192000, 862 .formats = SNDRV_PCM_FMTBIT_S32_LE | 863 SNDRV_PCM_FMTBIT_S16_LE, 864 }, 865 .ops = &stm32_spdifrx_pcm_dai_ops, 866 } 867 }; 868 869 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 870 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 871 .buffer_bytes_max = 8 * PAGE_SIZE, 872 .period_bytes_min = 1024, 873 .period_bytes_max = 4 * PAGE_SIZE, 874 .periods_min = 2, 875 .periods_max = 8, 876 }; 877 878 static const struct snd_soc_component_driver stm32_spdifrx_component = { 879 .name = "stm32-spdifrx", 880 }; 881 882 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 883 .pcm_hardware = &stm32_spdifrx_pcm_hw, 884 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 885 }; 886 887 static const struct of_device_id stm32_spdifrx_ids[] = { 888 { 889 .compatible = "st,stm32h7-spdifrx", 890 .data = &stm32_h7_spdifrx_regmap_conf 891 }, 892 {} 893 }; 894 895 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 896 struct stm32_spdifrx_data *spdifrx) 897 { 898 struct device_node *np = pdev->dev.of_node; 899 const struct of_device_id *of_id; 900 struct resource *res; 901 902 if (!np) 903 return -ENODEV; 904 905 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 906 if (of_id) 907 spdifrx->regmap_conf = 908 (const struct regmap_config *)of_id->data; 909 else 910 return -EINVAL; 911 912 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 913 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 914 if (IS_ERR(spdifrx->base)) 915 return PTR_ERR(spdifrx->base); 916 917 spdifrx->phys_addr = res->start; 918 919 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 920 if (IS_ERR(spdifrx->kclk)) { 921 dev_err(&pdev->dev, "Could not get kclk\n"); 922 return PTR_ERR(spdifrx->kclk); 923 } 924 925 spdifrx->irq = platform_get_irq(pdev, 0); 926 if (spdifrx->irq < 0) 927 return spdifrx->irq; 928 929 return 0; 930 } 931 932 static int stm32_spdifrx_probe(struct platform_device *pdev) 933 { 934 struct stm32_spdifrx_data *spdifrx; 935 struct reset_control *rst; 936 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 937 u32 ver, idr; 938 int ret; 939 940 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 941 if (!spdifrx) 942 return -ENOMEM; 943 944 spdifrx->pdev = pdev; 945 init_completion(&spdifrx->cs_completion); 946 spin_lock_init(&spdifrx->lock); 947 948 platform_set_drvdata(pdev, spdifrx); 949 950 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 951 if (ret) 952 return ret; 953 954 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 955 spdifrx->base, 956 spdifrx->regmap_conf); 957 if (IS_ERR(spdifrx->regmap)) { 958 dev_err(&pdev->dev, "Regmap init failed\n"); 959 return PTR_ERR(spdifrx->regmap); 960 } 961 962 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 963 dev_name(&pdev->dev), spdifrx); 964 if (ret) { 965 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 966 return ret; 967 } 968 969 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 970 if (!IS_ERR(rst)) { 971 reset_control_assert(rst); 972 udelay(2); 973 reset_control_deassert(rst); 974 } 975 976 ret = devm_snd_soc_register_component(&pdev->dev, 977 &stm32_spdifrx_component, 978 stm32_spdifrx_dai, 979 ARRAY_SIZE(stm32_spdifrx_dai)); 980 if (ret) 981 return ret; 982 983 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 984 if (ret) 985 goto error; 986 987 pcm_config = &stm32_spdifrx_pcm_config; 988 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 989 if (ret) { 990 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 991 goto error; 992 } 993 994 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 995 if (ret) 996 goto error; 997 998 if (idr == SPDIFRX_IPIDR_NUMBER) { 999 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 1000 1001 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 1002 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 1003 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 1004 } 1005 1006 return ret; 1007 1008 error: 1009 if (!IS_ERR(spdifrx->ctrl_chan)) 1010 dma_release_channel(spdifrx->ctrl_chan); 1011 if (spdifrx->dmab) 1012 snd_dma_free_pages(spdifrx->dmab); 1013 1014 return ret; 1015 } 1016 1017 static int stm32_spdifrx_remove(struct platform_device *pdev) 1018 { 1019 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 1020 1021 if (spdifrx->ctrl_chan) 1022 dma_release_channel(spdifrx->ctrl_chan); 1023 1024 if (spdifrx->dmab) 1025 snd_dma_free_pages(spdifrx->dmab); 1026 1027 return 0; 1028 } 1029 1030 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1031 1032 #ifdef CONFIG_PM_SLEEP 1033 static int stm32_spdifrx_suspend(struct device *dev) 1034 { 1035 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1036 1037 regcache_cache_only(spdifrx->regmap, true); 1038 regcache_mark_dirty(spdifrx->regmap); 1039 1040 return 0; 1041 } 1042 1043 static int stm32_spdifrx_resume(struct device *dev) 1044 { 1045 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1046 1047 regcache_cache_only(spdifrx->regmap, false); 1048 1049 return regcache_sync(spdifrx->regmap); 1050 } 1051 #endif /* CONFIG_PM_SLEEP */ 1052 1053 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1054 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1055 }; 1056 1057 static struct platform_driver stm32_spdifrx_driver = { 1058 .driver = { 1059 .name = "st,stm32-spdifrx", 1060 .of_match_table = stm32_spdifrx_ids, 1061 .pm = &stm32_spdifrx_pm_ops, 1062 }, 1063 .probe = stm32_spdifrx_probe, 1064 .remove = stm32_spdifrx_remove, 1065 }; 1066 1067 module_platform_driver(stm32_spdifrx_driver); 1068 1069 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1070 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1071 MODULE_ALIAS("platform:stm32-spdifrx"); 1072 MODULE_LICENSE("GPL v2"); 1073