1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xtfpga I2S controller driver 4 * 5 * Copyright (c) 2014 Cadence Design Systems Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <sound/pcm_params.h> 15 #include <sound/soc.h> 16 17 #define DRV_NAME "xtfpga-i2s" 18 19 #define XTFPGA_I2S_VERSION 0x00 20 #define XTFPGA_I2S_CONFIG 0x04 21 #define XTFPGA_I2S_INT_MASK 0x08 22 #define XTFPGA_I2S_INT_STATUS 0x0c 23 #define XTFPGA_I2S_CHAN0_DATA 0x10 24 #define XTFPGA_I2S_CHAN1_DATA 0x14 25 #define XTFPGA_I2S_CHAN2_DATA 0x18 26 #define XTFPGA_I2S_CHAN3_DATA 0x1c 27 28 #define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1 29 #define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2 30 #define XTFPGA_I2S_CONFIG_LEFT 0x4 31 #define XTFPGA_I2S_CONFIG_RATIO_BASE 8 32 #define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00 33 #define XTFPGA_I2S_CONFIG_RES_BASE 16 34 #define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000 35 #define XTFPGA_I2S_CONFIG_LEVEL_BASE 24 36 #define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000 37 #define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28 38 39 #define XTFPGA_I2S_INT_UNDERRUN 0x1 40 #define XTFPGA_I2S_INT_LEVEL 0x2 41 #define XTFPGA_I2S_INT_VALID 0x3 42 43 #define XTFPGA_I2S_FIFO_SIZE 8192 44 45 /* 46 * I2S controller operation: 47 * 48 * Enabling TX: output 1 period of zeros (starting with left channel) 49 * and then queued data. 50 * 51 * Level status and interrupt: whenever FIFO level is below FIFO trigger, 52 * level status is 1 and an IRQ is asserted (if enabled). 53 * 54 * Underrun status and interrupt: whenever FIFO is empty, underrun status 55 * is 1 and an IRQ is asserted (if enabled). 56 */ 57 struct xtfpga_i2s { 58 struct device *dev; 59 struct clk *clk; 60 struct regmap *regmap; 61 void __iomem *regs; 62 63 /* current playback substream. NULL if not playing. 64 * 65 * Access to that field is synchronized between the interrupt handler 66 * and userspace through RCU. 67 * 68 * Interrupt handler (threaded part) does PIO on substream data in RCU 69 * read-side critical section. Trigger callback sets and clears the 70 * pointer when the playback is started and stopped with 71 * rcu_assign_pointer. When userspace is about to free the playback 72 * stream in the pcm_close callback it synchronizes with the interrupt 73 * handler by means of synchronize_rcu call. 74 */ 75 struct snd_pcm_substream __rcu *tx_substream; 76 unsigned (*tx_fn)(struct xtfpga_i2s *i2s, 77 struct snd_pcm_runtime *runtime, 78 unsigned tx_ptr); 79 unsigned tx_ptr; /* next frame index in the sample buffer */ 80 81 /* current fifo level estimate. 82 * Doesn't have to be perfectly accurate, but must be not less than 83 * the actual FIFO level in order to avoid stall on push attempt. 84 */ 85 unsigned tx_fifo_level; 86 87 /* FIFO level at which level interrupt occurs */ 88 unsigned tx_fifo_low; 89 90 /* maximal FIFO level */ 91 unsigned tx_fifo_high; 92 }; 93 94 static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg) 95 { 96 return reg >= XTFPGA_I2S_CONFIG; 97 } 98 99 static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg) 100 { 101 return reg < XTFPGA_I2S_CHAN0_DATA; 102 } 103 104 static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg) 105 { 106 return reg == XTFPGA_I2S_INT_STATUS; 107 } 108 109 static const struct regmap_config xtfpga_i2s_regmap_config = { 110 .reg_bits = 32, 111 .reg_stride = 4, 112 .val_bits = 32, 113 .max_register = XTFPGA_I2S_CHAN3_DATA, 114 .writeable_reg = xtfpga_i2s_wr_reg, 115 .readable_reg = xtfpga_i2s_rd_reg, 116 .volatile_reg = xtfpga_i2s_volatile_reg, 117 .cache_type = REGCACHE_FLAT, 118 }; 119 120 /* Generate functions that do PIO from TX DMA area to FIFO for all supported 121 * stream formats. 122 * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g. 123 * xtfpga_pcm_tx_2x16 for 16-bit stereo. 124 * 125 * FIFO consists of 32-bit words, one word per channel, always 2 channels. 126 * If I2S interface is configured with smaller sample resolution, only 127 * the LSB of each word is used. 128 */ 129 #define xtfpga_pcm_tx_fn(channels, sample_bits) \ 130 static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \ 131 struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \ 132 unsigned tx_ptr) \ 133 { \ 134 const u##sample_bits (*p)[channels] = \ 135 (void *)runtime->dma_area; \ 136 \ 137 for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \ 138 i2s->tx_fifo_level += 2) { \ 139 iowrite32(p[tx_ptr][0], \ 140 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \ 141 iowrite32(p[tx_ptr][channels - 1], \ 142 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \ 143 if (++tx_ptr >= runtime->buffer_size) \ 144 tx_ptr = 0; \ 145 } \ 146 return tx_ptr; \ 147 } 148 149 xtfpga_pcm_tx_fn(1, 16) 150 xtfpga_pcm_tx_fn(2, 16) 151 xtfpga_pcm_tx_fn(1, 32) 152 xtfpga_pcm_tx_fn(2, 32) 153 154 #undef xtfpga_pcm_tx_fn 155 156 static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s) 157 { 158 struct snd_pcm_substream *tx_substream; 159 bool tx_active; 160 161 rcu_read_lock(); 162 tx_substream = rcu_dereference(i2s->tx_substream); 163 tx_active = tx_substream && snd_pcm_running(tx_substream); 164 if (tx_active) { 165 unsigned tx_ptr = READ_ONCE(i2s->tx_ptr); 166 unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime, 167 tx_ptr); 168 169 cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr); 170 } 171 rcu_read_unlock(); 172 173 return tx_active; 174 } 175 176 static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s) 177 { 178 unsigned int_status; 179 unsigned i; 180 181 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, 182 &int_status); 183 184 for (i = 0; i < 2; ++i) { 185 bool tx_active = xtfpga_pcm_push_tx(i2s); 186 187 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, 188 XTFPGA_I2S_INT_VALID); 189 if (tx_active) 190 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, 191 &int_status); 192 193 if (!tx_active || 194 !(int_status & XTFPGA_I2S_INT_LEVEL)) 195 break; 196 197 /* After the push the level IRQ is still asserted, 198 * means FIFO level is below tx_fifo_low. Estimate 199 * it as tx_fifo_low. 200 */ 201 i2s->tx_fifo_level = i2s->tx_fifo_low; 202 } 203 204 if (!(int_status & XTFPGA_I2S_INT_LEVEL)) 205 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 206 XTFPGA_I2S_INT_VALID); 207 else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN)) 208 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 209 XTFPGA_I2S_INT_UNDERRUN); 210 211 if (!(int_status & XTFPGA_I2S_INT_UNDERRUN)) 212 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 213 XTFPGA_I2S_CONFIG_INT_ENABLE | 214 XTFPGA_I2S_CONFIG_TX_ENABLE, 215 XTFPGA_I2S_CONFIG_INT_ENABLE | 216 XTFPGA_I2S_CONFIG_TX_ENABLE); 217 else 218 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 219 XTFPGA_I2S_CONFIG_INT_ENABLE | 220 XTFPGA_I2S_CONFIG_TX_ENABLE, 0); 221 } 222 223 static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id) 224 { 225 struct xtfpga_i2s *i2s = dev_id; 226 struct snd_pcm_substream *tx_substream; 227 unsigned config, int_status, int_mask; 228 229 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config); 230 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask); 231 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status); 232 233 if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) || 234 !(int_status & int_mask & XTFPGA_I2S_INT_VALID)) 235 return IRQ_NONE; 236 237 /* Update FIFO level estimate in accordance with interrupt status 238 * register. 239 */ 240 if (int_status & XTFPGA_I2S_INT_UNDERRUN) { 241 i2s->tx_fifo_level = 0; 242 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 243 XTFPGA_I2S_CONFIG_TX_ENABLE, 0); 244 } else { 245 /* The FIFO isn't empty, but is below tx_fifo_low. Estimate 246 * it as tx_fifo_low. 247 */ 248 i2s->tx_fifo_level = i2s->tx_fifo_low; 249 } 250 251 rcu_read_lock(); 252 tx_substream = rcu_dereference(i2s->tx_substream); 253 254 if (tx_substream && snd_pcm_running(tx_substream)) { 255 snd_pcm_period_elapsed(tx_substream); 256 if (int_status & XTFPGA_I2S_INT_UNDERRUN) 257 dev_dbg_ratelimited(i2s->dev, "%s: underrun\n", 258 __func__); 259 } 260 rcu_read_unlock(); 261 262 /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is 263 * not empty. 264 */ 265 xtfpga_pcm_refill_fifo(i2s); 266 267 return IRQ_HANDLED; 268 } 269 270 static int xtfpga_i2s_startup(struct snd_pcm_substream *substream, 271 struct snd_soc_dai *dai) 272 { 273 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai); 274 275 snd_soc_dai_set_dma_data(dai, substream, i2s); 276 return 0; 277 } 278 279 static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream, 280 struct snd_pcm_hw_params *params, 281 struct snd_soc_dai *dai) 282 { 283 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai); 284 unsigned srate = params_rate(params); 285 unsigned channels = params_channels(params); 286 unsigned period_size = params_period_size(params); 287 unsigned sample_size = snd_pcm_format_width(params_format(params)); 288 unsigned freq, ratio, level; 289 int err; 290 291 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 292 XTFPGA_I2S_CONFIG_RES_MASK, 293 sample_size << XTFPGA_I2S_CONFIG_RES_BASE); 294 295 freq = 256 * srate; 296 err = clk_set_rate(i2s->clk, freq); 297 if (err < 0) 298 return err; 299 300 /* ratio field of the config register controls MCLK->I2S clock 301 * derivation: I2S clock = MCLK / (2 * (ratio + 2)). 302 * 303 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo 304 * and 2 for 16 bit stereo. 305 */ 306 ratio = (freq - (srate * sample_size * 8)) / 307 (srate * sample_size * 4); 308 309 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 310 XTFPGA_I2S_CONFIG_RATIO_MASK, 311 ratio << XTFPGA_I2S_CONFIG_RATIO_BASE); 312 313 i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2; 314 315 /* period_size * 2: FIFO always gets 2 samples per frame */ 316 for (level = 1; 317 i2s->tx_fifo_low / 2 >= period_size * 2 && 318 level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >> 319 XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level) 320 i2s->tx_fifo_low /= 2; 321 322 i2s->tx_fifo_high = 2 * i2s->tx_fifo_low; 323 324 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, 325 XTFPGA_I2S_CONFIG_LEVEL_MASK, 326 level << XTFPGA_I2S_CONFIG_LEVEL_BASE); 327 328 dev_dbg(i2s->dev, 329 "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n", 330 __func__, srate, channels, sample_size, period_size); 331 dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n", 332 __func__, freq, ratio, level); 333 334 return 0; 335 } 336 337 static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 338 unsigned int fmt) 339 { 340 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) 341 return -EINVAL; 342 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 343 return -EINVAL; 344 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) 345 return -EINVAL; 346 347 return 0; 348 } 349 350 /* PCM */ 351 352 static const struct snd_pcm_hardware xtfpga_pcm_hardware = { 353 .info = SNDRV_PCM_INFO_INTERLEAVED | 354 SNDRV_PCM_INFO_MMAP_VALID | 355 SNDRV_PCM_INFO_BLOCK_TRANSFER, 356 .formats = SNDRV_PCM_FMTBIT_S16_LE | 357 SNDRV_PCM_FMTBIT_S32_LE, 358 .channels_min = 1, 359 .channels_max = 2, 360 .period_bytes_min = 2, 361 .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8, 362 .periods_min = 2, 363 .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2, 364 .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8, 365 .fifo_size = 16, 366 }; 367 368 static int xtfpga_pcm_open(struct snd_pcm_substream *substream) 369 { 370 struct snd_pcm_runtime *runtime = substream->runtime; 371 struct snd_soc_pcm_runtime *rtd = substream->private_data; 372 void *p; 373 374 snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware); 375 p = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); 376 runtime->private_data = p; 377 378 return 0; 379 } 380 381 static int xtfpga_pcm_close(struct snd_pcm_substream *substream) 382 { 383 synchronize_rcu(); 384 return 0; 385 } 386 387 static int xtfpga_pcm_hw_params(struct snd_pcm_substream *substream, 388 struct snd_pcm_hw_params *hw_params) 389 { 390 int ret; 391 struct snd_pcm_runtime *runtime = substream->runtime; 392 struct xtfpga_i2s *i2s = runtime->private_data; 393 unsigned channels = params_channels(hw_params); 394 395 switch (channels) { 396 case 1: 397 case 2: 398 break; 399 400 default: 401 return -EINVAL; 402 403 } 404 405 switch (params_format(hw_params)) { 406 case SNDRV_PCM_FORMAT_S16_LE: 407 i2s->tx_fn = (channels == 1) ? 408 xtfpga_pcm_tx_1x16 : 409 xtfpga_pcm_tx_2x16; 410 break; 411 412 case SNDRV_PCM_FORMAT_S32_LE: 413 i2s->tx_fn = (channels == 1) ? 414 xtfpga_pcm_tx_1x32 : 415 xtfpga_pcm_tx_2x32; 416 break; 417 418 default: 419 return -EINVAL; 420 } 421 422 ret = snd_pcm_lib_malloc_pages(substream, 423 params_buffer_bytes(hw_params)); 424 return ret; 425 } 426 427 static int xtfpga_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 428 { 429 int ret = 0; 430 struct snd_pcm_runtime *runtime = substream->runtime; 431 struct xtfpga_i2s *i2s = runtime->private_data; 432 433 switch (cmd) { 434 case SNDRV_PCM_TRIGGER_START: 435 case SNDRV_PCM_TRIGGER_RESUME: 436 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 437 WRITE_ONCE(i2s->tx_ptr, 0); 438 rcu_assign_pointer(i2s->tx_substream, substream); 439 xtfpga_pcm_refill_fifo(i2s); 440 break; 441 442 case SNDRV_PCM_TRIGGER_STOP: 443 case SNDRV_PCM_TRIGGER_SUSPEND: 444 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 445 rcu_assign_pointer(i2s->tx_substream, NULL); 446 break; 447 448 default: 449 ret = -EINVAL; 450 break; 451 } 452 return ret; 453 } 454 455 static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_pcm_substream *substream) 456 { 457 struct snd_pcm_runtime *runtime = substream->runtime; 458 struct xtfpga_i2s *i2s = runtime->private_data; 459 snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr); 460 461 return pos < runtime->buffer_size ? pos : 0; 462 } 463 464 static int xtfpga_pcm_new(struct snd_soc_pcm_runtime *rtd) 465 { 466 struct snd_card *card = rtd->card->snd_card; 467 size_t size = xtfpga_pcm_hardware.buffer_bytes_max; 468 469 snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 470 card->dev, size, size); 471 return 0; 472 } 473 474 static const struct snd_pcm_ops xtfpga_pcm_ops = { 475 .open = xtfpga_pcm_open, 476 .close = xtfpga_pcm_close, 477 .ioctl = snd_pcm_lib_ioctl, 478 .hw_params = xtfpga_pcm_hw_params, 479 .trigger = xtfpga_pcm_trigger, 480 .pointer = xtfpga_pcm_pointer, 481 }; 482 483 static const struct snd_soc_component_driver xtfpga_i2s_component = { 484 .name = DRV_NAME, 485 .pcm_new = xtfpga_pcm_new, 486 .ops = &xtfpga_pcm_ops, 487 }; 488 489 static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = { 490 .startup = xtfpga_i2s_startup, 491 .hw_params = xtfpga_i2s_hw_params, 492 .set_fmt = xtfpga_i2s_set_fmt, 493 }; 494 495 static struct snd_soc_dai_driver xtfpga_i2s_dai[] = { 496 { 497 .name = "xtfpga-i2s", 498 .id = 0, 499 .playback = { 500 .channels_min = 1, 501 .channels_max = 2, 502 .rates = SNDRV_PCM_RATE_8000_96000, 503 .formats = SNDRV_PCM_FMTBIT_S16_LE | 504 SNDRV_PCM_FMTBIT_S32_LE, 505 }, 506 .ops = &xtfpga_i2s_dai_ops, 507 }, 508 }; 509 510 static int xtfpga_i2s_runtime_suspend(struct device *dev) 511 { 512 struct xtfpga_i2s *i2s = dev_get_drvdata(dev); 513 514 clk_disable_unprepare(i2s->clk); 515 return 0; 516 } 517 518 static int xtfpga_i2s_runtime_resume(struct device *dev) 519 { 520 struct xtfpga_i2s *i2s = dev_get_drvdata(dev); 521 int ret; 522 523 ret = clk_prepare_enable(i2s->clk); 524 if (ret) { 525 dev_err(dev, "clk_prepare_enable failed: %d\n", ret); 526 return ret; 527 } 528 return 0; 529 } 530 531 static int xtfpga_i2s_probe(struct platform_device *pdev) 532 { 533 struct xtfpga_i2s *i2s; 534 struct resource *mem; 535 int err, irq; 536 537 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 538 if (!i2s) { 539 err = -ENOMEM; 540 goto err; 541 } 542 platform_set_drvdata(pdev, i2s); 543 i2s->dev = &pdev->dev; 544 dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s); 545 546 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 547 i2s->regs = devm_ioremap_resource(&pdev->dev, mem); 548 if (IS_ERR(i2s->regs)) { 549 err = PTR_ERR(i2s->regs); 550 goto err; 551 } 552 553 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs, 554 &xtfpga_i2s_regmap_config); 555 if (IS_ERR(i2s->regmap)) { 556 dev_err(&pdev->dev, "regmap init failed\n"); 557 err = PTR_ERR(i2s->regmap); 558 goto err; 559 } 560 561 i2s->clk = devm_clk_get(&pdev->dev, NULL); 562 if (IS_ERR(i2s->clk)) { 563 dev_err(&pdev->dev, "couldn't get clock\n"); 564 err = PTR_ERR(i2s->clk); 565 goto err; 566 } 567 568 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 569 (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE)); 570 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID); 571 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN); 572 573 irq = platform_get_irq(pdev, 0); 574 if (irq < 0) { 575 dev_err(&pdev->dev, "No IRQ resource\n"); 576 err = irq; 577 goto err; 578 } 579 err = devm_request_threaded_irq(&pdev->dev, irq, NULL, 580 xtfpga_i2s_threaded_irq_handler, 581 IRQF_SHARED | IRQF_ONESHOT, 582 pdev->name, i2s); 583 if (err < 0) { 584 dev_err(&pdev->dev, "request_irq failed\n"); 585 goto err; 586 } 587 588 err = devm_snd_soc_register_component(&pdev->dev, 589 &xtfpga_i2s_component, 590 xtfpga_i2s_dai, 591 ARRAY_SIZE(xtfpga_i2s_dai)); 592 if (err < 0) { 593 dev_err(&pdev->dev, "couldn't register component\n"); 594 goto err; 595 } 596 597 pm_runtime_enable(&pdev->dev); 598 if (!pm_runtime_enabled(&pdev->dev)) { 599 err = xtfpga_i2s_runtime_resume(&pdev->dev); 600 if (err) 601 goto err_pm_disable; 602 } 603 return 0; 604 605 err_pm_disable: 606 pm_runtime_disable(&pdev->dev); 607 err: 608 dev_err(&pdev->dev, "%s: err = %d\n", __func__, err); 609 return err; 610 } 611 612 static int xtfpga_i2s_remove(struct platform_device *pdev) 613 { 614 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev); 615 616 if (i2s->regmap && !IS_ERR(i2s->regmap)) { 617 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0); 618 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0); 619 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, 620 XTFPGA_I2S_INT_VALID); 621 } 622 pm_runtime_disable(&pdev->dev); 623 if (!pm_runtime_status_suspended(&pdev->dev)) 624 xtfpga_i2s_runtime_suspend(&pdev->dev); 625 return 0; 626 } 627 628 #ifdef CONFIG_OF 629 static const struct of_device_id xtfpga_i2s_of_match[] = { 630 { .compatible = "cdns,xtfpga-i2s", }, 631 {}, 632 }; 633 MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match); 634 #endif 635 636 static const struct dev_pm_ops xtfpga_i2s_pm_ops = { 637 SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend, 638 xtfpga_i2s_runtime_resume, NULL) 639 }; 640 641 static struct platform_driver xtfpga_i2s_driver = { 642 .probe = xtfpga_i2s_probe, 643 .remove = xtfpga_i2s_remove, 644 .driver = { 645 .name = "xtfpga-i2s", 646 .of_match_table = of_match_ptr(xtfpga_i2s_of_match), 647 .pm = &xtfpga_i2s_pm_ops, 648 }, 649 }; 650 651 module_platform_driver(xtfpga_i2s_driver); 652 653 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 654 MODULE_DESCRIPTION("xtfpga I2S controller driver"); 655 MODULE_LICENSE("GPL v2"); 656