1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_hdmi_audio.c - Intel HDMI audio driver 4 * 5 * Copyright (C) 2016 Intel Corp 6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 7 * Ramesh Babu K V <ramesh.babu@intel.com> 8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 9 * Jerome Anand <jerome.anand@intel.com> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * ALSA driver for Intel HDMI audio 14 */ 15 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/delay.h> 25 #include <sound/core.h> 26 #include <sound/asoundef.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/initval.h> 30 #include <sound/control.h> 31 #include <sound/jack.h> 32 #include <drm/drm_edid.h> 33 #include <drm/intel_lpe_audio.h> 34 #include "intel_hdmi_audio.h" 35 36 #define for_each_pipe(card_ctx, pipe) \ 37 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 38 #define for_each_port(card_ctx, port) \ 39 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 40 41 /*standard module options for ALSA. This module supports only one card*/ 42 static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 43 static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 44 static bool single_port; 45 46 module_param_named(index, hdmi_card_index, int, 0444); 47 MODULE_PARM_DESC(index, 48 "Index value for INTEL Intel HDMI Audio controller."); 49 module_param_named(id, hdmi_card_id, charp, 0444); 50 MODULE_PARM_DESC(id, 51 "ID string for INTEL Intel HDMI Audio controller."); 52 module_param(single_port, bool, 0444); 53 MODULE_PARM_DESC(single_port, 54 "Single-port mode (for compatibility)"); 55 56 /* 57 * ELD SA bits in the CEA Speaker Allocation data block 58 */ 59 static const int eld_speaker_allocation_bits[] = { 60 [0] = FL | FR, 61 [1] = LFE, 62 [2] = FC, 63 [3] = RL | RR, 64 [4] = RC, 65 [5] = FLC | FRC, 66 [6] = RLC | RRC, 67 /* the following are not defined in ELD yet */ 68 [7] = 0, 69 }; 70 71 /* 72 * This is an ordered list! 73 * 74 * The preceding ones have better chances to be selected by 75 * hdmi_channel_allocation(). 76 */ 77 static struct cea_channel_speaker_allocation channel_allocations[] = { 78 /* channel: 7 6 5 4 3 2 1 0 */ 79 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 80 /* 2.1 */ 81 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 82 /* Dolby Surround */ 83 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 84 /* surround40 */ 85 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 86 /* surround41 */ 87 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 88 /* surround50 */ 89 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 90 /* surround51 */ 91 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 92 /* 6.1 */ 93 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 94 /* surround71 */ 95 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 96 97 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 98 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 99 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 100 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 101 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 102 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 103 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 104 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 105 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 106 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 107 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 108 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 109 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 110 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 111 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 112 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 113 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 114 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 115 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 116 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 117 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 118 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 119 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 120 }; 121 122 static const struct channel_map_table map_tables[] = { 123 { SNDRV_CHMAP_FL, 0x00, FL }, 124 { SNDRV_CHMAP_FR, 0x01, FR }, 125 { SNDRV_CHMAP_RL, 0x04, RL }, 126 { SNDRV_CHMAP_RR, 0x05, RR }, 127 { SNDRV_CHMAP_LFE, 0x02, LFE }, 128 { SNDRV_CHMAP_FC, 0x03, FC }, 129 { SNDRV_CHMAP_RLC, 0x06, RLC }, 130 { SNDRV_CHMAP_RRC, 0x07, RRC }, 131 {} /* terminator */ 132 }; 133 134 /* hardware capability structure */ 135 static const struct snd_pcm_hardware had_pcm_hardware = { 136 .info = (SNDRV_PCM_INFO_INTERLEAVED | 137 SNDRV_PCM_INFO_MMAP | 138 SNDRV_PCM_INFO_MMAP_VALID | 139 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 140 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 141 SNDRV_PCM_FMTBIT_S24_LE | 142 SNDRV_PCM_FMTBIT_S32_LE), 143 .rates = SNDRV_PCM_RATE_32000 | 144 SNDRV_PCM_RATE_44100 | 145 SNDRV_PCM_RATE_48000 | 146 SNDRV_PCM_RATE_88200 | 147 SNDRV_PCM_RATE_96000 | 148 SNDRV_PCM_RATE_176400 | 149 SNDRV_PCM_RATE_192000, 150 .rate_min = HAD_MIN_RATE, 151 .rate_max = HAD_MAX_RATE, 152 .channels_min = HAD_MIN_CHANNEL, 153 .channels_max = HAD_MAX_CHANNEL, 154 .buffer_bytes_max = HAD_MAX_BUFFER, 155 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 156 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 157 .periods_min = HAD_MIN_PERIODS, 158 .periods_max = HAD_MAX_PERIODS, 159 .fifo_size = HAD_FIFO_SIZE, 160 }; 161 162 /* Get the active PCM substream; 163 * Call had_substream_put() for unreferecing. 164 * Don't call this inside had_spinlock, as it takes by itself 165 */ 166 static struct snd_pcm_substream * 167 had_substream_get(struct snd_intelhad *intelhaddata) 168 { 169 struct snd_pcm_substream *substream; 170 unsigned long flags; 171 172 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 173 substream = intelhaddata->stream_info.substream; 174 if (substream) 175 intelhaddata->stream_info.substream_refcount++; 176 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 177 return substream; 178 } 179 180 /* Unref the active PCM substream; 181 * Don't call this inside had_spinlock, as it takes by itself 182 */ 183 static void had_substream_put(struct snd_intelhad *intelhaddata) 184 { 185 unsigned long flags; 186 187 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 188 intelhaddata->stream_info.substream_refcount--; 189 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 190 } 191 192 static u32 had_config_offset(int pipe) 193 { 194 switch (pipe) { 195 default: 196 case 0: 197 return AUDIO_HDMI_CONFIG_A; 198 case 1: 199 return AUDIO_HDMI_CONFIG_B; 200 case 2: 201 return AUDIO_HDMI_CONFIG_C; 202 } 203 } 204 205 /* Register access functions */ 206 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 207 int pipe, u32 reg) 208 { 209 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 210 } 211 212 static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 213 int pipe, u32 reg, u32 val) 214 { 215 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 216 } 217 218 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 219 { 220 if (!ctx->connected) 221 *val = 0; 222 else 223 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 224 } 225 226 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 227 { 228 if (ctx->connected) 229 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 230 } 231 232 /* 233 * enable / disable audio configuration 234 * 235 * The normal read/modify should not directly be used on VLV2 for 236 * updating AUD_CONFIG register. 237 * This is because: 238 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 239 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always 240 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 241 * register. This field should be 1xy binary for configuration with 6 or 242 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 243 * causes the "channels" field to be updated as 0xy binary resulting in 244 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 245 * appropriate value when doing read-modify of AUD_CONFIG register. 246 */ 247 static void had_enable_audio(struct snd_intelhad *intelhaddata, 248 bool enable) 249 { 250 /* update the cached value */ 251 intelhaddata->aud_config.regx.aud_en = enable; 252 had_write_register(intelhaddata, AUD_CONFIG, 253 intelhaddata->aud_config.regval); 254 } 255 256 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 257 static void had_ack_irqs(struct snd_intelhad *ctx) 258 { 259 u32 status_reg; 260 261 if (!ctx->connected) 262 return; 263 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 264 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 265 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 266 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 267 } 268 269 /* Reset buffer pointers */ 270 static void had_reset_audio(struct snd_intelhad *intelhaddata) 271 { 272 had_write_register(intelhaddata, AUD_HDMI_STATUS, 273 AUD_HDMI_STATUSG_MASK_FUNCRST); 274 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 275 } 276 277 /* 278 * initialize audio channel status registers 279 * This function is called in the prepare callback 280 */ 281 static int had_prog_status_reg(struct snd_pcm_substream *substream, 282 struct snd_intelhad *intelhaddata) 283 { 284 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 285 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 286 287 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 288 IEC958_AES0_NONAUDIO) >> 1; 289 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 290 IEC958_AES3_CON_CLOCK) >> 4; 291 292 switch (substream->runtime->rate) { 293 case AUD_SAMPLE_RATE_32: 294 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 295 break; 296 297 case AUD_SAMPLE_RATE_44_1: 298 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 299 break; 300 case AUD_SAMPLE_RATE_48: 301 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 302 break; 303 case AUD_SAMPLE_RATE_88_2: 304 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 305 break; 306 case AUD_SAMPLE_RATE_96: 307 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 308 break; 309 case AUD_SAMPLE_RATE_176_4: 310 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 311 break; 312 case AUD_SAMPLE_RATE_192: 313 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 314 break; 315 316 default: 317 /* control should never come here */ 318 return -EINVAL; 319 } 320 321 had_write_register(intelhaddata, 322 AUD_CH_STATUS_0, ch_stat0.regval); 323 324 switch (substream->runtime->format) { 325 case SNDRV_PCM_FORMAT_S16_LE: 326 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 327 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 328 break; 329 case SNDRV_PCM_FORMAT_S24_LE: 330 case SNDRV_PCM_FORMAT_S32_LE: 331 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 332 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 333 break; 334 default: 335 return -EINVAL; 336 } 337 338 had_write_register(intelhaddata, 339 AUD_CH_STATUS_1, ch_stat1.regval); 340 return 0; 341 } 342 343 /* 344 * function to initialize audio 345 * registers and buffer confgiuration registers 346 * This function is called in the prepare callback 347 */ 348 static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 349 struct snd_intelhad *intelhaddata) 350 { 351 union aud_cfg cfg_val = {.regval = 0}; 352 union aud_buf_config buf_cfg = {.regval = 0}; 353 u8 channels; 354 355 had_prog_status_reg(substream, intelhaddata); 356 357 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 358 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 359 buf_cfg.regx.aud_delay = 0; 360 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 361 362 channels = substream->runtime->channels; 363 cfg_val.regx.num_ch = channels - 2; 364 if (channels <= 2) 365 cfg_val.regx.layout = LAYOUT0; 366 else 367 cfg_val.regx.layout = LAYOUT1; 368 369 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 370 cfg_val.regx.packet_mode = 1; 371 372 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 373 cfg_val.regx.left_align = 1; 374 375 cfg_val.regx.val_bit = 1; 376 377 /* fix up the DP bits */ 378 if (intelhaddata->dp_output) { 379 cfg_val.regx.dp_modei = 1; 380 cfg_val.regx.set = 1; 381 } 382 383 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 384 intelhaddata->aud_config = cfg_val; 385 return 0; 386 } 387 388 /* 389 * Compute derived values in channel_allocations[]. 390 */ 391 static void init_channel_allocations(void) 392 { 393 int i, j; 394 struct cea_channel_speaker_allocation *p; 395 396 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 397 p = channel_allocations + i; 398 p->channels = 0; 399 p->spk_mask = 0; 400 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 401 if (p->speakers[j]) { 402 p->channels++; 403 p->spk_mask |= p->speakers[j]; 404 } 405 } 406 } 407 408 /* 409 * The transformation takes two steps: 410 * 411 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 412 * spk_mask => (channel_allocations[]) => ai->CA 413 * 414 * TODO: it could select the wrong CA from multiple candidates. 415 */ 416 static int had_channel_allocation(struct snd_intelhad *intelhaddata, 417 int channels) 418 { 419 int i; 420 int ca = 0; 421 int spk_mask = 0; 422 423 /* 424 * CA defaults to 0 for basic stereo audio 425 */ 426 if (channels <= 2) 427 return 0; 428 429 /* 430 * expand ELD's speaker allocation mask 431 * 432 * ELD tells the speaker mask in a compact(paired) form, 433 * expand ELD's notions to match the ones used by Audio InfoFrame. 434 */ 435 436 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 437 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 438 spk_mask |= eld_speaker_allocation_bits[i]; 439 } 440 441 /* search for the first working match in the CA table */ 442 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 443 if (channels == channel_allocations[i].channels && 444 (spk_mask & channel_allocations[i].spk_mask) == 445 channel_allocations[i].spk_mask) { 446 ca = channel_allocations[i].ca_index; 447 break; 448 } 449 } 450 451 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 452 453 return ca; 454 } 455 456 /* from speaker bit mask to ALSA API channel position */ 457 static int spk_to_chmap(int spk) 458 { 459 const struct channel_map_table *t = map_tables; 460 461 for (; t->map; t++) { 462 if (t->spk_mask == spk) 463 return t->map; 464 } 465 return 0; 466 } 467 468 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 469 { 470 int i, c; 471 int spk_mask = 0; 472 struct snd_pcm_chmap_elem *chmap; 473 u8 eld_high, eld_high_mask = 0xF0; 474 u8 high_msb; 475 476 kfree(intelhaddata->chmap->chmap); 477 intelhaddata->chmap->chmap = NULL; 478 479 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 480 if (!chmap) 481 return; 482 483 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 484 intelhaddata->eld[DRM_ELD_SPEAKER]); 485 486 /* WA: Fix the max channel supported to 8 */ 487 488 /* 489 * Sink may support more than 8 channels, if eld_high has more than 490 * one bit set. SOC supports max 8 channels. 491 * Refer eld_speaker_allocation_bits, for sink speaker allocation 492 */ 493 494 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 495 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 496 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 497 /* eld_high & (eld_high-1): if more than 1 bit set */ 498 /* 0x1F: 7 channels */ 499 for (i = 1; i < 4; i++) { 500 high_msb = eld_high & (0x80 >> i); 501 if (high_msb) { 502 intelhaddata->eld[DRM_ELD_SPEAKER] &= 503 high_msb | 0xF; 504 break; 505 } 506 } 507 } 508 509 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 510 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 511 spk_mask |= eld_speaker_allocation_bits[i]; 512 } 513 514 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 515 if (spk_mask == channel_allocations[i].spk_mask) { 516 for (c = 0; c < channel_allocations[i].channels; c++) { 517 chmap->map[c] = spk_to_chmap( 518 channel_allocations[i].speakers[ 519 (MAX_SPEAKERS - 1) - c]); 520 } 521 chmap->channels = channel_allocations[i].channels; 522 intelhaddata->chmap->chmap = chmap; 523 break; 524 } 525 } 526 if (i >= ARRAY_SIZE(channel_allocations)) 527 kfree(chmap); 528 } 529 530 /* 531 * ALSA API channel-map control callbacks 532 */ 533 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 534 struct snd_ctl_elem_info *uinfo) 535 { 536 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 537 uinfo->count = HAD_MAX_CHANNEL; 538 uinfo->value.integer.min = 0; 539 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 540 return 0; 541 } 542 543 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 544 struct snd_ctl_elem_value *ucontrol) 545 { 546 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 547 struct snd_intelhad *intelhaddata = info->private_data; 548 int i; 549 const struct snd_pcm_chmap_elem *chmap; 550 551 memset(ucontrol->value.integer.value, 0, 552 sizeof(long) * HAD_MAX_CHANNEL); 553 mutex_lock(&intelhaddata->mutex); 554 if (!intelhaddata->chmap->chmap) { 555 mutex_unlock(&intelhaddata->mutex); 556 return 0; 557 } 558 559 chmap = intelhaddata->chmap->chmap; 560 for (i = 0; i < chmap->channels; i++) 561 ucontrol->value.integer.value[i] = chmap->map[i]; 562 mutex_unlock(&intelhaddata->mutex); 563 564 return 0; 565 } 566 567 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 568 struct snd_pcm *pcm) 569 { 570 int err; 571 572 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 573 NULL, 0, (unsigned long)intelhaddata, 574 &intelhaddata->chmap); 575 if (err < 0) 576 return err; 577 578 intelhaddata->chmap->private_data = intelhaddata; 579 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 580 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 581 intelhaddata->chmap->chmap = NULL; 582 return 0; 583 } 584 585 /* 586 * Initialize Data Island Packets registers 587 * This function is called in the prepare callback 588 */ 589 static void had_prog_dip(struct snd_pcm_substream *substream, 590 struct snd_intelhad *intelhaddata) 591 { 592 int i; 593 union aud_ctrl_st ctrl_state = {.regval = 0}; 594 union aud_info_frame2 frame2 = {.regval = 0}; 595 union aud_info_frame3 frame3 = {.regval = 0}; 596 u8 checksum = 0; 597 u32 info_frame; 598 int channels; 599 int ca; 600 601 channels = substream->runtime->channels; 602 603 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 604 605 ca = had_channel_allocation(intelhaddata, channels); 606 if (intelhaddata->dp_output) { 607 info_frame = DP_INFO_FRAME_WORD1; 608 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 609 } else { 610 info_frame = HDMI_INFO_FRAME_WORD1; 611 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 612 frame3.regx.chnl_alloc = ca; 613 614 /* Calculte the byte wide checksum for all valid DIP words */ 615 for (i = 0; i < BYTES_PER_WORD; i++) 616 checksum += (info_frame >> (i * 8)) & 0xff; 617 for (i = 0; i < BYTES_PER_WORD; i++) 618 checksum += (frame2.regval >> (i * 8)) & 0xff; 619 for (i = 0; i < BYTES_PER_WORD; i++) 620 checksum += (frame3.regval >> (i * 8)) & 0xff; 621 622 frame2.regx.chksum = -(checksum); 623 } 624 625 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 626 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 627 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 628 629 /* program remaining DIP words with zero */ 630 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 631 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 632 633 ctrl_state.regx.dip_freq = 1; 634 ctrl_state.regx.dip_en_sta = 1; 635 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 636 } 637 638 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 639 { 640 u32 maud_val; 641 642 /* Select maud according to DP 1.2 spec */ 643 if (link_rate == DP_2_7_GHZ) { 644 switch (aud_samp_freq) { 645 case AUD_SAMPLE_RATE_32: 646 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 647 break; 648 649 case AUD_SAMPLE_RATE_44_1: 650 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 651 break; 652 653 case AUD_SAMPLE_RATE_48: 654 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 655 break; 656 657 case AUD_SAMPLE_RATE_88_2: 658 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 659 break; 660 661 case AUD_SAMPLE_RATE_96: 662 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 663 break; 664 665 case AUD_SAMPLE_RATE_176_4: 666 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 667 break; 668 669 case HAD_MAX_RATE: 670 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 671 break; 672 673 default: 674 maud_val = -EINVAL; 675 break; 676 } 677 } else if (link_rate == DP_1_62_GHZ) { 678 switch (aud_samp_freq) { 679 case AUD_SAMPLE_RATE_32: 680 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 681 break; 682 683 case AUD_SAMPLE_RATE_44_1: 684 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 685 break; 686 687 case AUD_SAMPLE_RATE_48: 688 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 689 break; 690 691 case AUD_SAMPLE_RATE_88_2: 692 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 693 break; 694 695 case AUD_SAMPLE_RATE_96: 696 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 697 break; 698 699 case AUD_SAMPLE_RATE_176_4: 700 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 701 break; 702 703 case HAD_MAX_RATE: 704 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 705 break; 706 707 default: 708 maud_val = -EINVAL; 709 break; 710 } 711 } else 712 maud_val = -EINVAL; 713 714 return maud_val; 715 } 716 717 /* 718 * Program HDMI audio CTS value 719 * 720 * @aud_samp_freq: sampling frequency of audio data 721 * @tmds: sampling frequency of the display data 722 * @link_rate: DP link rate 723 * @n_param: N value, depends on aud_samp_freq 724 * @intelhaddata: substream private data 725 * 726 * Program CTS register based on the audio and display sampling frequency 727 */ 728 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 729 u32 n_param, struct snd_intelhad *intelhaddata) 730 { 731 u32 cts_val; 732 u64 dividend, divisor; 733 734 if (intelhaddata->dp_output) { 735 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 736 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 737 } else { 738 /* Calculate CTS according to HDMI 1.3a spec*/ 739 dividend = (u64)tmds * n_param*1000; 740 divisor = 128 * aud_samp_freq; 741 cts_val = div64_u64(dividend, divisor); 742 } 743 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 744 tmds, n_param, cts_val); 745 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 746 } 747 748 static int had_calculate_n_value(u32 aud_samp_freq) 749 { 750 int n_val; 751 752 /* Select N according to HDMI 1.3a spec*/ 753 switch (aud_samp_freq) { 754 case AUD_SAMPLE_RATE_32: 755 n_val = 4096; 756 break; 757 758 case AUD_SAMPLE_RATE_44_1: 759 n_val = 6272; 760 break; 761 762 case AUD_SAMPLE_RATE_48: 763 n_val = 6144; 764 break; 765 766 case AUD_SAMPLE_RATE_88_2: 767 n_val = 12544; 768 break; 769 770 case AUD_SAMPLE_RATE_96: 771 n_val = 12288; 772 break; 773 774 case AUD_SAMPLE_RATE_176_4: 775 n_val = 25088; 776 break; 777 778 case HAD_MAX_RATE: 779 n_val = 24576; 780 break; 781 782 default: 783 n_val = -EINVAL; 784 break; 785 } 786 return n_val; 787 } 788 789 /* 790 * Program HDMI audio N value 791 * 792 * @aud_samp_freq: sampling frequency of audio data 793 * @n_param: N value, depends on aud_samp_freq 794 * @intelhaddata: substream private data 795 * 796 * This function is called in the prepare callback. 797 * It programs based on the audio and display sampling frequency 798 */ 799 static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 800 struct snd_intelhad *intelhaddata) 801 { 802 int n_val; 803 804 if (intelhaddata->dp_output) { 805 /* 806 * According to DP specs, Maud and Naud values hold 807 * a relationship, which is stated as: 808 * Maud/Naud = 512 * fs / f_LS_Clk 809 * where, fs is the sampling frequency of the audio stream 810 * and Naud is 32768 for Async clock. 811 */ 812 813 n_val = DP_NAUD_VAL; 814 } else 815 n_val = had_calculate_n_value(aud_samp_freq); 816 817 if (n_val < 0) 818 return n_val; 819 820 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 821 *n_param = n_val; 822 return 0; 823 } 824 825 /* 826 * PCM ring buffer handling 827 * 828 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 829 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 830 * moves at each period elapsed. The below illustrates how it works: 831 * 832 * At time=0 833 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 834 * BD | 0 | 1 | 2 | 3 | 835 * 836 * At time=1 (period elapsed) 837 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 838 * BD | 1 | 2 | 3 | 0 | 839 * 840 * At time=2 (second period elapsed) 841 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 842 * BD | 2 | 3 | 0 | 1 | 843 * 844 * The bd_head field points to the index of the BD to be read. It's also the 845 * position to be filled at next. The pcm_head and the pcm_filled fields 846 * point to the indices of the current position and of the next position to 847 * be filled, respectively. For PCM buffer there are both _head and _filled 848 * because they may be difference when nperiods > 4. For example, in the 849 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 850 * 851 * pcm_head (=1) --v v-- pcm_filled (=5) 852 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 853 * BD | 1 | 2 | 3 | 0 | 854 * bd_head (=1) --^ ^-- next to fill (= bd_head) 855 * 856 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 857 * the hardware skips those BDs in the loop. 858 * 859 * An exceptional setup is the case with nperiods=1. Since we have to update 860 * BDs after finishing one BD processing, we'd need at least two BDs, where 861 * both BDs point to the same content, the same address, the same size of the 862 * whole PCM buffer. 863 */ 864 865 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 866 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 867 868 /* Set up a buffer descriptor at the "filled" position */ 869 static void had_prog_bd(struct snd_pcm_substream *substream, 870 struct snd_intelhad *intelhaddata) 871 { 872 int idx = intelhaddata->bd_head; 873 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 874 u32 addr = substream->runtime->dma_addr + ofs; 875 876 addr |= AUD_BUF_VALID; 877 if (!substream->runtime->no_period_wakeup) 878 addr |= AUD_BUF_INTR_EN; 879 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 880 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 881 intelhaddata->period_bytes); 882 883 /* advance the indices to the next */ 884 intelhaddata->bd_head++; 885 intelhaddata->bd_head %= intelhaddata->num_bds; 886 intelhaddata->pcmbuf_filled++; 887 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 888 } 889 890 /* invalidate a buffer descriptor with the given index */ 891 static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 892 int idx) 893 { 894 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 895 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 896 } 897 898 /* Initial programming of ring buffer */ 899 static void had_init_ringbuf(struct snd_pcm_substream *substream, 900 struct snd_intelhad *intelhaddata) 901 { 902 struct snd_pcm_runtime *runtime = substream->runtime; 903 int i, num_periods; 904 905 num_periods = runtime->periods; 906 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 907 /* set the minimum 2 BDs for num_periods=1 */ 908 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 909 intelhaddata->period_bytes = 910 frames_to_bytes(runtime, runtime->period_size); 911 WARN_ON(intelhaddata->period_bytes & 0x3f); 912 913 intelhaddata->bd_head = 0; 914 intelhaddata->pcmbuf_head = 0; 915 intelhaddata->pcmbuf_filled = 0; 916 917 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 918 if (i < intelhaddata->num_bds) 919 had_prog_bd(substream, intelhaddata); 920 else /* invalidate the rest */ 921 had_invalidate_bd(intelhaddata, i); 922 } 923 924 intelhaddata->bd_head = 0; /* reset at head again before starting */ 925 } 926 927 /* process a bd, advance to the next */ 928 static void had_advance_ringbuf(struct snd_pcm_substream *substream, 929 struct snd_intelhad *intelhaddata) 930 { 931 int num_periods = substream->runtime->periods; 932 933 /* reprogram the next buffer */ 934 had_prog_bd(substream, intelhaddata); 935 936 /* proceed to next */ 937 intelhaddata->pcmbuf_head++; 938 intelhaddata->pcmbuf_head %= num_periods; 939 } 940 941 /* process the current BD(s); 942 * returns the current PCM buffer byte position, or -EPIPE for underrun. 943 */ 944 static int had_process_ringbuf(struct snd_pcm_substream *substream, 945 struct snd_intelhad *intelhaddata) 946 { 947 int len, processed; 948 unsigned long flags; 949 950 processed = 0; 951 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 952 for (;;) { 953 /* get the remaining bytes on the buffer */ 954 had_read_register(intelhaddata, 955 AUD_BUF_LEN(intelhaddata->bd_head), 956 &len); 957 if (len < 0 || len > intelhaddata->period_bytes) { 958 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 959 len); 960 len = -EPIPE; 961 goto out; 962 } 963 964 if (len > 0) /* OK, this is the current buffer */ 965 break; 966 967 /* len=0 => already empty, check the next buffer */ 968 if (++processed >= intelhaddata->num_bds) { 969 len = -EPIPE; /* all empty? - report underrun */ 970 goto out; 971 } 972 had_advance_ringbuf(substream, intelhaddata); 973 } 974 975 len = intelhaddata->period_bytes - len; 976 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 977 out: 978 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 979 return len; 980 } 981 982 /* called from irq handler */ 983 static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 984 { 985 struct snd_pcm_substream *substream; 986 987 substream = had_substream_get(intelhaddata); 988 if (!substream) 989 return; /* no stream? - bail out */ 990 991 if (!intelhaddata->connected) { 992 snd_pcm_stop_xrun(substream); 993 goto out; /* disconnected? - bail out */ 994 } 995 996 /* process or stop the stream */ 997 if (had_process_ringbuf(substream, intelhaddata) < 0) 998 snd_pcm_stop_xrun(substream); 999 else 1000 snd_pcm_period_elapsed(substream); 1001 1002 out: 1003 had_substream_put(intelhaddata); 1004 } 1005 1006 /* 1007 * The interrupt status 'sticky' bits might not be cleared by 1008 * setting '1' to that bit once... 1009 */ 1010 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1011 { 1012 int i; 1013 u32 val; 1014 1015 for (i = 0; i < 100; i++) { 1016 /* clear bit30, 31 AUD_HDMI_STATUS */ 1017 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1018 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1019 return; 1020 udelay(100); 1021 cond_resched(); 1022 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1023 } 1024 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1025 } 1026 1027 /* Perform some reset procedure but only when need_reset is set; 1028 * this is called from prepare or hw_free callbacks once after trigger STOP 1029 * or underrun has been processed in order to settle down the h/w state. 1030 */ 1031 static void had_do_reset(struct snd_intelhad *intelhaddata) 1032 { 1033 if (!intelhaddata->need_reset || !intelhaddata->connected) 1034 return; 1035 1036 /* Reset buffer pointers */ 1037 had_reset_audio(intelhaddata); 1038 wait_clear_underrun_bit(intelhaddata); 1039 intelhaddata->need_reset = false; 1040 } 1041 1042 /* called from irq handler */ 1043 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1044 { 1045 struct snd_pcm_substream *substream; 1046 1047 /* Report UNDERRUN error to above layers */ 1048 substream = had_substream_get(intelhaddata); 1049 if (substream) { 1050 snd_pcm_stop_xrun(substream); 1051 had_substream_put(intelhaddata); 1052 } 1053 intelhaddata->need_reset = true; 1054 } 1055 1056 /* 1057 * ALSA PCM open callback 1058 */ 1059 static int had_pcm_open(struct snd_pcm_substream *substream) 1060 { 1061 struct snd_intelhad *intelhaddata; 1062 struct snd_pcm_runtime *runtime; 1063 int retval; 1064 1065 intelhaddata = snd_pcm_substream_chip(substream); 1066 runtime = substream->runtime; 1067 1068 pm_runtime_get_sync(intelhaddata->dev); 1069 1070 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1071 runtime->hw = had_pcm_hardware; 1072 1073 retval = snd_pcm_hw_constraint_integer(runtime, 1074 SNDRV_PCM_HW_PARAM_PERIODS); 1075 if (retval < 0) 1076 goto error; 1077 1078 /* Make sure, that the period size is always aligned 1079 * 64byte boundary 1080 */ 1081 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1082 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1083 if (retval < 0) 1084 goto error; 1085 1086 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1087 if (retval < 0) 1088 goto error; 1089 1090 /* expose PCM substream */ 1091 spin_lock_irq(&intelhaddata->had_spinlock); 1092 intelhaddata->stream_info.substream = substream; 1093 intelhaddata->stream_info.substream_refcount++; 1094 spin_unlock_irq(&intelhaddata->had_spinlock); 1095 1096 return retval; 1097 error: 1098 pm_runtime_mark_last_busy(intelhaddata->dev); 1099 pm_runtime_put_autosuspend(intelhaddata->dev); 1100 return retval; 1101 } 1102 1103 /* 1104 * ALSA PCM close callback 1105 */ 1106 static int had_pcm_close(struct snd_pcm_substream *substream) 1107 { 1108 struct snd_intelhad *intelhaddata; 1109 1110 intelhaddata = snd_pcm_substream_chip(substream); 1111 1112 /* unreference and sync with the pending PCM accesses */ 1113 spin_lock_irq(&intelhaddata->had_spinlock); 1114 intelhaddata->stream_info.substream = NULL; 1115 intelhaddata->stream_info.substream_refcount--; 1116 while (intelhaddata->stream_info.substream_refcount > 0) { 1117 spin_unlock_irq(&intelhaddata->had_spinlock); 1118 cpu_relax(); 1119 spin_lock_irq(&intelhaddata->had_spinlock); 1120 } 1121 spin_unlock_irq(&intelhaddata->had_spinlock); 1122 1123 pm_runtime_mark_last_busy(intelhaddata->dev); 1124 pm_runtime_put_autosuspend(intelhaddata->dev); 1125 return 0; 1126 } 1127 1128 /* 1129 * ALSA PCM hw_params callback 1130 */ 1131 static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1132 struct snd_pcm_hw_params *hw_params) 1133 { 1134 struct snd_intelhad *intelhaddata; 1135 int buf_size, retval; 1136 1137 intelhaddata = snd_pcm_substream_chip(substream); 1138 buf_size = params_buffer_bytes(hw_params); 1139 retval = snd_pcm_lib_malloc_pages(substream, buf_size); 1140 if (retval < 0) 1141 return retval; 1142 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1143 __func__, buf_size); 1144 return retval; 1145 } 1146 1147 /* 1148 * ALSA PCM hw_free callback 1149 */ 1150 static int had_pcm_hw_free(struct snd_pcm_substream *substream) 1151 { 1152 struct snd_intelhad *intelhaddata; 1153 1154 intelhaddata = snd_pcm_substream_chip(substream); 1155 had_do_reset(intelhaddata); 1156 1157 return snd_pcm_lib_free_pages(substream); 1158 } 1159 1160 /* 1161 * ALSA PCM trigger callback 1162 */ 1163 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1164 { 1165 int retval = 0; 1166 struct snd_intelhad *intelhaddata; 1167 1168 intelhaddata = snd_pcm_substream_chip(substream); 1169 1170 spin_lock(&intelhaddata->had_spinlock); 1171 switch (cmd) { 1172 case SNDRV_PCM_TRIGGER_START: 1173 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1174 case SNDRV_PCM_TRIGGER_RESUME: 1175 /* Enable Audio */ 1176 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1177 had_enable_audio(intelhaddata, true); 1178 break; 1179 1180 case SNDRV_PCM_TRIGGER_STOP: 1181 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1182 /* Disable Audio */ 1183 had_enable_audio(intelhaddata, false); 1184 intelhaddata->need_reset = true; 1185 break; 1186 1187 default: 1188 retval = -EINVAL; 1189 } 1190 spin_unlock(&intelhaddata->had_spinlock); 1191 return retval; 1192 } 1193 1194 /* 1195 * ALSA PCM prepare callback 1196 */ 1197 static int had_pcm_prepare(struct snd_pcm_substream *substream) 1198 { 1199 int retval; 1200 u32 disp_samp_freq, n_param; 1201 u32 link_rate = 0; 1202 struct snd_intelhad *intelhaddata; 1203 struct snd_pcm_runtime *runtime; 1204 1205 intelhaddata = snd_pcm_substream_chip(substream); 1206 runtime = substream->runtime; 1207 1208 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1209 (int)frames_to_bytes(runtime, runtime->period_size)); 1210 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1211 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1212 (int)snd_pcm_lib_buffer_bytes(substream)); 1213 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1214 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1215 1216 had_do_reset(intelhaddata); 1217 1218 /* Get N value in KHz */ 1219 disp_samp_freq = intelhaddata->tmds_clock_speed; 1220 1221 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1222 if (retval) { 1223 dev_err(intelhaddata->dev, 1224 "programming N value failed %#x\n", retval); 1225 goto prep_end; 1226 } 1227 1228 if (intelhaddata->dp_output) 1229 link_rate = intelhaddata->link_rate; 1230 1231 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1232 n_param, intelhaddata); 1233 1234 had_prog_dip(substream, intelhaddata); 1235 1236 retval = had_init_audio_ctrl(substream, intelhaddata); 1237 1238 /* Prog buffer address */ 1239 had_init_ringbuf(substream, intelhaddata); 1240 1241 /* 1242 * Program channel mapping in following order: 1243 * FL, FR, C, LFE, RL, RR 1244 */ 1245 1246 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1247 1248 prep_end: 1249 return retval; 1250 } 1251 1252 /* 1253 * ALSA PCM pointer callback 1254 */ 1255 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1256 { 1257 struct snd_intelhad *intelhaddata; 1258 int len; 1259 1260 intelhaddata = snd_pcm_substream_chip(substream); 1261 1262 if (!intelhaddata->connected) 1263 return SNDRV_PCM_POS_XRUN; 1264 1265 len = had_process_ringbuf(substream, intelhaddata); 1266 if (len < 0) 1267 return SNDRV_PCM_POS_XRUN; 1268 len = bytes_to_frames(substream->runtime, len); 1269 /* wrapping may happen when periods=1 */ 1270 len %= substream->runtime->buffer_size; 1271 return len; 1272 } 1273 1274 /* 1275 * ALSA PCM mmap callback 1276 */ 1277 static int had_pcm_mmap(struct snd_pcm_substream *substream, 1278 struct vm_area_struct *vma) 1279 { 1280 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1281 return remap_pfn_range(vma, vma->vm_start, 1282 substream->dma_buffer.addr >> PAGE_SHIFT, 1283 vma->vm_end - vma->vm_start, vma->vm_page_prot); 1284 } 1285 1286 /* 1287 * ALSA PCM ops 1288 */ 1289 static const struct snd_pcm_ops had_pcm_ops = { 1290 .open = had_pcm_open, 1291 .close = had_pcm_close, 1292 .ioctl = snd_pcm_lib_ioctl, 1293 .hw_params = had_pcm_hw_params, 1294 .hw_free = had_pcm_hw_free, 1295 .prepare = had_pcm_prepare, 1296 .trigger = had_pcm_trigger, 1297 .pointer = had_pcm_pointer, 1298 .mmap = had_pcm_mmap, 1299 }; 1300 1301 /* process mode change of the running stream; called in mutex */ 1302 static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1303 { 1304 struct snd_pcm_substream *substream; 1305 int retval = 0; 1306 u32 disp_samp_freq, n_param; 1307 u32 link_rate = 0; 1308 1309 substream = had_substream_get(intelhaddata); 1310 if (!substream) 1311 return 0; 1312 1313 /* Disable Audio */ 1314 had_enable_audio(intelhaddata, false); 1315 1316 /* Update CTS value */ 1317 disp_samp_freq = intelhaddata->tmds_clock_speed; 1318 1319 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1320 if (retval) { 1321 dev_err(intelhaddata->dev, 1322 "programming N value failed %#x\n", retval); 1323 goto out; 1324 } 1325 1326 if (intelhaddata->dp_output) 1327 link_rate = intelhaddata->link_rate; 1328 1329 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1330 n_param, intelhaddata); 1331 1332 /* Enable Audio */ 1333 had_enable_audio(intelhaddata, true); 1334 1335 out: 1336 had_substream_put(intelhaddata); 1337 return retval; 1338 } 1339 1340 /* process hot plug, called from wq with mutex locked */ 1341 static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1342 { 1343 struct snd_pcm_substream *substream; 1344 1345 spin_lock_irq(&intelhaddata->had_spinlock); 1346 if (intelhaddata->connected) { 1347 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1348 spin_unlock_irq(&intelhaddata->had_spinlock); 1349 return; 1350 } 1351 1352 /* Disable Audio */ 1353 had_enable_audio(intelhaddata, false); 1354 1355 intelhaddata->connected = true; 1356 dev_dbg(intelhaddata->dev, 1357 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1358 __func__, __LINE__); 1359 spin_unlock_irq(&intelhaddata->had_spinlock); 1360 1361 had_build_channel_allocation_map(intelhaddata); 1362 1363 /* Report to above ALSA layer */ 1364 substream = had_substream_get(intelhaddata); 1365 if (substream) { 1366 snd_pcm_stop_xrun(substream); 1367 had_substream_put(intelhaddata); 1368 } 1369 1370 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1371 } 1372 1373 /* process hot unplug, called from wq with mutex locked */ 1374 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1375 { 1376 struct snd_pcm_substream *substream; 1377 1378 spin_lock_irq(&intelhaddata->had_spinlock); 1379 if (!intelhaddata->connected) { 1380 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1381 spin_unlock_irq(&intelhaddata->had_spinlock); 1382 return; 1383 1384 } 1385 1386 /* Disable Audio */ 1387 had_enable_audio(intelhaddata, false); 1388 1389 intelhaddata->connected = false; 1390 dev_dbg(intelhaddata->dev, 1391 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1392 __func__, __LINE__); 1393 spin_unlock_irq(&intelhaddata->had_spinlock); 1394 1395 kfree(intelhaddata->chmap->chmap); 1396 intelhaddata->chmap->chmap = NULL; 1397 1398 /* Report to above ALSA layer */ 1399 substream = had_substream_get(intelhaddata); 1400 if (substream) { 1401 snd_pcm_stop_xrun(substream); 1402 had_substream_put(intelhaddata); 1403 } 1404 1405 snd_jack_report(intelhaddata->jack, 0); 1406 } 1407 1408 /* 1409 * ALSA iec958 and ELD controls 1410 */ 1411 1412 static int had_iec958_info(struct snd_kcontrol *kcontrol, 1413 struct snd_ctl_elem_info *uinfo) 1414 { 1415 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1416 uinfo->count = 1; 1417 return 0; 1418 } 1419 1420 static int had_iec958_get(struct snd_kcontrol *kcontrol, 1421 struct snd_ctl_elem_value *ucontrol) 1422 { 1423 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1424 1425 mutex_lock(&intelhaddata->mutex); 1426 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1427 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1428 ucontrol->value.iec958.status[2] = 1429 (intelhaddata->aes_bits >> 16) & 0xff; 1430 ucontrol->value.iec958.status[3] = 1431 (intelhaddata->aes_bits >> 24) & 0xff; 1432 mutex_unlock(&intelhaddata->mutex); 1433 return 0; 1434 } 1435 1436 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1437 struct snd_ctl_elem_value *ucontrol) 1438 { 1439 ucontrol->value.iec958.status[0] = 0xff; 1440 ucontrol->value.iec958.status[1] = 0xff; 1441 ucontrol->value.iec958.status[2] = 0xff; 1442 ucontrol->value.iec958.status[3] = 0xff; 1443 return 0; 1444 } 1445 1446 static int had_iec958_put(struct snd_kcontrol *kcontrol, 1447 struct snd_ctl_elem_value *ucontrol) 1448 { 1449 unsigned int val; 1450 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1451 int changed = 0; 1452 1453 val = (ucontrol->value.iec958.status[0] << 0) | 1454 (ucontrol->value.iec958.status[1] << 8) | 1455 (ucontrol->value.iec958.status[2] << 16) | 1456 (ucontrol->value.iec958.status[3] << 24); 1457 mutex_lock(&intelhaddata->mutex); 1458 if (intelhaddata->aes_bits != val) { 1459 intelhaddata->aes_bits = val; 1460 changed = 1; 1461 } 1462 mutex_unlock(&intelhaddata->mutex); 1463 return changed; 1464 } 1465 1466 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1467 struct snd_ctl_elem_info *uinfo) 1468 { 1469 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1470 uinfo->count = HDMI_MAX_ELD_BYTES; 1471 return 0; 1472 } 1473 1474 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1475 struct snd_ctl_elem_value *ucontrol) 1476 { 1477 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1478 1479 mutex_lock(&intelhaddata->mutex); 1480 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1481 HDMI_MAX_ELD_BYTES); 1482 mutex_unlock(&intelhaddata->mutex); 1483 return 0; 1484 } 1485 1486 static const struct snd_kcontrol_new had_controls[] = { 1487 { 1488 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1489 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1490 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1491 .info = had_iec958_info, /* shared */ 1492 .get = had_iec958_mask_get, 1493 }, 1494 { 1495 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1496 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1497 .info = had_iec958_info, 1498 .get = had_iec958_get, 1499 .put = had_iec958_put, 1500 }, 1501 { 1502 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1503 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1504 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1505 .name = "ELD", 1506 .info = had_ctl_eld_info, 1507 .get = had_ctl_eld_get, 1508 }, 1509 }; 1510 1511 /* 1512 * audio interrupt handler 1513 */ 1514 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1515 { 1516 struct snd_intelhad_card *card_ctx = dev_id; 1517 u32 audio_stat[3] = {}; 1518 int pipe, port; 1519 1520 for_each_pipe(card_ctx, pipe) { 1521 /* use raw register access to ack IRQs even while disconnected */ 1522 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1523 AUD_HDMI_STATUS) & 1524 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1525 1526 if (audio_stat[pipe]) 1527 had_write_register_raw(card_ctx, pipe, 1528 AUD_HDMI_STATUS, audio_stat[pipe]); 1529 } 1530 1531 for_each_port(card_ctx, port) { 1532 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1533 int pipe = ctx->pipe; 1534 1535 if (pipe < 0) 1536 continue; 1537 1538 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1539 had_process_buffer_done(ctx); 1540 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1541 had_process_buffer_underrun(ctx); 1542 } 1543 1544 return IRQ_HANDLED; 1545 } 1546 1547 /* 1548 * monitor plug/unplug notification from i915; just kick off the work 1549 */ 1550 static void notify_audio_lpe(struct platform_device *pdev, int port) 1551 { 1552 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1553 struct snd_intelhad *ctx; 1554 1555 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; 1556 if (single_port) 1557 ctx->port = port; 1558 1559 schedule_work(&ctx->hdmi_audio_wq); 1560 } 1561 1562 /* the work to handle monitor hot plug/unplug */ 1563 static void had_audio_wq(struct work_struct *work) 1564 { 1565 struct snd_intelhad *ctx = 1566 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1567 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1568 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1569 1570 pm_runtime_get_sync(ctx->dev); 1571 mutex_lock(&ctx->mutex); 1572 if (ppdata->pipe < 0) { 1573 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1574 __func__, ctx->port); 1575 1576 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1577 1578 ctx->dp_output = false; 1579 ctx->tmds_clock_speed = 0; 1580 ctx->link_rate = 0; 1581 1582 /* Shut down the stream */ 1583 had_process_hot_unplug(ctx); 1584 1585 ctx->pipe = -1; 1586 } else { 1587 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1588 __func__, ctx->port, ppdata->ls_clock); 1589 1590 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1591 1592 ctx->dp_output = ppdata->dp_output; 1593 if (ctx->dp_output) { 1594 ctx->tmds_clock_speed = 0; 1595 ctx->link_rate = ppdata->ls_clock; 1596 } else { 1597 ctx->tmds_clock_speed = ppdata->ls_clock; 1598 ctx->link_rate = 0; 1599 } 1600 1601 /* 1602 * Shut down the stream before we change 1603 * the pipe assignment for this pcm device 1604 */ 1605 had_process_hot_plug(ctx); 1606 1607 ctx->pipe = ppdata->pipe; 1608 1609 /* Restart the stream if necessary */ 1610 had_process_mode_change(ctx); 1611 } 1612 1613 mutex_unlock(&ctx->mutex); 1614 pm_runtime_mark_last_busy(ctx->dev); 1615 pm_runtime_put_autosuspend(ctx->dev); 1616 } 1617 1618 /* 1619 * Jack interface 1620 */ 1621 static int had_create_jack(struct snd_intelhad *ctx, 1622 struct snd_pcm *pcm) 1623 { 1624 char hdmi_str[32]; 1625 int err; 1626 1627 snprintf(hdmi_str, sizeof(hdmi_str), 1628 "HDMI/DP,pcm=%d", pcm->device); 1629 1630 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1631 SND_JACK_AVOUT, &ctx->jack, 1632 true, false); 1633 if (err < 0) 1634 return err; 1635 ctx->jack->private_data = ctx; 1636 return 0; 1637 } 1638 1639 /* 1640 * PM callbacks 1641 */ 1642 1643 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) 1644 { 1645 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1646 1647 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1648 1649 return 0; 1650 } 1651 1652 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) 1653 { 1654 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1655 1656 pm_runtime_mark_last_busy(dev); 1657 1658 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1659 1660 return 0; 1661 } 1662 1663 /* release resources */ 1664 static void hdmi_lpe_audio_free(struct snd_card *card) 1665 { 1666 struct snd_intelhad_card *card_ctx = card->private_data; 1667 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1668 int port; 1669 1670 spin_lock_irq(&pdata->lpe_audio_slock); 1671 pdata->notify_audio_lpe = NULL; 1672 spin_unlock_irq(&pdata->lpe_audio_slock); 1673 1674 for_each_port(card_ctx, port) { 1675 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1676 1677 cancel_work_sync(&ctx->hdmi_audio_wq); 1678 } 1679 1680 if (card_ctx->mmio_start) 1681 iounmap(card_ctx->mmio_start); 1682 if (card_ctx->irq >= 0) 1683 free_irq(card_ctx->irq, card_ctx); 1684 } 1685 1686 /* 1687 * hdmi_lpe_audio_probe - start bridge with i915 1688 * 1689 * This function is called when the i915 driver creates the 1690 * hdmi-lpe-audio platform device. 1691 */ 1692 static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1693 { 1694 struct snd_card *card; 1695 struct snd_intelhad_card *card_ctx; 1696 struct snd_intelhad *ctx; 1697 struct snd_pcm *pcm; 1698 struct intel_hdmi_lpe_audio_pdata *pdata; 1699 int irq; 1700 struct resource *res_mmio; 1701 int port, ret; 1702 1703 pdata = pdev->dev.platform_data; 1704 if (!pdata) { 1705 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1706 return -EINVAL; 1707 } 1708 1709 /* get resources */ 1710 irq = platform_get_irq(pdev, 0); 1711 if (irq < 0) { 1712 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq); 1713 return irq; 1714 } 1715 1716 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1717 if (!res_mmio) { 1718 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1719 return -ENXIO; 1720 } 1721 1722 /* create a card instance with ALSA framework */ 1723 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1724 THIS_MODULE, sizeof(*card_ctx), &card); 1725 if (ret) 1726 return ret; 1727 1728 card_ctx = card->private_data; 1729 card_ctx->dev = &pdev->dev; 1730 card_ctx->card = card; 1731 strcpy(card->driver, INTEL_HAD); 1732 strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1733 strcpy(card->longname, "Intel HDMI/DP LPE Audio"); 1734 1735 card_ctx->irq = -1; 1736 1737 card->private_free = hdmi_lpe_audio_free; 1738 1739 platform_set_drvdata(pdev, card_ctx); 1740 1741 card_ctx->num_pipes = pdata->num_pipes; 1742 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1743 1744 for_each_port(card_ctx, port) { 1745 ctx = &card_ctx->pcm_ctx[port]; 1746 ctx->card_ctx = card_ctx; 1747 ctx->dev = card_ctx->dev; 1748 ctx->port = single_port ? -1 : port; 1749 ctx->pipe = -1; 1750 1751 spin_lock_init(&ctx->had_spinlock); 1752 mutex_init(&ctx->mutex); 1753 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1754 } 1755 1756 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1757 __func__, (unsigned int)res_mmio->start, 1758 (unsigned int)res_mmio->end); 1759 1760 card_ctx->mmio_start = ioremap_nocache(res_mmio->start, 1761 (size_t)(resource_size(res_mmio))); 1762 if (!card_ctx->mmio_start) { 1763 dev_err(&pdev->dev, "Could not get ioremap\n"); 1764 ret = -EACCES; 1765 goto err; 1766 } 1767 1768 /* setup interrupt handler */ 1769 ret = request_irq(irq, display_pipe_interrupt_handler, 0, 1770 pdev->name, card_ctx); 1771 if (ret < 0) { 1772 dev_err(&pdev->dev, "request_irq failed\n"); 1773 goto err; 1774 } 1775 1776 card_ctx->irq = irq; 1777 1778 /* only 32bit addressable */ 1779 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1780 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1781 1782 init_channel_allocations(); 1783 1784 card_ctx->num_pipes = pdata->num_pipes; 1785 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1786 1787 for_each_port(card_ctx, port) { 1788 int i; 1789 1790 ctx = &card_ctx->pcm_ctx[port]; 1791 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1792 MAX_CAP_STREAMS, &pcm); 1793 if (ret) 1794 goto err; 1795 1796 /* setup private data which can be retrieved when required */ 1797 pcm->private_data = ctx; 1798 pcm->info_flags = 0; 1799 strlcpy(pcm->name, card->shortname, strlen(card->shortname)); 1800 /* setup the ops for playabck */ 1801 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1802 1803 /* allocate dma pages; 1804 * try to allocate 600k buffer as default which is large enough 1805 */ 1806 snd_pcm_lib_preallocate_pages_for_all(pcm, 1807 SNDRV_DMA_TYPE_DEV_UC, 1808 card->dev, 1809 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER); 1810 1811 /* create controls */ 1812 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1813 struct snd_kcontrol *kctl; 1814 1815 kctl = snd_ctl_new1(&had_controls[i], ctx); 1816 if (!kctl) { 1817 ret = -ENOMEM; 1818 goto err; 1819 } 1820 1821 kctl->id.device = pcm->device; 1822 1823 ret = snd_ctl_add(card, kctl); 1824 if (ret < 0) 1825 goto err; 1826 } 1827 1828 /* Register channel map controls */ 1829 ret = had_register_chmap_ctls(ctx, pcm); 1830 if (ret < 0) 1831 goto err; 1832 1833 ret = had_create_jack(ctx, pcm); 1834 if (ret < 0) 1835 goto err; 1836 } 1837 1838 ret = snd_card_register(card); 1839 if (ret) 1840 goto err; 1841 1842 spin_lock_irq(&pdata->lpe_audio_slock); 1843 pdata->notify_audio_lpe = notify_audio_lpe; 1844 spin_unlock_irq(&pdata->lpe_audio_slock); 1845 1846 pm_runtime_use_autosuspend(&pdev->dev); 1847 pm_runtime_mark_last_busy(&pdev->dev); 1848 1849 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1850 for_each_port(card_ctx, port) { 1851 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1852 1853 schedule_work(&ctx->hdmi_audio_wq); 1854 } 1855 1856 return 0; 1857 1858 err: 1859 snd_card_free(card); 1860 return ret; 1861 } 1862 1863 /* 1864 * hdmi_lpe_audio_remove - stop bridge with i915 1865 * 1866 * This function is called when the platform device is destroyed. 1867 */ 1868 static int hdmi_lpe_audio_remove(struct platform_device *pdev) 1869 { 1870 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1871 1872 snd_card_free(card_ctx->card); 1873 return 0; 1874 } 1875 1876 static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1877 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1878 }; 1879 1880 static struct platform_driver hdmi_lpe_audio_driver = { 1881 .driver = { 1882 .name = "hdmi-lpe-audio", 1883 .pm = &hdmi_lpe_audio_pm, 1884 }, 1885 .probe = hdmi_lpe_audio_probe, 1886 .remove = hdmi_lpe_audio_remove, 1887 }; 1888 1889 module_platform_driver(hdmi_lpe_audio_driver); 1890 MODULE_ALIAS("platform:hdmi_lpe_audio"); 1891 1892 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1893 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1894 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1895 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1896 MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1897 MODULE_LICENSE("GPL v2"); 1898 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}"); 1899