1c6b2f240SFeng Tang# The basic row format is: 2c6b2f240SFeng Tang# LEAF, SUBLEAF, register_name, bits, short_name, long_description 3c6b2f240SFeng Tang 4c6b2f240SFeng Tang# Leaf 00H 5c6b2f240SFeng Tang 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs 6c6b2f240SFeng Tang 7c6b2f240SFeng Tang# Leaf 01H 8c6b2f240SFeng Tang 1, 0, EAX, 3:0, stepping, Stepping ID 9c6b2f240SFeng Tang 1, 0, EAX, 7:4, model, Model 10c6b2f240SFeng Tang 1, 0, EAX, 11:8, family, Family ID 11c6b2f240SFeng Tang 1, 0, EAX, 13:12, processor, Processor Type 12c6b2f240SFeng Tang 1, 0, EAX, 19:16, model_ext, Extended Model ID 13c6b2f240SFeng Tang 1, 0, EAX, 27:20, family_ext, Extended Family ID 14c6b2f240SFeng Tang 15c6b2f240SFeng Tang 1, 0, EBX, 7:0, brand, Brand Index 16c6b2f240SFeng Tang 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes 17c6b2f240SFeng Tang 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package 18c6b2f240SFeng Tang 1, 0, EBX, 31:24, apic_id, Initial APIC ID 19c6b2f240SFeng Tang 20c6b2f240SFeng Tang 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3) 21c6b2f240SFeng Tang 1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported 22c6b2f240SFeng Tang 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout 23c6b2f240SFeng Tang 1, 0, ECX, 3, mwait, MONITOR/MWAIT supported 24c6b2f240SFeng Tang 1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which allows for branch message storage qualified by CPL 25c6b2f240SFeng Tang 1, 0, ECX, 5, vmx, Virtual Machine Extensions supported 26c6b2f240SFeng Tang 1, 0, ECX, 6, smx, Safer Mode Extension supported 27c6b2f240SFeng Tang 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology 28c6b2f240SFeng Tang 1, 0, ECX, 8, tm2, Thermal Monitor 2 29c6b2f240SFeng Tang 1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extensions 3 (SSSE3) 30c6b2f240SFeng Tang 1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definition) 31c6b2f240SFeng Tang 1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon debug supported 32c6b2f240SFeng Tang 1, 0, ECX, 12, fma, FMA extensions using YMM state supported 33c6b2f240SFeng Tang 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported 34c6b2f240SFeng Tang 1, 0, ECX, 14, xtpr_update, xTPR Update Control supported 35c6b2f240SFeng Tang 1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present 36c6b2f240SFeng Tang 1, 0, ECX, 17, pcid, Process-Context Identifiers feature present 37c6b2f240SFeng Tang 1, 0, ECX, 18, dca, Prefetching data from a memory mapped device supported 38c6b2f240SFeng Tang 1, 0, ECX, 19, sse4_1, SSE4.1 feature present 39c6b2f240SFeng Tang 1, 0, ECX, 20, sse4_2, SSE4.2 feature present 40c6b2f240SFeng Tang 1, 0, ECX, 21, x2apic, x2APIC supported 41c6b2f240SFeng Tang 1, 0, ECX, 22, movbe, MOVBE instruction supported 42c6b2f240SFeng Tang 1, 0, ECX, 23, popcnt, POPCNT instruction supported 43c6b2f240SFeng Tang 1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline value 44c6b2f240SFeng Tang 1, 0, ECX, 25, aesni, AESNI instruction supported 45c6b2f240SFeng Tang 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0) 46c6b2f240SFeng Tang 1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to enable XSETBV/XGETBV/XCR0 47c6b2f240SFeng Tang 1, 0, ECX, 28, avx, AVX instruction supported 48c6b2f240SFeng Tang 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported 49c6b2f240SFeng Tang 1, 0, ECX, 30, rdrand, RDRAND instruction supported 50c6b2f240SFeng Tang 51c6b2f240SFeng Tang 1, 0, EDX, 0, fpu, x87 FPU on chip 52c6b2f240SFeng Tang 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement 53c6b2f240SFeng Tang 1, 0, EDX, 2, de, Debugging Extensions 54c6b2f240SFeng Tang 1, 0, EDX, 3, pse, Page Size Extensions 55c6b2f240SFeng Tang 1, 0, EDX, 4, tsc, Time Stamp Counter 56c6b2f240SFeng Tang 1, 0, EDX, 5, msr, RDMSR and WRMSR Support 57c6b2f240SFeng Tang 1, 0, EDX, 6, pae, Physical Address Extensions 58c6b2f240SFeng Tang 1, 0, EDX, 7, mce, Machine Check Exception 59c6b2f240SFeng Tang 1, 0, EDX, 8, cx8, CMPXCHG8B instr 60c6b2f240SFeng Tang 1, 0, EDX, 9, apic, APIC on Chip 61c6b2f240SFeng Tang 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs 62c6b2f240SFeng Tang 1, 0, EDX, 12, mtrr, Memory Type Range Registers 63c6b2f240SFeng Tang 1, 0, EDX, 13, pge, Page Global Bit 64c6b2f240SFeng Tang 1, 0, EDX, 14, mca, Machine Check Architecture 65c6b2f240SFeng Tang 1, 0, EDX, 15, cmov, Conditional Move Instrs 66c6b2f240SFeng Tang 1, 0, EDX, 16, pat, Page Attribute Table 67c6b2f240SFeng Tang 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension 68c6b2f240SFeng Tang 1, 0, EDX, 18, psn, Processor Serial Number 69c6b2f240SFeng Tang 1, 0, EDX, 19, clflush, CLFLUSH instr 70c6b2f240SFeng Tang# 1, 0, EDX, 20, 71c6b2f240SFeng Tang 1, 0, EDX, 21, ds, Debug Store 72c6b2f240SFeng Tang 1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlled Clock Facilities 73c6b2f240SFeng Tang 1, 0, EDX, 23, mmx, Intel MMX Technology 74c6b2f240SFeng Tang 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs 75c6b2f240SFeng Tang 1, 0, EDX, 25, sse, SSE 76c6b2f240SFeng Tang 1, 0, EDX, 26, sse2, SSE2 77c6b2f240SFeng Tang 1, 0, EDX, 27, ss, Self Snoop 78c6b2f240SFeng Tang 1, 0, EDX, 28, hit, Max APIC IDs 79c6b2f240SFeng Tang 1, 0, EDX, 29, tm, Thermal Monitor 80c6b2f240SFeng Tang# 1, 0, EDX, 30, 81c6b2f240SFeng Tang 1, 0, EDX, 31, pbe, Pending Break Enable 82c6b2f240SFeng Tang 83c6b2f240SFeng Tang# Leaf 02H 84c6b2f240SFeng Tang# cache and TLB descriptor info 85c6b2f240SFeng Tang 86c6b2f240SFeng Tang# Leaf 03H 87c6b2f240SFeng Tang# Precessor Serial Number, introduced on Pentium III, not valid for 88c6b2f240SFeng Tang# latest models 89c6b2f240SFeng Tang 90c6b2f240SFeng Tang# Leaf 04H 91c6b2f240SFeng Tang# thread/core and cache topology 92c6b2f240SFeng Tang 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or unified 93c6b2f240SFeng Tang 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1) 94c6b2f240SFeng Tang 4, 0, EAX, 8, cache_self_init, Cache Self Initialization 95c6b2f240SFeng Tang 4, 0, EAX, 9, fully_associate, Fully Associative cache 96c6b2f240SFeng Tang# 4, 0, EAX, 13:10, resvd, resvd 97c6b2f240SFeng Tang 4, 0, EAX, 25:14, max_logical_id, Max number of addressable IDs for logical processors sharing the cache 98c6b2f240SFeng Tang 4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs for processors in phy package 99c6b2f240SFeng Tang 100c6b2f240SFeng Tang 4, 0, EBX, 11:0, cache_linesize, Size of a cache line in bytes 101c6b2f240SFeng Tang 4, 0, EBX, 21:12, cache_partition, Physical Line partitions 102c6b2f240SFeng Tang 4, 0, EBX, 31:22, cache_ways, Ways of associativity 103c6b2f240SFeng Tang 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1 104c6b2f240SFeng Tang 4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level caches of non-originating threads sharing this cache 105c6b2f240SFeng Tang 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower cache level 106c6b2f240SFeng Tang 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing 107c6b2f240SFeng Tang 108c6b2f240SFeng Tang# Leaf 05H 109c6b2f240SFeng Tang# MONITOR/MWAIT 110c6b2f240SFeng Tang 5, 0, EAX, 15:0, min_mon_size, Smallest monitor line size in bytes 111c6b2f240SFeng Tang 5, 0, EBX, 15:0, max_mon_size, Largest monitor line size in bytes 112c6b2f240SFeng Tang 5, 0, ECX, 0, mwait_ext, Enum of Monitor-Mwait extensions supported 113c6b2f240SFeng Tang 5, 0, ECX, 1, mwait_irq_break, Largest monitor line size in bytes 114c6b2f240SFeng Tang 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT 115c6b2f240SFeng Tang 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT 116c6b2f240SFeng Tang 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT 117c6b2f240SFeng Tang 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT 118c6b2f240SFeng Tang 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT 119c6b2f240SFeng Tang 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT 120c6b2f240SFeng Tang 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT 121c6b2f240SFeng Tang 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT 122c6b2f240SFeng Tang 123c6b2f240SFeng Tang# Leaf 06H 124c6b2f240SFeng Tang# Thermal & Power Management 125c6b2f240SFeng Tang 126c6b2f240SFeng Tang 6, 0, EAX, 0, dig_temp, Digital temperature sensor supported 127c6b2f240SFeng Tang 6, 0, EAX, 1, turbo, Intel Turbo Boost 128c6b2f240SFeng Tang 6, 0, EAX, 2, arat, Always running APIC timer 129c6b2f240SFeng Tang# 6, 0, EAX, 3, resv, Reserved 130c6b2f240SFeng Tang 6, 0, EAX, 4, pln, Power limit notifications supported 131c6b2f240SFeng Tang 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension supported 132c6b2f240SFeng Tang 6, 0, EAX, 6, ptm, Package thermal management supported 133c6b2f240SFeng Tang 6, 0, EAX, 7, hwp, HWP base register 134c6b2f240SFeng Tang 6, 0, EAX, 8, hwp_notify, HWP notification 135c6b2f240SFeng Tang 6, 0, EAX, 9, hwp_act_window, HWP activity window 136c6b2f240SFeng Tang 6, 0, EAX, 10, hwp_energy, HWP energy performance preference 137c6b2f240SFeng Tang 6, 0, EAX, 11, hwp_pkg_req, HWP package level request 138c6b2f240SFeng Tang# 6, 0, EAX, 12, resv, Reserved 139c6b2f240SFeng Tang 6, 0, EAX, 13, hdc, HDC base registers supported 140c6b2f240SFeng Tang 6, 0, EAX, 14, turbo3, Turbo Boost Max 3.0 141c6b2f240SFeng Tang 6, 0, EAX, 15, hwp_cap, Highest Performance change supported 142c6b2f240SFeng Tang 6, 0, EAX, 16, hwp_peci, HWP PECI override is supported 143c6b2f240SFeng Tang 6, 0, EAX, 17, hwp_flex, Flexible HWP is supported 144c6b2f240SFeng Tang 6, 0, EAX, 18, hwp_fast, Fast access mode for the IA32_HWP_REQUEST MSR is supported 145c6b2f240SFeng Tang# 6, 0, EAX, 19, resv, Reserved 146c6b2f240SFeng Tang 6, 0, EAX, 20, hwp_ignr, Ignoring Idle Logical Processor HWP request is supported 147c6b2f240SFeng Tang 148c6b2f240SFeng Tang 6, 0, EBX, 3:0, therm_irq_thresh, Number of Interrupt Thresholds in Digital Thermal Sensor 149c6b2f240SFeng Tang 6, 0, ECX, 0, aperfmperf, Presence of IA32_MPERF and IA32_APERF 150c6b2f240SFeng Tang 6, 0, ECX, 3, energ_bias, Performance-energy bias preference supported 151c6b2f240SFeng Tang 152c6b2f240SFeng Tang# Leaf 07H 153c6b2f240SFeng Tang# ECX == 0 154c6b2f240SFeng Tang# AVX512 refers to https://en.wikipedia.org/wiki/AVX-512 155c6b2f240SFeng Tang# XXX: Do we really need to enumerate each and every AVX512 sub features 156c6b2f240SFeng Tang 157c6b2f240SFeng Tang 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported 158c6b2f240SFeng Tang 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported 159c6b2f240SFeng Tang 7, 0, EBX, 2, sgx, Software Guard Extensions 160c6b2f240SFeng Tang 7, 0, EBX, 3, bmi1, BMI1 161c6b2f240SFeng Tang 7, 0, EBX, 4, hle, Hardware Lock Elision 162c6b2f240SFeng Tang 7, 0, EBX, 5, avx2, AVX2 163c6b2f240SFeng Tang# 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions 164c6b2f240SFeng Tang 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention 165c6b2f240SFeng Tang 7, 0, EBX, 8, bmi2, BMI2 166c6b2f240SFeng Tang 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB 167c6b2f240SFeng Tang 7, 0, EBX, 10, invpcid, INVPCID instruction 168c6b2f240SFeng Tang 7, 0, EBX, 11, rtm, Restricted Transactional Memory 169c6b2f240SFeng Tang 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability 170c6b2f240SFeng Tang 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS 171c6b2f240SFeng Tang 7, 0, EBX, 14, mpx, Memory Protection Extensions 172c6b2f240SFeng Tang 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability 173c6b2f240SFeng Tang 7, 0, EBX, 16, avx512f, AVX512 Foundation instr 174c6b2f240SFeng Tang 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr 175c6b2f240SFeng Tang 7, 0, EBX, 18, rdseed, RDSEED instr 176c6b2f240SFeng Tang 7, 0, EBX, 19, adx, ADX instr 177c6b2f240SFeng Tang 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention 178c6b2f240SFeng Tang 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add 179c6b2f240SFeng Tang# 7, 0, EBX, 22, resvd, resvd 180c6b2f240SFeng Tang 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr 181c6b2f240SFeng Tang 7, 0, EBX, 24, clwb, CLWB instr 182c6b2f240SFeng Tang 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr 183c6b2f240SFeng Tang 7, 0, EBX, 26, avx512pf, Prefetch 184c6b2f240SFeng Tang 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr 185c6b2f240SFeng Tang 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr 186c6b2f240SFeng Tang 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr 1874e347bdfSTerry Bowman 7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr 1884e347bdfSTerry Bowman 7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL) 189c6b2f240SFeng Tang 7, 0, ECX, 0, prefetchwt1, X 190c6b2f240SFeng Tang 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions 191c6b2f240SFeng Tang 7, 0, ECX, 2, umip, User-mode Instruction Prevention 192c6b2f240SFeng Tang 193c6b2f240SFeng Tang 7, 0, ECX, 3, pku, Protection Keys for User-mode pages 194c6b2f240SFeng Tang 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys 195c6b2f240SFeng Tang# 7, 0, ECX, 16:5, resvd, resvd 196c6b2f240SFeng Tang 7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode 197c6b2f240SFeng Tang 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX 198c6b2f240SFeng Tang# 7, 0, ECX, 29:23, resvd, resvd 199c6b2f240SFeng Tang 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration 200c6b2f240SFeng Tang# 7, 0, ECX, 31, resvd, resvd 201c6b2f240SFeng Tang 202c6b2f240SFeng Tang# Leaf 08H 203c6b2f240SFeng Tang# 204c6b2f240SFeng Tang 205c6b2f240SFeng Tang 206c6b2f240SFeng Tang# Leaf 09H 207c6b2f240SFeng Tang# Direct Cache Access (DCA) information 208c6b2f240SFeng Tang 9, 0, ECX, 31:0, dca_cap, The value of IA32_PLATFORM_DCA_CAP 209c6b2f240SFeng Tang 210c6b2f240SFeng Tang# Leaf 0AH 211c6b2f240SFeng Tang# Architectural Performance Monitoring 212c6b2f240SFeng Tang# 213c6b2f240SFeng Tang# Do we really need to print out the PMU related stuff? 214c6b2f240SFeng Tang# Does normal user really care about it? 215c6b2f240SFeng Tang# 216c6b2f240SFeng Tang 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version 217c6b2f240SFeng Tang 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU 218c6b2f240SFeng Tang 0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter 219c6b2f240SFeng Tang 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events 220c6b2f240SFeng Tang 221c6b2f240SFeng Tang 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not available 222c6b2f240SFeng Tang 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired event not available 223c6b2f240SFeng Tang 0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles event not available 224c6b2f240SFeng Tang 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache reference event not available 225c6b2f240SFeng Tang 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses event not available 226c6b2f240SFeng Tang 0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instruction retired event not available 227c6b2f240SFeng Tang 0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredict retired event not available 228c6b2f240SFeng Tang 229c6b2f240SFeng Tang 0xA, 0, ECX, 4:0, pmu_fixed_cnt_num, Performance Monitoring Unit version 230c6b2f240SFeng Tang 0xA, 0, ECX, 12:5, pmu_fixed_cnt_bits, Numer of PMU counters per logical CPU 231c6b2f240SFeng Tang 232c6b2f240SFeng Tang# Leaf 0BH 233c6b2f240SFeng Tang# Extended Topology Enumeration Leaf 234c6b2f240SFeng Tang# 235c6b2f240SFeng Tang 236c6b2f240SFeng Tang 0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type 237c6b2f240SFeng Tang 0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at this level type 238c6b2f240SFeng Tang 0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core 239c6b2f240SFeng Tang 0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical processor 240c6b2f240SFeng Tang 241c6b2f240SFeng Tang 242c6b2f240SFeng Tang# Leaf 0DH 243c6b2f240SFeng Tang# Processor Extended State 244c6b2f240SFeng Tang 245c6b2f240SFeng Tang 0xD, 0, EAX, 0, x87, X87 state 246c6b2f240SFeng Tang 0xD, 0, EAX, 1, sse, SSE state 247c6b2f240SFeng Tang 0xD, 0, EAX, 2, avx, AVX state 248c6b2f240SFeng Tang 0xD, 0, EAX, 4:3, mpx, MPX state 249c6b2f240SFeng Tang 0xD, 0, EAX, 7:5, avx512, AVX-512 state 250c6b2f240SFeng Tang 0xD, 0, EAX, 9, pkru, PKRU state 251c6b2f240SFeng Tang 252c6b2f240SFeng Tang 0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0 253c6b2f240SFeng Tang 0xD, 0, ECX, 31:0, max_sz_xsave, Maximum size (bytes) of the XSAVE/XRSTOR save area 254c6b2f240SFeng Tang 255c6b2f240SFeng Tang 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available 256c6b2f240SFeng Tang 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported 257c6b2f240SFeng Tang 0xD, 1, EAX, 2, xgetbv, XGETBV supported 258c6b2f240SFeng Tang 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported 259c6b2f240SFeng Tang 260c6b2f240SFeng Tang 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0 261c6b2f240SFeng Tang 0xD, 1, ECX, 8, pt, PT state 262c6b2f240SFeng Tang 0xD, 1, ECX, 11, cet_usr, CET user state 263c6b2f240SFeng Tang 0xD, 1, ECX, 12, cet_supv, CET supervisor state 264c6b2f240SFeng Tang 0xD, 1, ECX, 13, hdc, HDC state 265c6b2f240SFeng Tang 0xD, 1, ECX, 16, hwp, HWP state 266c6b2f240SFeng Tang 267c6b2f240SFeng Tang# Leaf 0FH 268c6b2f240SFeng Tang# Intel RDT Monitoring 269c6b2f240SFeng Tang 270c6b2f240SFeng Tang 0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RMID within this physical processor of all types 271c6b2f240SFeng Tang 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported 272c6b2f240SFeng Tang 273c6b2f240SFeng Tang 0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of RMID of this types 274c6b2f240SFeng Tang 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported 275c6b2f240SFeng Tang 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported 276c6b2f240SFeng Tang 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported 277c6b2f240SFeng Tang 278c6b2f240SFeng Tang# Leaf 10H 279c6b2f240SFeng Tang# Intel RDT Allocation 280c6b2f240SFeng Tang 281c6b2f240SFeng Tang 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported 282c6b2f240SFeng Tang 0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation supported 283c6b2f240SFeng Tang 0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation supported 284c6b2f240SFeng Tang 285c6b2f240SFeng Tang 286c6b2f240SFeng Tang# Leaf 12H 287c6b2f240SFeng Tang# SGX Capability 288c6b2f240SFeng Tang# 289c6b2f240SFeng Tang# Some detailed SGX features not added yet 290c6b2f240SFeng Tang 291c6b2f240SFeng Tang 0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported 292c6b2f240SFeng Tang 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported 293c6b2f240SFeng Tang 294c6b2f240SFeng Tang 295c6b2f240SFeng Tang# Leaf 14H 296c6b2f240SFeng Tang# Intel Processor Tracer 297c6b2f240SFeng Tang# 298c6b2f240SFeng Tang 299c6b2f240SFeng Tang# Leaf 15H 300c6b2f240SFeng Tang# Time Stamp Counter and Nominal Core Crystal Clock Information 301c6b2f240SFeng Tang 302c6b2f240SFeng Tang 0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TSC/”core crystal clock” ratio 303c6b2f240SFeng Tang 0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/”core crystal clock” ratio 304c6b2f240SFeng Tang 0x15, 0, ECX, 31:0, nom_freq, Nominal frequency of the core crystal clock in Hz 305c6b2f240SFeng Tang 306c6b2f240SFeng Tang# Leaf 16H 307c6b2f240SFeng Tang# Processor Frequency Information 308c6b2f240SFeng Tang 309c6b2f240SFeng Tang 0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in MHz 310c6b2f240SFeng Tang 0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz 311c6b2f240SFeng Tang 0x16, 0, ECX, 15:0, bus_freq, Bus (Reference) Frequency in MHz 312c6b2f240SFeng Tang 313c6b2f240SFeng Tang# Leaf 17H 314c6b2f240SFeng Tang# System-On-Chip Vendor Attribute 315c6b2f240SFeng Tang 316c6b2f240SFeng Tang 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported sub-leaf 317c6b2f240SFeng Tang 0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID 318c6b2f240SFeng Tang 0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an industry standard scheme 319c6b2f240SFeng Tang 0x17, 0, ECX, 31:0, soc_pid, SOC Project ID assigned by vendor 320c6b2f240SFeng Tang 0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID 321c6b2f240SFeng Tang 322c6b2f240SFeng Tang# Leaf 18H 323c6b2f240SFeng Tang# Deterministic Address Translation Parameters 324c6b2f240SFeng Tang 325c6b2f240SFeng Tang 326c6b2f240SFeng Tang# Leaf 19H 327c6b2f240SFeng Tang# Key Locker Leaf 328c6b2f240SFeng Tang 329c6b2f240SFeng Tang 330c6b2f240SFeng Tang# Leaf 1AH 331c6b2f240SFeng Tang# Hybrid Information 332c6b2f240SFeng Tang 333c6b2f240SFeng Tang 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core 334c6b2f240SFeng Tang 335c6b2f240SFeng Tang 336c6b2f240SFeng Tang# Leaf 1FH 337c6b2f240SFeng Tang# V2 Extended Topology - A preferred superset to leaf 0BH 338c6b2f240SFeng Tang 339c6b2f240SFeng Tang 340c6b2f240SFeng Tang# According to SDM 341c6b2f240SFeng Tang# 40000000H - 4FFFFFFFH is invalid range 342c6b2f240SFeng Tang 343c6b2f240SFeng Tang# Leaf 80000001H 344c6b2f240SFeng Tang# Extended Processor Signature and Feature Bits 345c6b2f240SFeng Tang 346*ce22e434STerry Bowman0x80000001, 0, EAX, 27:20, extfamily, Extended family 347*ce22e434STerry Bowman0x80000001, 0, EAX, 19:16, extmodel, Extended model 348*ce22e434STerry Bowman0x80000001, 0, EAX, 11:8, basefamily, Description of Family 349*ce22e434STerry Bowman0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product 350*ce22e434STerry Bowman0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) for a specific model 351c6b2f240SFeng Tang 352*ce22e434STerry Bowman0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type 353*ce22e434STerry Bowman 354*ce22e434STerry Bowman0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode 355*ce22e434STerry Bowman0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode 356*ce22e434STerry Bowman0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, and INVLPGA 357*ce22e434STerry Bowman0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space 358*ce22e434STerry Bowman0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV CR0 means MOV CR8 359*ce22e434STerry Bowman0x80000001, 0, ECX, 5, lzcnt, LZCNT 360*ce22e434STerry Bowman0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support 361*ce22e434STerry Bowman0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode 362*ce22e434STerry Bowman0x80000001, 0, ECX, 8, prefetchw, PREFETCHW 363*ce22e434STerry Bowman0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support 364*ce22e434STerry Bowman0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling 365*ce22e434STerry Bowman0x80000001, 0, ECX, 11, xop, Extended operation support 366*ce22e434STerry Bowman0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support 367*ce22e434STerry Bowman0x80000001, 0, ECX, 13, wdt, Watchdog timer support 368*ce22e434STerry Bowman0x80000001, 0, ECX, 15, lwp, Lightweight profiling support 369*ce22e434STerry Bowman0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support 370*ce22e434STerry Bowman0x80000001, 0, ECX, 17, tce, Translation cache extension 371*ce22e434STerry Bowman0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for Core::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId 372*ce22e434STerry Bowman0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR 373*ce22e434STerry Bowman0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::X86::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR 374*ce22e434STerry Bowman0x80000001, 0, ECX, 26, databreakpointextension, Indicates data breakpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADDR_MASK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK 375*ce22e434STerry Bowman0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supported 376*ce22e434STerry Bowman0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 performance counter extensions 377*ce22e434STerry Bowman0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capability is supported 378*ce22e434STerry Bowman0x80000001, 0, ECX, 30, admskextn, Indicates support for address mask extension (to 32 bits and to all 4 DRs) for instruction breakpoints 379*ce22e434STerry Bowman 380*ce22e434STerry Bowman0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip 381*ce22e434STerry Bowman0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements 382*ce22e434STerry Bowman0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, CR4.DE 383*ce22e434STerry Bowman0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages) 384*ce22e434STerry Bowman0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD 385*ce22e434STerry Bowman0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instructions 386*ce22e434STerry Bowman0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE) 387*ce22e434STerry Bowman0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE 388*ce22e434STerry Bowman0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction 389*ce22e434STerry Bowman0x80000001, 0, EDX, 9, apic, advanced programmable interrupt controller (APIC) exists and is enabled 390c6b2f240SFeng Tang0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported 391*ce22e434STerry Bowman0x80000001, 0, EDX, 12, mtrr, Memory-type range registers 392*ce22e434STerry Bowman0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE 393*ce22e434STerry Bowman0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP 394*ce22e434STerry Bowman0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV, FCOMI, FCMOV 395*ce22e434STerry Bowman0x80000001, 0, EDX, 16, pat, Page attribute table 396*ce22e434STerry Bowman0x80000001, 0, EDX, 17, pse36, Page-size extensions 397c6b2f240SFeng Tang0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available 398*ce22e434STerry Bowman0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions 399*ce22e434STerry Bowman0x80000001, 0, EDX, 23, mmx, MMX instructions 400*ce22e434STerry Bowman0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions 401*ce22e434STerry Bowman0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimizations 402c6b2f240SFeng Tang0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported 403c6b2f240SFeng Tang0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available 404*ce22e434STerry Bowman0x80000001, 0, EDX, 29, lm, 64b Architecture supported 405*ce22e434STerry Bowman0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instructions 406*ce22e434STerry Bowman0x80000001, 0, EDX, 31, threednow, 3DNow! instructions 407c6b2f240SFeng Tang 408c6b2f240SFeng Tang# Leaf 80000002H/80000003H/80000004H 409c6b2f240SFeng Tang# Processor Brand String 410c6b2f240SFeng Tang 411c6b2f240SFeng Tang# Leaf 80000005H 412c6b2f240SFeng Tang# Reserved 413c6b2f240SFeng Tang 414c6b2f240SFeng Tang# Leaf 80000006H 415c6b2f240SFeng Tang# Extended L2 Cache Features 416c6b2f240SFeng Tang 417c6b2f240SFeng Tang0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes 418c6b2f240SFeng Tang0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity 419c6b2f240SFeng Tang0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units 420c6b2f240SFeng Tang 421c6b2f240SFeng Tang 422c6b2f240SFeng Tang# Leaf 80000007H 423c6b2f240SFeng Tang 424c6b2f240SFeng Tang0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available 425c6b2f240SFeng Tang 426c6b2f240SFeng Tang 427c6b2f240SFeng Tang# Leaf 80000008H 428c6b2f240SFeng Tang 429c6b2f240SFeng Tang0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits 430c6b2f240SFeng Tang0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits 431c6b2f240SFeng Tang0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD 4322d4177c0SBorislav Petkov 433f281854fSBorislav Petkov# 0x8000001E 434f281854fSBorislav Petkov# EAX: Extended APIC ID 435f281854fSBorislav Petkov0x8000001E, 0, EAX, 31:0, extended_apic_id, Extended APIC ID 436f281854fSBorislav Petkov# EBX: Core Identifiers 437f281854fSBorislav Petkov0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID 438f281854fSBorislav Petkov0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per core is threads_per_core + 1 439f281854fSBorislav Petkov# ECX: Node Identifiers 440f281854fSBorislav Petkov0x8000001E, 0, ECX, 7:0, node_id, Node ID 441f281854fSBorislav Petkov0x8000001E, 0, ECX, 10:8, nodes_per_processor, Nodes per processor { 0: 1 node, else reserved } 442f281854fSBorislav Petkov 4432d4177c0SBorislav Petkov# 8000001F: AMD Secure Encryption 4442d4177c0SBorislav Petkov0x8000001F, 0, EAX, 0, sme, Secure Memory Encryption 4452d4177c0SBorislav Petkov0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization 4462d4177c0SBorislav Petkov0x8000001F, 0, EAX, 2, vmpgflush, VM Page Flush MSR 4472d4177c0SBorislav Petkov0x8000001F, 0, EAX, 3, seves, SEV Encrypted State 4482d4177c0SBorislav Petkov0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memory encryption 4492d4177c0SBorislav Petkov0x8000001F, 0, EBX, 11:6, mem_encrypt_physaddr_width, Reduction of physical address space in bits with SME enabled 4502d4177c0SBorislav Petkov0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-enabled guest 4512d4177c0SBorislav Petkov0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest 452