1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169 }; 170 171 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172 /* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182 enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ 208 209 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 210 }; 211 212 enum perf_branch_sample_type { 213 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 214 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 215 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 216 217 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 218 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 220 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 221 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 223 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 224 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 225 226 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 227 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 228 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 229 230 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 231 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 232 233 PERF_SAMPLE_BRANCH_TYPE_SAVE = 234 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 235 236 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 237 238 PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 239 240 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 241 }; 242 243 /* 244 * Common flow change classification 245 */ 246 enum { 247 PERF_BR_UNKNOWN = 0, /* unknown */ 248 PERF_BR_COND = 1, /* conditional */ 249 PERF_BR_UNCOND = 2, /* unconditional */ 250 PERF_BR_IND = 3, /* indirect */ 251 PERF_BR_CALL = 4, /* function call */ 252 PERF_BR_IND_CALL = 5, /* indirect function call */ 253 PERF_BR_RET = 6, /* function return */ 254 PERF_BR_SYSCALL = 7, /* syscall */ 255 PERF_BR_SYSRET = 8, /* syscall return */ 256 PERF_BR_COND_CALL = 9, /* conditional function call */ 257 PERF_BR_COND_RET = 10, /* conditional function return */ 258 PERF_BR_ERET = 11, /* exception return */ 259 PERF_BR_IRQ = 12, /* irq */ 260 PERF_BR_SERROR = 13, /* system error */ 261 PERF_BR_NO_TX = 14, /* not in transaction */ 262 PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 263 PERF_BR_MAX, 264 }; 265 266 enum { 267 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 268 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 269 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 270 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 271 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 272 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 273 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 274 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 275 PERF_BR_NEW_MAX, 276 }; 277 278 enum { 279 PERF_BR_PRIV_UNKNOWN = 0, 280 PERF_BR_PRIV_USER = 1, 281 PERF_BR_PRIV_KERNEL = 2, 282 PERF_BR_PRIV_HV = 3, 283 }; 284 285 #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1 286 #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2 287 #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3 288 #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4 289 #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5 290 291 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 292 (PERF_SAMPLE_BRANCH_USER|\ 293 PERF_SAMPLE_BRANCH_KERNEL|\ 294 PERF_SAMPLE_BRANCH_HV) 295 296 /* 297 * Values to determine ABI of the registers dump. 298 */ 299 enum perf_sample_regs_abi { 300 PERF_SAMPLE_REGS_ABI_NONE = 0, 301 PERF_SAMPLE_REGS_ABI_32 = 1, 302 PERF_SAMPLE_REGS_ABI_64 = 2, 303 }; 304 305 /* 306 * Values for the memory transaction event qualifier, mostly for 307 * abort events. Multiple bits can be set. 308 */ 309 enum { 310 PERF_TXN_ELISION = (1 << 0), /* From elision */ 311 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 312 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 313 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 314 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 315 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 316 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 317 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 318 319 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 320 321 /* bits 32..63 are reserved for the abort code */ 322 323 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 324 PERF_TXN_ABORT_SHIFT = 32, 325 }; 326 327 /* 328 * The format of the data returned by read() on a perf event fd, 329 * as specified by attr.read_format: 330 * 331 * struct read_format { 332 * { u64 value; 333 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 334 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 335 * { u64 id; } && PERF_FORMAT_ID 336 * { u64 lost; } && PERF_FORMAT_LOST 337 * } && !PERF_FORMAT_GROUP 338 * 339 * { u64 nr; 340 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 341 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 342 * { u64 value; 343 * { u64 id; } && PERF_FORMAT_ID 344 * { u64 lost; } && PERF_FORMAT_LOST 345 * } cntr[nr]; 346 * } && PERF_FORMAT_GROUP 347 * }; 348 */ 349 enum perf_event_read_format { 350 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 351 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 352 PERF_FORMAT_ID = 1U << 2, 353 PERF_FORMAT_GROUP = 1U << 3, 354 PERF_FORMAT_LOST = 1U << 4, 355 356 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 357 }; 358 359 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 360 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 361 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 362 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 363 /* add: sample_stack_user */ 364 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 365 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 366 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 367 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 368 369 /* 370 * Hardware event_id to monitor via a performance monitoring event: 371 * 372 * @sample_max_stack: Max number of frame pointers in a callchain, 373 * should be < /proc/sys/kernel/perf_event_max_stack 374 */ 375 struct perf_event_attr { 376 377 /* 378 * Major type: hardware/software/tracepoint/etc. 379 */ 380 __u32 type; 381 382 /* 383 * Size of the attr structure, for fwd/bwd compat. 384 */ 385 __u32 size; 386 387 /* 388 * Type specific configuration information. 389 */ 390 __u64 config; 391 392 union { 393 __u64 sample_period; 394 __u64 sample_freq; 395 }; 396 397 __u64 sample_type; 398 __u64 read_format; 399 400 __u64 disabled : 1, /* off by default */ 401 inherit : 1, /* children inherit it */ 402 pinned : 1, /* must always be on PMU */ 403 exclusive : 1, /* only group on PMU */ 404 exclude_user : 1, /* don't count user */ 405 exclude_kernel : 1, /* ditto kernel */ 406 exclude_hv : 1, /* ditto hypervisor */ 407 exclude_idle : 1, /* don't count when idle */ 408 mmap : 1, /* include mmap data */ 409 comm : 1, /* include comm data */ 410 freq : 1, /* use freq, not period */ 411 inherit_stat : 1, /* per task counts */ 412 enable_on_exec : 1, /* next exec enables */ 413 task : 1, /* trace fork/exit */ 414 watermark : 1, /* wakeup_watermark */ 415 /* 416 * precise_ip: 417 * 418 * 0 - SAMPLE_IP can have arbitrary skid 419 * 1 - SAMPLE_IP must have constant skid 420 * 2 - SAMPLE_IP requested to have 0 skid 421 * 3 - SAMPLE_IP must have 0 skid 422 * 423 * See also PERF_RECORD_MISC_EXACT_IP 424 */ 425 precise_ip : 2, /* skid constraint */ 426 mmap_data : 1, /* non-exec mmap data */ 427 sample_id_all : 1, /* sample_type all events */ 428 429 exclude_host : 1, /* don't count in host */ 430 exclude_guest : 1, /* don't count in guest */ 431 432 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 433 exclude_callchain_user : 1, /* exclude user callchains */ 434 mmap2 : 1, /* include mmap with inode data */ 435 comm_exec : 1, /* flag comm events that are due to an exec */ 436 use_clockid : 1, /* use @clockid for time fields */ 437 context_switch : 1, /* context switch data */ 438 write_backward : 1, /* Write ring buffer from end to beginning */ 439 namespaces : 1, /* include namespaces data */ 440 ksymbol : 1, /* include ksymbol events */ 441 bpf_event : 1, /* include bpf events */ 442 aux_output : 1, /* generate AUX records instead of events */ 443 cgroup : 1, /* include cgroup events */ 444 text_poke : 1, /* include text poke events */ 445 build_id : 1, /* use build id in mmap2 events */ 446 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 447 remove_on_exec : 1, /* event is removed from task on exec */ 448 sigtrap : 1, /* send synchronous SIGTRAP on event */ 449 __reserved_1 : 26; 450 451 union { 452 __u32 wakeup_events; /* wakeup every n events */ 453 __u32 wakeup_watermark; /* bytes before wakeup */ 454 }; 455 456 __u32 bp_type; 457 union { 458 __u64 bp_addr; 459 __u64 kprobe_func; /* for perf_kprobe */ 460 __u64 uprobe_path; /* for perf_uprobe */ 461 __u64 config1; /* extension of config */ 462 }; 463 union { 464 __u64 bp_len; 465 __u64 kprobe_addr; /* when kprobe_func == NULL */ 466 __u64 probe_offset; /* for perf_[k,u]probe */ 467 __u64 config2; /* extension of config1 */ 468 }; 469 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 470 471 /* 472 * Defines set of user regs to dump on samples. 473 * See asm/perf_regs.h for details. 474 */ 475 __u64 sample_regs_user; 476 477 /* 478 * Defines size of the user stack to dump on samples. 479 */ 480 __u32 sample_stack_user; 481 482 __s32 clockid; 483 /* 484 * Defines set of regs to dump for each sample 485 * state captured on: 486 * - precise = 0: PMU interrupt 487 * - precise > 0: sampled instruction 488 * 489 * See asm/perf_regs.h for details. 490 */ 491 __u64 sample_regs_intr; 492 493 /* 494 * Wakeup watermark for AUX area 495 */ 496 __u32 aux_watermark; 497 __u16 sample_max_stack; 498 __u16 __reserved_2; 499 __u32 aux_sample_size; 500 __u32 __reserved_3; 501 502 /* 503 * User provided data if sigtrap=1, passed back to user via 504 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 505 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 506 * truncated accordingly on 32 bit architectures. 507 */ 508 __u64 sig_data; 509 }; 510 511 /* 512 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 513 * to query bpf programs attached to the same perf tracepoint 514 * as the given perf event. 515 */ 516 struct perf_event_query_bpf { 517 /* 518 * The below ids array length 519 */ 520 __u32 ids_len; 521 /* 522 * Set by the kernel to indicate the number of 523 * available programs 524 */ 525 __u32 prog_cnt; 526 /* 527 * User provided buffer to store program ids 528 */ 529 __u32 ids[]; 530 }; 531 532 /* 533 * Ioctls that can be done on a perf event fd: 534 */ 535 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 536 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 537 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 538 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 539 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 540 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 541 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 542 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 543 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 544 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 545 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 546 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 547 548 enum perf_event_ioc_flags { 549 PERF_IOC_FLAG_GROUP = 1U << 0, 550 }; 551 552 /* 553 * Structure of the page that can be mapped via mmap 554 */ 555 struct perf_event_mmap_page { 556 __u32 version; /* version number of this structure */ 557 __u32 compat_version; /* lowest version this is compat with */ 558 559 /* 560 * Bits needed to read the hw events in user-space. 561 * 562 * u32 seq, time_mult, time_shift, index, width; 563 * u64 count, enabled, running; 564 * u64 cyc, time_offset; 565 * s64 pmc = 0; 566 * 567 * do { 568 * seq = pc->lock; 569 * barrier() 570 * 571 * enabled = pc->time_enabled; 572 * running = pc->time_running; 573 * 574 * if (pc->cap_usr_time && enabled != running) { 575 * cyc = rdtsc(); 576 * time_offset = pc->time_offset; 577 * time_mult = pc->time_mult; 578 * time_shift = pc->time_shift; 579 * } 580 * 581 * index = pc->index; 582 * count = pc->offset; 583 * if (pc->cap_user_rdpmc && index) { 584 * width = pc->pmc_width; 585 * pmc = rdpmc(index - 1); 586 * } 587 * 588 * barrier(); 589 * } while (pc->lock != seq); 590 * 591 * NOTE: for obvious reason this only works on self-monitoring 592 * processes. 593 */ 594 __u32 lock; /* seqlock for synchronization */ 595 __u32 index; /* hardware event identifier */ 596 __s64 offset; /* add to hardware event value */ 597 __u64 time_enabled; /* time event active */ 598 __u64 time_running; /* time event on cpu */ 599 union { 600 __u64 capabilities; 601 struct { 602 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 603 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 604 605 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 606 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 607 cap_user_time_zero : 1, /* The time_zero field is used */ 608 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 609 cap_____res : 58; 610 }; 611 }; 612 613 /* 614 * If cap_user_rdpmc this field provides the bit-width of the value 615 * read using the rdpmc() or equivalent instruction. This can be used 616 * to sign extend the result like: 617 * 618 * pmc <<= 64 - width; 619 * pmc >>= 64 - width; // signed shift right 620 * count += pmc; 621 */ 622 __u16 pmc_width; 623 624 /* 625 * If cap_usr_time the below fields can be used to compute the time 626 * delta since time_enabled (in ns) using rdtsc or similar. 627 * 628 * u64 quot, rem; 629 * u64 delta; 630 * 631 * quot = (cyc >> time_shift); 632 * rem = cyc & (((u64)1 << time_shift) - 1); 633 * delta = time_offset + quot * time_mult + 634 * ((rem * time_mult) >> time_shift); 635 * 636 * Where time_offset,time_mult,time_shift and cyc are read in the 637 * seqcount loop described above. This delta can then be added to 638 * enabled and possible running (if index), improving the scaling: 639 * 640 * enabled += delta; 641 * if (index) 642 * running += delta; 643 * 644 * quot = count / running; 645 * rem = count % running; 646 * count = quot * enabled + (rem * enabled) / running; 647 */ 648 __u16 time_shift; 649 __u32 time_mult; 650 __u64 time_offset; 651 /* 652 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 653 * from sample timestamps. 654 * 655 * time = timestamp - time_zero; 656 * quot = time / time_mult; 657 * rem = time % time_mult; 658 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 659 * 660 * And vice versa: 661 * 662 * quot = cyc >> time_shift; 663 * rem = cyc & (((u64)1 << time_shift) - 1); 664 * timestamp = time_zero + quot * time_mult + 665 * ((rem * time_mult) >> time_shift); 666 */ 667 __u64 time_zero; 668 669 __u32 size; /* Header size up to __reserved[] fields. */ 670 __u32 __reserved_1; 671 672 /* 673 * If cap_usr_time_short, the hardware clock is less than 64bit wide 674 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 675 * 676 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 677 * 678 * NOTE: this form is explicitly chosen such that cap_usr_time_short 679 * is a correction on top of cap_usr_time, and code that doesn't 680 * know about cap_usr_time_short still works under the assumption 681 * the counter doesn't wrap. 682 */ 683 __u64 time_cycles; 684 __u64 time_mask; 685 686 /* 687 * Hole for extension of the self monitor capabilities 688 */ 689 690 __u8 __reserved[116*8]; /* align to 1k. */ 691 692 /* 693 * Control data for the mmap() data buffer. 694 * 695 * User-space reading the @data_head value should issue an smp_rmb(), 696 * after reading this value. 697 * 698 * When the mapping is PROT_WRITE the @data_tail value should be 699 * written by userspace to reflect the last read data, after issueing 700 * an smp_mb() to separate the data read from the ->data_tail store. 701 * In this case the kernel will not over-write unread data. 702 * 703 * See perf_output_put_handle() for the data ordering. 704 * 705 * data_{offset,size} indicate the location and size of the perf record 706 * buffer within the mmapped area. 707 */ 708 __u64 data_head; /* head in the data section */ 709 __u64 data_tail; /* user-space written tail */ 710 __u64 data_offset; /* where the buffer starts */ 711 __u64 data_size; /* data buffer size */ 712 713 /* 714 * AUX area is defined by aux_{offset,size} fields that should be set 715 * by the userspace, so that 716 * 717 * aux_offset >= data_offset + data_size 718 * 719 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 720 * 721 * Ring buffer pointers aux_{head,tail} have the same semantics as 722 * data_{head,tail} and same ordering rules apply. 723 */ 724 __u64 aux_head; 725 __u64 aux_tail; 726 __u64 aux_offset; 727 __u64 aux_size; 728 }; 729 730 /* 731 * The current state of perf_event_header::misc bits usage: 732 * ('|' used bit, '-' unused bit) 733 * 734 * 012 CDEF 735 * |||---------|||| 736 * 737 * Where: 738 * 0-2 CPUMODE_MASK 739 * 740 * C PROC_MAP_PARSE_TIMEOUT 741 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 742 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 743 * F (reserved) 744 */ 745 746 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 747 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 748 #define PERF_RECORD_MISC_KERNEL (1 << 0) 749 #define PERF_RECORD_MISC_USER (2 << 0) 750 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 751 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 752 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 753 754 /* 755 * Indicates that /proc/PID/maps parsing are truncated by time out. 756 */ 757 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 758 /* 759 * Following PERF_RECORD_MISC_* are used on different 760 * events, so can reuse the same bit position: 761 * 762 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 763 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 764 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 765 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 766 */ 767 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 768 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 769 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 770 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 771 /* 772 * These PERF_RECORD_MISC_* flags below are safely reused 773 * for the following events: 774 * 775 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 776 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 777 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 778 * 779 * 780 * PERF_RECORD_MISC_EXACT_IP: 781 * Indicates that the content of PERF_SAMPLE_IP points to 782 * the actual instruction that triggered the event. See also 783 * perf_event_attr::precise_ip. 784 * 785 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 786 * Indicates that thread was preempted in TASK_RUNNING state. 787 * 788 * PERF_RECORD_MISC_MMAP_BUILD_ID: 789 * Indicates that mmap2 event carries build id data. 790 */ 791 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 792 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 793 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 794 /* 795 * Reserve the last bit to indicate some extended misc field 796 */ 797 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 798 799 struct perf_event_header { 800 __u32 type; 801 __u16 misc; 802 __u16 size; 803 }; 804 805 struct perf_ns_link_info { 806 __u64 dev; 807 __u64 ino; 808 }; 809 810 enum { 811 NET_NS_INDEX = 0, 812 UTS_NS_INDEX = 1, 813 IPC_NS_INDEX = 2, 814 PID_NS_INDEX = 3, 815 USER_NS_INDEX = 4, 816 MNT_NS_INDEX = 5, 817 CGROUP_NS_INDEX = 6, 818 819 NR_NAMESPACES, /* number of available namespaces */ 820 }; 821 822 enum perf_event_type { 823 824 /* 825 * If perf_event_attr.sample_id_all is set then all event types will 826 * have the sample_type selected fields related to where/when 827 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 828 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 829 * just after the perf_event_header and the fields already present for 830 * the existing fields, i.e. at the end of the payload. That way a newer 831 * perf.data file will be supported by older perf tools, with these new 832 * optional fields being ignored. 833 * 834 * struct sample_id { 835 * { u32 pid, tid; } && PERF_SAMPLE_TID 836 * { u64 time; } && PERF_SAMPLE_TIME 837 * { u64 id; } && PERF_SAMPLE_ID 838 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 839 * { u32 cpu, res; } && PERF_SAMPLE_CPU 840 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 841 * } && perf_event_attr::sample_id_all 842 * 843 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 844 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 845 * relative to header.size. 846 */ 847 848 /* 849 * The MMAP events record the PROT_EXEC mappings so that we can 850 * correlate userspace IPs to code. They have the following structure: 851 * 852 * struct { 853 * struct perf_event_header header; 854 * 855 * u32 pid, tid; 856 * u64 addr; 857 * u64 len; 858 * u64 pgoff; 859 * char filename[]; 860 * struct sample_id sample_id; 861 * }; 862 */ 863 PERF_RECORD_MMAP = 1, 864 865 /* 866 * struct { 867 * struct perf_event_header header; 868 * u64 id; 869 * u64 lost; 870 * struct sample_id sample_id; 871 * }; 872 */ 873 PERF_RECORD_LOST = 2, 874 875 /* 876 * struct { 877 * struct perf_event_header header; 878 * 879 * u32 pid, tid; 880 * char comm[]; 881 * struct sample_id sample_id; 882 * }; 883 */ 884 PERF_RECORD_COMM = 3, 885 886 /* 887 * struct { 888 * struct perf_event_header header; 889 * u32 pid, ppid; 890 * u32 tid, ptid; 891 * u64 time; 892 * struct sample_id sample_id; 893 * }; 894 */ 895 PERF_RECORD_EXIT = 4, 896 897 /* 898 * struct { 899 * struct perf_event_header header; 900 * u64 time; 901 * u64 id; 902 * u64 stream_id; 903 * struct sample_id sample_id; 904 * }; 905 */ 906 PERF_RECORD_THROTTLE = 5, 907 PERF_RECORD_UNTHROTTLE = 6, 908 909 /* 910 * struct { 911 * struct perf_event_header header; 912 * u32 pid, ppid; 913 * u32 tid, ptid; 914 * u64 time; 915 * struct sample_id sample_id; 916 * }; 917 */ 918 PERF_RECORD_FORK = 7, 919 920 /* 921 * struct { 922 * struct perf_event_header header; 923 * u32 pid, tid; 924 * 925 * struct read_format values; 926 * struct sample_id sample_id; 927 * }; 928 */ 929 PERF_RECORD_READ = 8, 930 931 /* 932 * struct { 933 * struct perf_event_header header; 934 * 935 * # 936 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 937 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 938 * # is fixed relative to header. 939 * # 940 * 941 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 942 * { u64 ip; } && PERF_SAMPLE_IP 943 * { u32 pid, tid; } && PERF_SAMPLE_TID 944 * { u64 time; } && PERF_SAMPLE_TIME 945 * { u64 addr; } && PERF_SAMPLE_ADDR 946 * { u64 id; } && PERF_SAMPLE_ID 947 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 948 * { u32 cpu, res; } && PERF_SAMPLE_CPU 949 * { u64 period; } && PERF_SAMPLE_PERIOD 950 * 951 * { struct read_format values; } && PERF_SAMPLE_READ 952 * 953 * { u64 nr, 954 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 955 * 956 * # 957 * # The RAW record below is opaque data wrt the ABI 958 * # 959 * # That is, the ABI doesn't make any promises wrt to 960 * # the stability of its content, it may vary depending 961 * # on event, hardware, kernel version and phase of 962 * # the moon. 963 * # 964 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 965 * # 966 * 967 * { u32 size; 968 * char data[size];}&& PERF_SAMPLE_RAW 969 * 970 * { u64 nr; 971 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 972 * { u64 from, to, flags } lbr[nr]; 973 * } && PERF_SAMPLE_BRANCH_STACK 974 * 975 * { u64 abi; # enum perf_sample_regs_abi 976 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 977 * 978 * { u64 size; 979 * char data[size]; 980 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 981 * 982 * { union perf_sample_weight 983 * { 984 * u64 full; && PERF_SAMPLE_WEIGHT 985 * #if defined(__LITTLE_ENDIAN_BITFIELD) 986 * struct { 987 * u32 var1_dw; 988 * u16 var2_w; 989 * u16 var3_w; 990 * } && PERF_SAMPLE_WEIGHT_STRUCT 991 * #elif defined(__BIG_ENDIAN_BITFIELD) 992 * struct { 993 * u16 var3_w; 994 * u16 var2_w; 995 * u32 var1_dw; 996 * } && PERF_SAMPLE_WEIGHT_STRUCT 997 * #endif 998 * } 999 * } 1000 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 1001 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 1002 * { u64 abi; # enum perf_sample_regs_abi 1003 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 1004 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 1005 * { u64 size; 1006 * char data[size]; } && PERF_SAMPLE_AUX 1007 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1008 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1009 * }; 1010 */ 1011 PERF_RECORD_SAMPLE = 9, 1012 1013 /* 1014 * The MMAP2 records are an augmented version of MMAP, they add 1015 * maj, min, ino numbers to be used to uniquely identify each mapping 1016 * 1017 * struct { 1018 * struct perf_event_header header; 1019 * 1020 * u32 pid, tid; 1021 * u64 addr; 1022 * u64 len; 1023 * u64 pgoff; 1024 * union { 1025 * struct { 1026 * u32 maj; 1027 * u32 min; 1028 * u64 ino; 1029 * u64 ino_generation; 1030 * }; 1031 * struct { 1032 * u8 build_id_size; 1033 * u8 __reserved_1; 1034 * u16 __reserved_2; 1035 * u8 build_id[20]; 1036 * }; 1037 * }; 1038 * u32 prot, flags; 1039 * char filename[]; 1040 * struct sample_id sample_id; 1041 * }; 1042 */ 1043 PERF_RECORD_MMAP2 = 10, 1044 1045 /* 1046 * Records that new data landed in the AUX buffer part. 1047 * 1048 * struct { 1049 * struct perf_event_header header; 1050 * 1051 * u64 aux_offset; 1052 * u64 aux_size; 1053 * u64 flags; 1054 * struct sample_id sample_id; 1055 * }; 1056 */ 1057 PERF_RECORD_AUX = 11, 1058 1059 /* 1060 * Indicates that instruction trace has started 1061 * 1062 * struct { 1063 * struct perf_event_header header; 1064 * u32 pid; 1065 * u32 tid; 1066 * struct sample_id sample_id; 1067 * }; 1068 */ 1069 PERF_RECORD_ITRACE_START = 12, 1070 1071 /* 1072 * Records the dropped/lost sample number. 1073 * 1074 * struct { 1075 * struct perf_event_header header; 1076 * 1077 * u64 lost; 1078 * struct sample_id sample_id; 1079 * }; 1080 */ 1081 PERF_RECORD_LOST_SAMPLES = 13, 1082 1083 /* 1084 * Records a context switch in or out (flagged by 1085 * PERF_RECORD_MISC_SWITCH_OUT). See also 1086 * PERF_RECORD_SWITCH_CPU_WIDE. 1087 * 1088 * struct { 1089 * struct perf_event_header header; 1090 * struct sample_id sample_id; 1091 * }; 1092 */ 1093 PERF_RECORD_SWITCH = 14, 1094 1095 /* 1096 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1097 * next_prev_tid that are the next (switching out) or previous 1098 * (switching in) pid/tid. 1099 * 1100 * struct { 1101 * struct perf_event_header header; 1102 * u32 next_prev_pid; 1103 * u32 next_prev_tid; 1104 * struct sample_id sample_id; 1105 * }; 1106 */ 1107 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1108 1109 /* 1110 * struct { 1111 * struct perf_event_header header; 1112 * u32 pid; 1113 * u32 tid; 1114 * u64 nr_namespaces; 1115 * { u64 dev, inode; } [nr_namespaces]; 1116 * struct sample_id sample_id; 1117 * }; 1118 */ 1119 PERF_RECORD_NAMESPACES = 16, 1120 1121 /* 1122 * Record ksymbol register/unregister events: 1123 * 1124 * struct { 1125 * struct perf_event_header header; 1126 * u64 addr; 1127 * u32 len; 1128 * u16 ksym_type; 1129 * u16 flags; 1130 * char name[]; 1131 * struct sample_id sample_id; 1132 * }; 1133 */ 1134 PERF_RECORD_KSYMBOL = 17, 1135 1136 /* 1137 * Record bpf events: 1138 * enum perf_bpf_event_type { 1139 * PERF_BPF_EVENT_UNKNOWN = 0, 1140 * PERF_BPF_EVENT_PROG_LOAD = 1, 1141 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1142 * }; 1143 * 1144 * struct { 1145 * struct perf_event_header header; 1146 * u16 type; 1147 * u16 flags; 1148 * u32 id; 1149 * u8 tag[BPF_TAG_SIZE]; 1150 * struct sample_id sample_id; 1151 * }; 1152 */ 1153 PERF_RECORD_BPF_EVENT = 18, 1154 1155 /* 1156 * struct { 1157 * struct perf_event_header header; 1158 * u64 id; 1159 * char path[]; 1160 * struct sample_id sample_id; 1161 * }; 1162 */ 1163 PERF_RECORD_CGROUP = 19, 1164 1165 /* 1166 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1167 * the number of old bytes, 'new_len' is the number of new bytes. Either 1168 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1169 * addition or removal of a trampoline. 'bytes' contains the old bytes 1170 * followed immediately by the new bytes. 1171 * 1172 * struct { 1173 * struct perf_event_header header; 1174 * u64 addr; 1175 * u16 old_len; 1176 * u16 new_len; 1177 * u8 bytes[]; 1178 * struct sample_id sample_id; 1179 * }; 1180 */ 1181 PERF_RECORD_TEXT_POKE = 20, 1182 1183 /* 1184 * Data written to the AUX area by hardware due to aux_output, may need 1185 * to be matched to the event by an architecture-specific hardware ID. 1186 * This records the hardware ID, but requires sample_id to provide the 1187 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1188 * records from multiple events. 1189 * 1190 * struct { 1191 * struct perf_event_header header; 1192 * u64 hw_id; 1193 * struct sample_id sample_id; 1194 * }; 1195 */ 1196 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1197 1198 PERF_RECORD_MAX, /* non-ABI */ 1199 }; 1200 1201 enum perf_record_ksymbol_type { 1202 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1203 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1204 /* 1205 * Out of line code such as kprobe-replaced instructions or optimized 1206 * kprobes or ftrace trampolines. 1207 */ 1208 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1209 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1210 }; 1211 1212 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1213 1214 enum perf_bpf_event_type { 1215 PERF_BPF_EVENT_UNKNOWN = 0, 1216 PERF_BPF_EVENT_PROG_LOAD = 1, 1217 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1218 PERF_BPF_EVENT_MAX, /* non-ABI */ 1219 }; 1220 1221 #define PERF_MAX_STACK_DEPTH 127 1222 #define PERF_MAX_CONTEXTS_PER_STACK 8 1223 1224 enum perf_callchain_context { 1225 PERF_CONTEXT_HV = (__u64)-32, 1226 PERF_CONTEXT_KERNEL = (__u64)-128, 1227 PERF_CONTEXT_USER = (__u64)-512, 1228 1229 PERF_CONTEXT_GUEST = (__u64)-2048, 1230 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1231 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1232 1233 PERF_CONTEXT_MAX = (__u64)-4095, 1234 }; 1235 1236 /** 1237 * PERF_RECORD_AUX::flags bits 1238 */ 1239 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1240 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1241 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1242 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1243 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1244 1245 /* CoreSight PMU AUX buffer formats */ 1246 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1247 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1248 1249 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1250 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1251 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1252 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1253 1254 #if defined(__LITTLE_ENDIAN_BITFIELD) 1255 union perf_mem_data_src { 1256 __u64 val; 1257 struct { 1258 __u64 mem_op:5, /* type of opcode */ 1259 mem_lvl:14, /* memory hierarchy level */ 1260 mem_snoop:5, /* snoop mode */ 1261 mem_lock:2, /* lock instr */ 1262 mem_dtlb:7, /* tlb access */ 1263 mem_lvl_num:4, /* memory hierarchy level number */ 1264 mem_remote:1, /* remote */ 1265 mem_snoopx:2, /* snoop mode, ext */ 1266 mem_blk:3, /* access blocked */ 1267 mem_hops:3, /* hop level */ 1268 mem_rsvd:18; 1269 }; 1270 }; 1271 #elif defined(__BIG_ENDIAN_BITFIELD) 1272 union perf_mem_data_src { 1273 __u64 val; 1274 struct { 1275 __u64 mem_rsvd:18, 1276 mem_hops:3, /* hop level */ 1277 mem_blk:3, /* access blocked */ 1278 mem_snoopx:2, /* snoop mode, ext */ 1279 mem_remote:1, /* remote */ 1280 mem_lvl_num:4, /* memory hierarchy level number */ 1281 mem_dtlb:7, /* tlb access */ 1282 mem_lock:2, /* lock instr */ 1283 mem_snoop:5, /* snoop mode */ 1284 mem_lvl:14, /* memory hierarchy level */ 1285 mem_op:5; /* type of opcode */ 1286 }; 1287 }; 1288 #else 1289 #error "Unknown endianness" 1290 #endif 1291 1292 /* type of opcode (load/store/prefetch,code) */ 1293 #define PERF_MEM_OP_NA 0x01 /* not available */ 1294 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1295 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1296 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1297 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1298 #define PERF_MEM_OP_SHIFT 0 1299 1300 /* 1301 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1302 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1303 * Supporting this namespace inorder to not break defined ABIs. 1304 * 1305 * memory hierarchy (memory level, hit or miss) 1306 */ 1307 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1308 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1309 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1310 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1311 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1312 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1313 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1314 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1315 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1316 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1317 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1318 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1319 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1320 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1321 #define PERF_MEM_LVL_SHIFT 5 1322 1323 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1324 #define PERF_MEM_REMOTE_SHIFT 37 1325 1326 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1327 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1328 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1329 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1330 /* 5-0x8 available */ 1331 #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ 1332 #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ 1333 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1334 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1335 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1336 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1337 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1338 1339 #define PERF_MEM_LVLNUM_SHIFT 33 1340 1341 /* snoop mode */ 1342 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1343 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1344 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1345 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1346 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1347 #define PERF_MEM_SNOOP_SHIFT 19 1348 1349 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1350 #define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ 1351 #define PERF_MEM_SNOOPX_SHIFT 38 1352 1353 /* locked instruction */ 1354 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1355 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1356 #define PERF_MEM_LOCK_SHIFT 24 1357 1358 /* TLB access */ 1359 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1360 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1361 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1362 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1363 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1364 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1365 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1366 #define PERF_MEM_TLB_SHIFT 26 1367 1368 /* Access blocked */ 1369 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1370 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1371 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1372 #define PERF_MEM_BLK_SHIFT 40 1373 1374 /* hop level */ 1375 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1376 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1377 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1378 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1379 /* 5-7 available */ 1380 #define PERF_MEM_HOPS_SHIFT 43 1381 1382 #define PERF_MEM_S(a, s) \ 1383 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1384 1385 /* 1386 * single taken branch record layout: 1387 * 1388 * from: source instruction (may not always be a branch insn) 1389 * to: branch target 1390 * mispred: branch target was mispredicted 1391 * predicted: branch target was predicted 1392 * 1393 * support for mispred, predicted is optional. In case it 1394 * is not supported mispred = predicted = 0. 1395 * 1396 * in_tx: running in a hardware transaction 1397 * abort: aborting a hardware transaction 1398 * cycles: cycles from last branch (or 0 if not supported) 1399 * type: branch type 1400 */ 1401 struct perf_branch_entry { 1402 __u64 from; 1403 __u64 to; 1404 __u64 mispred:1, /* target mispredicted */ 1405 predicted:1,/* target predicted */ 1406 in_tx:1, /* in transaction */ 1407 abort:1, /* transaction abort */ 1408 cycles:16, /* cycle count to last branch */ 1409 type:4, /* branch type */ 1410 new_type:4, /* additional branch type */ 1411 priv:3, /* privilege level */ 1412 reserved:33; 1413 }; 1414 1415 union perf_sample_weight { 1416 __u64 full; 1417 #if defined(__LITTLE_ENDIAN_BITFIELD) 1418 struct { 1419 __u32 var1_dw; 1420 __u16 var2_w; 1421 __u16 var3_w; 1422 }; 1423 #elif defined(__BIG_ENDIAN_BITFIELD) 1424 struct { 1425 __u16 var3_w; 1426 __u16 var2_w; 1427 __u32 var1_dw; 1428 }; 1429 #else 1430 #error "Unknown endianness" 1431 #endif 1432 }; 1433 1434 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1435