1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [--no-desc] [--long-desc] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21-d:: 22--desc:: 23Print extra event descriptions. (default) 24 25--no-desc:: 26Don't print descriptions. 27 28-v:: 29--long-desc:: 30Print longer event descriptions. 31 32--debug:: 33Enable debugging output. 34 35--details:: 36Print how named events are resolved internally into perf events, and also 37any extra expressions computed by perf stat. 38 39--deprecated:: 40Print deprecated events. By default the deprecated events are hidden. 41 42[[EVENT_MODIFIERS]] 43EVENT MODIFIERS 44--------------- 45 46Events can optionally have a modifier by appending a colon and one or 47more modifiers. Modifiers allow the user to restrict the events to be 48counted. The following modifiers exist: 49 50 u - user-space counting 51 k - kernel counting 52 h - hypervisor counting 53 I - non idle counting 54 G - guest counting (in KVM guests) 55 H - host counting (not in KVM guests) 56 p - precise level 57 P - use maximum detected precise level 58 S - read sample value (PERF_SAMPLE_READ) 59 D - pin the event to the PMU 60 W - group is weak and will fallback to non-group if not schedulable, 61 62The 'p' modifier can be used for specifying how precise the instruction 63address should be. The 'p' modifier can be specified multiple times: 64 65 0 - SAMPLE_IP can have arbitrary skid 66 1 - SAMPLE_IP must have constant skid 67 2 - SAMPLE_IP requested to have 0 skid 68 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 69 sample shadowing effects. 70 71For Intel systems precise event sampling is implemented with PEBS 72which supports up to precise-level 2, and precise level 3 for 73some special cases 74 75On AMD systems it is implemented using IBS (up to precise-level 2). 76The precise modifier works with event types 0x76 (cpu-cycles, CPU 77clocks not halted) and 0xC1 (micro-ops retired). Both events map to 78IBS execution sampling (IBS op) with the IBS Op Counter Control bit 79(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s 80Manual Volume 2: System Programming, 13.3 Instruction-Based 81Sampling). Examples to use IBS: 82 83 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 84 perf record -a -e r076:p ... # same as -e cpu-cycles:p 85 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 86 87RAW HARDWARE EVENT DESCRIPTOR 88----------------------------- 89Even when an event is not available in a symbolic form within perf right now, 90it can be encoded in a per processor specific way. 91 92For instance For x86 CPUs NNN represents the raw register encoding with the 93layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 94of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 95Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 96 97Note: Only the following bit fields can be set in x86 counter 98registers: event, umask, edge, inv, cmask. Esp. guest/host only and 99OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 100MODIFIERS>>. 101 102Example: 103 104If the Intel docs for a QM720 Core i7 describe an event as: 105 106 Event Umask Event Mask 107 Num. Value Mnemonic Description Comment 108 109 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 110 delivered by loop stream detector invert to count 111 cycles 112 113raw encoding of 0x1A8 can be used: 114 115 perf stat -e r1a8 -a sleep 1 116 perf record -e r1a8 ... 117 118You should refer to the processor specific documentation for getting these 119details. Some of them are referenced in the SEE ALSO section below. 120 121ARBITRARY PMUS 122-------------- 123 124perf also supports an extended syntax for specifying raw parameters 125to PMUs. Using this typically requires looking up the specific event 126in the CPU vendor specific documentation. 127 128The available PMUs and their raw parameters can be listed with 129 130 ls /sys/devices/*/format 131 132For example the raw event "LSD.UOPS" core pmu event above could 133be specified as 134 135 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 136 137 or using extended name syntax 138 139 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 140 141PER SOCKET PMUS 142--------------- 143 144Some PMUs are not associated with a core, but with a whole CPU socket. 145Events on these PMUs generally cannot be sampled, but only counted globally 146with perf stat -a. They can be bound to one logical CPU, but will measure 147all the CPUs in the same socket. 148 149This example measures memory bandwidth every second 150on the first memory controller on socket 0 of a Intel Xeon system 151 152 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 153 154Each memory controller has its own PMU. Measuring the complete system 155bandwidth would require specifying all imc PMUs (see perf list output), 156and adding the values together. To simplify creation of multiple events, 157prefix and glob matching is supported in the PMU name, and the prefix 158'uncore_' is also ignored when performing the match. So the command above 159can be expanded to all memory controllers by using the syntaxes: 160 161 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 162 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 163 164This example measures the combined core power every second 165 166 perf stat -I 1000 -e power/energy-cores/ -a 167 168ACCESS RESTRICTIONS 169------------------- 170 171For non root users generally only context switched PMU events are available. 172This is normally only the events in the cpu PMU, the predefined events 173like cycles and instructions and some software events. 174 175Other PMUs and global measurements are normally root only. 176Some event qualifiers, such as "any", are also root only. 177 178This can be overridden by setting the kernel.perf_event_paranoid 179sysctl to -1, which allows non root to use these events. 180 181For accessing trace point events perf needs to have read access to 182/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed 183setting. 184 185TRACING 186------- 187 188Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 189that allows low overhead execution tracing. These are described in a separate 190intel-pt.txt document. 191 192PARAMETERIZED EVENTS 193-------------------- 194 195Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 196example: 197 198 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 199 200This means that when provided as an event, a value for '?' must 201also be supplied. For example: 202 203 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 204 205EVENT QUALIFIERS: 206 207It is also possible to add extra qualifiers to an event: 208 209percore: 210 211Sums up the event counts for all hardware threads in a core, e.g.: 212 213 214 perf stat -e cpu/event=0,umask=0x3,percore=1/ 215 216 217EVENT GROUPS 218------------ 219 220Perf supports time based multiplexing of events, when the number of events 221active exceeds the number of hardware performance counters. Multiplexing 222can cause measurement errors when the workload changes its execution 223profile. 224 225When metrics are computed using formulas from event counts, it is useful to 226ensure some events are always measured together as a group to minimize multiplexing 227errors. Event groups can be specified using { }. 228 229 perf stat -e '{instructions,cycles}' ... 230 231The number of available performance counters depend on the CPU. A group 232cannot contain more events than available counters. 233For example Intel Core CPUs typically have four generic performance counters 234for the core, plus three fixed counters for instructions, cycles and 235ref-cycles. Some special events have restrictions on which counter they 236can schedule, and may not support multiple instances in a single group. 237When too many events are specified in the group some of them will not 238be measured. 239 240Globally pinned events can limit the number of counters available for 241other groups. On x86 systems, the NMI watchdog pins a counter by default. 242The nmi watchdog can be disabled as root with 243 244 echo 0 > /proc/sys/kernel/nmi_watchdog 245 246Events from multiple different PMUs cannot be mixed in a group, with 247some exceptions for software events. 248 249LEADER SAMPLING 250--------------- 251 252perf also supports group leader sampling using the :S specifier. 253 254 perf record -e '{cycles,instructions}:S' ... 255 perf report --group 256 257Normally all events in an event group sample, but with :S only 258the first event (the leader) samples, and it only reads the values of the 259other events in the group. 260 261OPTIONS 262------- 263 264Without options all known events will be listed. 265 266To limit the list use: 267 268. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 269 270. 'sw' or 'software' to list software events such as context switches, etc. 271 272. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 273 274. 'tracepoint' to list all tracepoint events, alternatively use 275 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 276 block, etc. 277 278. 'pmu' to print the kernel supplied PMU events. 279 280. 'sdt' to list all Statically Defined Tracepoint events. 281 282. 'metric' to list metrics 283 284. 'metricgroup' to list metricgroups with metrics. 285 286. If none of the above is matched, it will apply the supplied glob to all 287 events, printing the ones that match. 288 289. As a last resort, it will do a substring search in all event names. 290 291One or more types can be used at the same time, listing the events for the 292types specified. 293 294Support raw format: 295 296. '--raw-dump', shows the raw-dump of all the events. 297. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 298 a certain kind of events. 299 300SEE ALSO 301-------- 302linkperf:perf-stat[1], linkperf:perf-top[1], 303linkperf:perf-record[1], 304http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 305http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 306