1[
2    {
3        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
4        "Counter": "0,1,2,3,4,5",
5        "EventCode": "0xB7",
6        "EventName": "OCR.COREWB_M.ANY_RESPONSE",
7        "MSRIndex": "0x1a6,0x1a7",
8        "MSRValue": "0x10008",
9        "SampleAfterValue": "100003",
10        "UMask": "0x1",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts demand data reads that have any type of response.",
15        "Counter": "0,1,2,3,4,5",
16        "EventCode": "0xB7",
17        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
18        "MSRIndex": "0x1a6,0x1a7",
19        "MSRValue": "0x10001",
20        "SampleAfterValue": "100003",
21        "UMask": "0x1",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
26        "Counter": "0,1,2,3,4,5",
27        "EventCode": "0xB7",
28        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
29        "MSRIndex": "0x1a6,0x1a7",
30        "MSRValue": "0x10002",
31        "SampleAfterValue": "100003",
32        "UMask": "0x1",
33        "Unit": "cpu_atom"
34    },
35    {
36        "BriefDescription": "Counts streaming stores that have any type of response.",
37        "Counter": "0,1,2,3,4,5",
38        "EventCode": "0xB7",
39        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
40        "MSRIndex": "0x1a6,0x1a7",
41        "MSRValue": "0x10800",
42        "SampleAfterValue": "100003",
43        "UMask": "0x1",
44        "Unit": "cpu_atom"
45    },
46    {
47        "BriefDescription": "ASSISTS.HARDWARE",
48        "CollectPEBSRecord": "2",
49        "Counter": "0,1,2,3,4,5,6,7",
50        "EventCode": "0xc1",
51        "EventName": "ASSISTS.HARDWARE",
52        "PEBScounters": "0,1,2,3,4,5,6,7",
53        "SampleAfterValue": "100003",
54        "Speculative": "1",
55        "UMask": "0x4",
56        "Unit": "cpu_core"
57    },
58    {
59        "BriefDescription": "ASSISTS.PAGE_FAULT",
60        "CollectPEBSRecord": "2",
61        "Counter": "0,1,2,3,4,5,6,7",
62        "EventCode": "0xc1",
63        "EventName": "ASSISTS.PAGE_FAULT",
64        "PEBScounters": "0,1,2,3,4,5,6,7",
65        "SampleAfterValue": "1000003",
66        "Speculative": "1",
67        "UMask": "0x8",
68        "Unit": "cpu_core"
69    },
70    {
71        "BriefDescription": "CORE_POWER.LICENSE_1",
72        "CollectPEBSRecord": "2",
73        "Counter": "0,1,2,3",
74        "EventCode": "0x28",
75        "EventName": "CORE_POWER.LICENSE_1",
76        "PEBScounters": "0,1,2,3",
77        "SampleAfterValue": "200003",
78        "Speculative": "1",
79        "UMask": "0x2",
80        "Unit": "cpu_core"
81    },
82    {
83        "BriefDescription": "CORE_POWER.LICENSE_2",
84        "CollectPEBSRecord": "2",
85        "Counter": "0,1,2,3",
86        "EventCode": "0x28",
87        "EventName": "CORE_POWER.LICENSE_2",
88        "PEBScounters": "0,1,2,3",
89        "SampleAfterValue": "200003",
90        "Speculative": "1",
91        "UMask": "0x4",
92        "Unit": "cpu_core"
93    },
94    {
95        "BriefDescription": "CORE_POWER.LICENSE_3",
96        "CollectPEBSRecord": "2",
97        "Counter": "0,1,2,3",
98        "EventCode": "0x28",
99        "EventName": "CORE_POWER.LICENSE_3",
100        "PEBScounters": "0,1,2,3",
101        "SampleAfterValue": "200003",
102        "Speculative": "1",
103        "UMask": "0x8",
104        "Unit": "cpu_core"
105    },
106    {
107        "BriefDescription": "Counts demand data reads that have any type of response.",
108        "Counter": "0,1,2,3,4,5,6,7",
109        "EventCode": "0x2A,0x2B",
110        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
111        "MSRIndex": "0x1a6,0x1a7",
112        "MSRValue": "0x10001",
113        "SampleAfterValue": "100003",
114        "UMask": "0x1",
115        "Unit": "cpu_core"
116    },
117    {
118        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
119        "Counter": "0,1,2,3,4,5,6,7",
120        "EventCode": "0x2A,0x2B",
121        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
122        "MSRIndex": "0x1a6,0x1a7",
123        "MSRValue": "0x184000001",
124        "SampleAfterValue": "100003",
125        "UMask": "0x1",
126        "Unit": "cpu_core"
127    },
128    {
129        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
130        "Counter": "0,1,2,3,4,5,6,7",
131        "EventCode": "0x2A,0x2B",
132        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
133        "MSRIndex": "0x1a6,0x1a7",
134        "MSRValue": "0x10002",
135        "SampleAfterValue": "100003",
136        "UMask": "0x1",
137        "Unit": "cpu_core"
138    },
139    {
140        "BriefDescription": "Counts streaming stores that have any type of response.",
141        "Counter": "0,1,2,3,4,5,6,7",
142        "EventCode": "0x2A,0x2B",
143        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
144        "MSRIndex": "0x1a6,0x1a7",
145        "MSRValue": "0x10800",
146        "SampleAfterValue": "100003",
147        "UMask": "0x1",
148        "Unit": "cpu_core"
149    },
150    {
151        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
152        "CollectPEBSRecord": "2",
153        "Counter": "0,1,2,3,4,5,6,7",
154        "EventCode": "0xa5",
155        "EventName": "RS.EMPTY",
156        "PEBScounters": "0,1,2,3,4,5,6,7",
157        "SampleAfterValue": "1000003",
158        "Speculative": "1",
159        "UMask": "0x7",
160        "Unit": "cpu_core"
161    },
162    {
163        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
164        "CollectPEBSRecord": "2",
165        "Counter": "0,1,2,3,4,5,6,7",
166        "CounterMask": "1",
167        "EdgeDetect": "1",
168        "EventCode": "0xa5",
169        "EventName": "RS.EMPTY_COUNT",
170        "Invert": "1",
171        "PEBScounters": "0,1,2,3,4,5,6,7",
172        "SampleAfterValue": "100003",
173        "Speculative": "1",
174        "UMask": "0x7",
175        "Unit": "cpu_core"
176    },
177    {
178        "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
179        "CollectPEBSRecord": "2",
180        "Counter": "0,1,2,3,4,5,6,7",
181        "CounterMask": "1",
182        "EdgeDetect": "1",
183        "EventCode": "0xa5",
184        "EventName": "RS_EMPTY.COUNT",
185        "Invert": "1",
186        "PEBScounters": "0,1,2,3,4,5,6,7",
187        "SampleAfterValue": "100003",
188        "Speculative": "1",
189        "UMask": "0x7",
190        "Unit": "cpu_core"
191    },
192    {
193        "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
194        "CollectPEBSRecord": "2",
195        "Counter": "0,1,2,3,4,5,6,7",
196        "EventCode": "0xa5",
197        "EventName": "RS_EMPTY.CYCLES",
198        "PEBScounters": "0,1,2,3,4,5,6,7",
199        "SampleAfterValue": "1000003",
200        "Speculative": "1",
201        "UMask": "0x7",
202        "Unit": "cpu_core"
203    },
204    {
205        "BriefDescription": "XQ.FULL_CYCLES",
206        "CollectPEBSRecord": "2",
207        "Counter": "0,1,2,3",
208        "CounterMask": "1",
209        "EventCode": "0x2d",
210        "EventName": "XQ.FULL_CYCLES",
211        "PEBScounters": "0,1,2,3",
212        "SampleAfterValue": "1000003",
213        "Speculative": "1",
214        "UMask": "0x1",
215        "Unit": "cpu_core"
216    }
217]
218