1[ 2 { 3 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.WR", 7 "PerPkg": "1", 8 "UMask": "0x2", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x4", 15 "EventName": "UNC_M_CAS_COUNT.RD_REG", 16 "PerPkg": "1", 17 "UMask": "0x1", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Underfill Read CAS Commands issued", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x4", 24 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 25 "PerPkg": "1", 26 "UMask": "0x2", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x4", 33 "EventName": "UNC_M_CAS_COUNT.RD", 34 "PerPkg": "1", 35 "UMask": "0x3", 36 "Unit": "iMC" 37 }, 38 { 39 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 40 "Counter": "0,1,2,3", 41 "EventCode": "0x4", 42 "EventName": "LLC_MISSES.MEM_READ", 43 "PerPkg": "1", 44 "ScaleUnit": "64Bytes", 45 "UMask": "0x3", 46 "Unit": "iMC" 47 }, 48 { 49 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 50 "Counter": "0,1,2,3", 51 "EventCode": "0x4", 52 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 53 "PerPkg": "1", 54 "UMask": "0x4", 55 "Unit": "iMC" 56 }, 57 { 58 "BriefDescription": "All DRAM Write CAS commands issued", 59 "Counter": "0,1,2,3", 60 "EventCode": "0x4", 61 "EventName": "UNC_M_CAS_COUNT.WR", 62 "PerPkg": "1", 63 "UMask": "0xC", 64 "Unit": "iMC" 65 }, 66 { 67 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 68 "Counter": "0,1,2,3", 69 "EventCode": "0x4", 70 "EventName": "LLC_MISSES.MEM_WRITE", 71 "PerPkg": "1", 72 "ScaleUnit": "64Bytes", 73 "UMask": "0xC", 74 "Unit": "iMC" 75 }, 76 { 77 "BriefDescription": "All DRAM CAS Commands issued", 78 "Counter": "0,1,2,3", 79 "EventCode": "0x4", 80 "EventName": "UNC_M_CAS_COUNT.ALL", 81 "PerPkg": "1", 82 "UMask": "0xF", 83 "Unit": "iMC" 84 }, 85 { 86 "BriefDescription": "Memory controller clock ticks", 87 "Counter": "0,1,2,3", 88 "EventName": "UNC_M_CLOCKTICKS", 89 "PerPkg": "1", 90 "Unit": "iMC" 91 }, 92 { 93 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37", 94 "Counter": "0,1,2,3", 95 "EventCode": "0x85", 96 "EventName": "UNC_M_POWER_CHANNEL_PPD", 97 "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", 98 "MetricName": "power_channel_ppd %", 99 "PerPkg": "1", 100 "Unit": "iMC" 101 }, 102 { 103 "BriefDescription": "Cycles Memory is in self refresh power mode", 104 "Counter": "0,1,2,3", 105 "EventCode": "0x43", 106 "EventName": "UNC_M_POWER_SELF_REFRESH", 107 "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", 108 "MetricName": "power_self_refresh %", 109 "PerPkg": "1", 110 "Unit": "iMC" 111 }, 112 { 113 "BriefDescription": "Pre-charges due to page misses", 114 "Counter": "0,1,2,3", 115 "EventCode": "0x2", 116 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 117 "PerPkg": "1", 118 "UMask": "0x1", 119 "Unit": "iMC" 120 }, 121 { 122 "BriefDescription": "Pre-charge for reads", 123 "Counter": "0,1,2,3", 124 "EventCode": "0x2", 125 "EventName": "UNC_M_PRE_COUNT.RD", 126 "PerPkg": "1", 127 "UMask": "0x4", 128 "Unit": "iMC" 129 }, 130 { 131 "BriefDescription": "Read Pending Queue Allocations", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x10", 134 "EventName": "UNC_M_RPQ_INSERTS", 135 "PerPkg": "1", 136 "Unit": "iMC" 137 }, 138 { 139 "BriefDescription": "Read Pending Queue Occupancy", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x80", 142 "EventName": "UNC_M_RPQ_OCCUPANCY", 143 "PerPkg": "1", 144 "Unit": "iMC" 145 }, 146 { 147 "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", 148 "Counter": "0,1,2,3", 149 "EventCode": "0xD3", 150 "EventName": "UNC_M_TAGCHK.HIT", 151 "PerPkg": "1", 152 "UMask": "0x1", 153 "Unit": "iMC" 154 }, 155 { 156 "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", 157 "Counter": "0,1,2,3", 158 "EventCode": "0xD3", 159 "EventName": "UNC_M_TAGCHK.MISS_CLEAN", 160 "PerPkg": "1", 161 "UMask": "0x2", 162 "Unit": "iMC" 163 }, 164 { 165 "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", 166 "Counter": "0,1,2,3", 167 "EventCode": "0xD3", 168 "EventName": "UNC_M_TAGCHK.MISS_DIRTY", 169 "PerPkg": "1", 170 "UMask": "0x4", 171 "Unit": "iMC" 172 }, 173 { 174 "BriefDescription": "Write Pending Queue Allocations", 175 "Counter": "0,1,2,3", 176 "EventCode": "0x20", 177 "EventName": "UNC_M_WPQ_INSERTS", 178 "PerPkg": "1", 179 "Unit": "iMC" 180 }, 181 { 182 "BriefDescription": "Write Pending Queue Occupancy", 183 "Counter": "0,1,2,3", 184 "EventCode": "0x81", 185 "EventName": "UNC_M_WPQ_OCCUPANCY", 186 "PerPkg": "1", 187 "Unit": "iMC" 188 }, 189 { 190 "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", 191 "Counter": "0,1,2,3", 192 "EventCode": "0xE0", 193 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", 194 "PerPkg": "1", 195 "UMask": "0x1", 196 "Unit": "iMC" 197 }, 198 { 199 "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all", 200 "Counter": "0,1,2,3", 201 "EventCode": "0xE0", 202 "EventName": "UNC_M_PMM_READ_LATENCY", 203 "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS", 204 "MetricName": "UNC_M_PMM_READ_LATENCY", 205 "PerPkg": "1", 206 "ScaleUnit": "6000000000ns", 207 "UMask": "0x1", 208 "Unit": "iMC" 209 }, 210 { 211 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", 212 "Counter": "0,1,2,3", 213 "EventCode": "0xE3", 214 "EventName": "UNC_M_PMM_RPQ_INSERTS", 215 "PerPkg": "1", 216 "Unit": "iMC" 217 }, 218 { 219 "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xE3", 222 "EventName": "UNC_M_PMM_BANDWIDTH.READ", 223 "PerPkg": "1", 224 "ScaleUnit": "6.103515625E-5MB/sec", 225 "Unit": "iMC" 226 }, 227 { 228 "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts", 229 "Counter": "0,1,2,3", 230 "EventCode": "0xE3", 231 "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL", 232 "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS", 233 "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL", 234 "PerPkg": "1", 235 "ScaleUnit": "6.103515625E-5MB/sec", 236 "Unit": "iMC" 237 }, 238 { 239 "BriefDescription": "All commands for Intel Optane DC persistent memory", 240 "Counter": "0,1,2,3", 241 "EventCode": "0xEA", 242 "EventName": "UNC_M_PMM_CMD1.ALL", 243 "PerPkg": "1", 244 "UMask": "0x1", 245 "Unit": "iMC" 246 }, 247 { 248 "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", 249 "Counter": "0,1,2,3", 250 "EventCode": "0xEA", 251 "EventName": "UNC_M_PMM_CMD1.RD", 252 "PerPkg": "1", 253 "UMask": "0x2", 254 "Unit": "iMC" 255 }, 256 { 257 "BriefDescription": "Write commands for Intel Optane DC persistent memory", 258 "Counter": "0,1,2,3", 259 "EventCode": "0xEA", 260 "EventName": "UNC_M_PMM_CMD1.WR", 261 "PerPkg": "1", 262 "UMask": "0x4", 263 "Unit": "iMC" 264 }, 265 { 266 "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", 267 "Counter": "0,1,2,3", 268 "EventCode": "0xEA", 269 "EventName": "UNC_M_PMM_CMD1.UFILL_RD", 270 "PerPkg": "1", 271 "UMask": "0x8", 272 "Unit": "iMC" 273 }, 274 { 275 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xE7", 278 "EventName": "UNC_M_PMM_WPQ_INSERTS", 279 "PerPkg": "1", 280 "Unit": "iMC" 281 }, 282 { 283 "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts", 284 "Counter": "0,1,2,3", 285 "EventCode": "0xE7", 286 "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", 287 "PerPkg": "1", 288 "ScaleUnit": "6.103515625E-5MB/sec", 289 "Unit": "iMC" 290 }, 291 { 292 "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", 293 "Counter": "0,1,2,3", 294 "EventCode": "0xE4", 295 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", 296 "PerPkg": "1", 297 "UMask": "0x1", 298 "Unit": "iMC" 299 }, 300 { 301 "BriefDescription": "DRAM Activate Count; Activate due to Read", 302 "Counter": "0,1,2,3", 303 "EventCode": "0x1", 304 "EventName": "UNC_M_ACT_COUNT.RD", 305 "PerPkg": "1", 306 "UMask": "0x1", 307 "Unit": "iMC" 308 }, 309 { 310 "BriefDescription": "DRAM Activate Count; Activate due to Bypass", 311 "Counter": "0,1,2,3", 312 "EventCode": "0x1", 313 "EventName": "UNC_M_ACT_COUNT.BYP", 314 "PerPkg": "1", 315 "UMask": "0x8", 316 "Unit": "iMC" 317 }, 318 { 319 "BriefDescription": "ACT command issued by 2 cycle bypass", 320 "Counter": "0,1,2,3", 321 "EventCode": "0xA1", 322 "EventName": "UNC_M_BYP_CMDS.ACT", 323 "PerPkg": "1", 324 "UMask": "0x1", 325 "Unit": "iMC" 326 }, 327 { 328 "BriefDescription": "CAS command issued by 2 cycle bypass", 329 "Counter": "0,1,2,3", 330 "EventCode": "0xA1", 331 "EventName": "UNC_M_BYP_CMDS.CAS", 332 "PerPkg": "1", 333 "UMask": "0x2", 334 "Unit": "iMC" 335 }, 336 { 337 "BriefDescription": "PRE command issued by 2 cycle bypass", 338 "Counter": "0,1,2,3", 339 "EventCode": "0xA1", 340 "EventName": "UNC_M_BYP_CMDS.PRE", 341 "PerPkg": "1", 342 "UMask": "0x4", 343 "Unit": "iMC" 344 }, 345 { 346 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 347 "Counter": "0,1,2,3", 348 "EventCode": "0x4", 349 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 350 "PerPkg": "1", 351 "UMask": "0x8", 352 "Unit": "iMC" 353 }, 354 { 355 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x4", 358 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 359 "PerPkg": "1", 360 "UMask": "0x10", 361 "Unit": "iMC" 362 }, 363 { 364 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", 365 "Counter": "0,1,2,3", 366 "EventCode": "0x4", 367 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 368 "PerPkg": "1", 369 "UMask": "0x20", 370 "Unit": "iMC" 371 }, 372 { 373 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", 374 "Counter": "0,1,2,3", 375 "EventCode": "0x4", 376 "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", 377 "PerPkg": "1", 378 "UMask": "0x40", 379 "Unit": "iMC" 380 }, 381 { 382 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", 383 "Counter": "0,1,2,3", 384 "EventCode": "0x4", 385 "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", 386 "PerPkg": "1", 387 "UMask": "0x80", 388 "Unit": "iMC" 389 }, 390 { 391 "BriefDescription": "DRAM Precharge All Commands", 392 "Counter": "0,1,2,3", 393 "EventCode": "0x6", 394 "EventName": "UNC_M_DRAM_PRE_ALL", 395 "PerPkg": "1", 396 "Unit": "iMC" 397 }, 398 { 399 "BriefDescription": "ECC Correctable Errors", 400 "Counter": "0,1,2,3", 401 "EventCode": "0x9", 402 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 403 "PerPkg": "1", 404 "Unit": "iMC" 405 }, 406 { 407 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 408 "Counter": "0,1,2,3", 409 "EventCode": "0x7", 410 "EventName": "UNC_M_MAJOR_MODES.READ", 411 "PerPkg": "1", 412 "UMask": "0x1", 413 "Unit": "iMC" 414 }, 415 { 416 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 417 "Counter": "0,1,2,3", 418 "EventCode": "0x7", 419 "EventName": "UNC_M_MAJOR_MODES.WRITE", 420 "PerPkg": "1", 421 "UMask": "0x2", 422 "Unit": "iMC" 423 }, 424 { 425 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 426 "Counter": "0,1,2,3", 427 "EventCode": "0x7", 428 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 429 "PerPkg": "1", 430 "UMask": "0x4", 431 "Unit": "iMC" 432 }, 433 { 434 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 435 "Counter": "0,1,2,3", 436 "EventCode": "0x7", 437 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 438 "PerPkg": "1", 439 "UMask": "0x8", 440 "Unit": "iMC" 441 }, 442 { 443 "BriefDescription": "Channel DLLOFF Cycles", 444 "Counter": "0,1,2,3", 445 "EventCode": "0x84", 446 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 447 "PerPkg": "1", 448 "Unit": "iMC" 449 }, 450 { 451 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x83", 454 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 455 "PerPkg": "1", 456 "UMask": "0x1", 457 "Unit": "iMC" 458 }, 459 { 460 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 461 "Counter": "0,1,2,3", 462 "EventCode": "0x83", 463 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 464 "PerPkg": "1", 465 "UMask": "0x2", 466 "Unit": "iMC" 467 }, 468 { 469 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 470 "Counter": "0,1,2,3", 471 "EventCode": "0x83", 472 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 473 "PerPkg": "1", 474 "UMask": "0x4", 475 "Unit": "iMC" 476 }, 477 { 478 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 479 "Counter": "0,1,2,3", 480 "EventCode": "0x83", 481 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 482 "PerPkg": "1", 483 "UMask": "0x8", 484 "Unit": "iMC" 485 }, 486 { 487 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 488 "Counter": "0,1,2,3", 489 "EventCode": "0x83", 490 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 491 "PerPkg": "1", 492 "UMask": "0x10", 493 "Unit": "iMC" 494 }, 495 { 496 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 497 "Counter": "0,1,2,3", 498 "EventCode": "0x83", 499 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 500 "PerPkg": "1", 501 "UMask": "0x20", 502 "Unit": "iMC" 503 }, 504 { 505 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 506 "Counter": "0,1,2,3", 507 "EventCode": "0x83", 508 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 509 "PerPkg": "1", 510 "UMask": "0x40", 511 "Unit": "iMC" 512 }, 513 { 514 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 515 "Counter": "0,1,2,3", 516 "EventCode": "0x83", 517 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 518 "PerPkg": "1", 519 "UMask": "0x80", 520 "Unit": "iMC" 521 }, 522 { 523 "BriefDescription": "Critical Throttle Cycles", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x86", 526 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 527 "PerPkg": "1", 528 "Unit": "iMC" 529 }, 530 { 531 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x42", 534 "EventName": "UNC_M_POWER_PCU_THROTTLING", 535 "PerPkg": "1", 536 "Unit": "iMC" 537 }, 538 { 539 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x41", 542 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 543 "PerPkg": "1", 544 "UMask": "0x1", 545 "Unit": "iMC" 546 }, 547 { 548 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 549 "Counter": "0,1,2,3", 550 "EventCode": "0x41", 551 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 552 "PerPkg": "1", 553 "UMask": "0x2", 554 "Unit": "iMC" 555 }, 556 { 557 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 558 "Counter": "0,1,2,3", 559 "EventCode": "0x41", 560 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 561 "PerPkg": "1", 562 "UMask": "0x4", 563 "Unit": "iMC" 564 }, 565 { 566 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 567 "Counter": "0,1,2,3", 568 "EventCode": "0x41", 569 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 570 "PerPkg": "1", 571 "UMask": "0x8", 572 "Unit": "iMC" 573 }, 574 { 575 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 576 "Counter": "0,1,2,3", 577 "EventCode": "0x41", 578 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 579 "PerPkg": "1", 580 "UMask": "0x10", 581 "Unit": "iMC" 582 }, 583 { 584 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 585 "Counter": "0,1,2,3", 586 "EventCode": "0x41", 587 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 588 "PerPkg": "1", 589 "UMask": "0x20", 590 "Unit": "iMC" 591 }, 592 { 593 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 594 "Counter": "0,1,2,3", 595 "EventCode": "0x41", 596 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 597 "PerPkg": "1", 598 "UMask": "0x40", 599 "Unit": "iMC" 600 }, 601 { 602 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 603 "Counter": "0,1,2,3", 604 "EventCode": "0x41", 605 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 606 "PerPkg": "1", 607 "UMask": "0x80", 608 "Unit": "iMC" 609 }, 610 { 611 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 612 "Counter": "0,1,2,3", 613 "EventCode": "0x8", 614 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 615 "PerPkg": "1", 616 "UMask": "0x1", 617 "Unit": "iMC" 618 }, 619 { 620 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 621 "Counter": "0,1,2,3", 622 "EventCode": "0x8", 623 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 624 "PerPkg": "1", 625 "UMask": "0x2", 626 "Unit": "iMC" 627 }, 628 { 629 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 630 "Counter": "0,1,2,3", 631 "EventCode": "0x2", 632 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 633 "PerPkg": "1", 634 "UMask": "0x2", 635 "Unit": "iMC" 636 }, 637 { 638 "BriefDescription": "Pre-charge for writes", 639 "Counter": "0,1,2,3", 640 "EventCode": "0x2", 641 "EventName": "UNC_M_PRE_COUNT.WR", 642 "PerPkg": "1", 643 "UMask": "0x8", 644 "Unit": "iMC" 645 }, 646 { 647 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 648 "Counter": "0,1,2,3", 649 "EventCode": "0x2", 650 "EventName": "UNC_M_PRE_COUNT.BYP", 651 "PerPkg": "1", 652 "UMask": "0x10", 653 "Unit": "iMC" 654 }, 655 { 656 "BriefDescription": "Read CAS issued with LOW priority", 657 "Counter": "0,1,2,3", 658 "EventCode": "0xA0", 659 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 660 "PerPkg": "1", 661 "UMask": "0x1", 662 "Unit": "iMC" 663 }, 664 { 665 "BriefDescription": "Read CAS issued with MEDIUM priority", 666 "Counter": "0,1,2,3", 667 "EventCode": "0xA0", 668 "EventName": "UNC_M_RD_CAS_PRIO.MED", 669 "PerPkg": "1", 670 "UMask": "0x2", 671 "Unit": "iMC" 672 }, 673 { 674 "BriefDescription": "Read CAS issued with HIGH priority", 675 "Counter": "0,1,2,3", 676 "EventCode": "0xA0", 677 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 678 "PerPkg": "1", 679 "UMask": "0x4", 680 "Unit": "iMC" 681 }, 682 { 683 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 684 "Counter": "0,1,2,3", 685 "EventCode": "0xA0", 686 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 687 "PerPkg": "1", 688 "UMask": "0x8", 689 "Unit": "iMC" 690 }, 691 { 692 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 693 "Counter": "0,1,2,3", 694 "EventCode": "0xB0", 695 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 696 "PerPkg": "1", 697 "Unit": "iMC" 698 }, 699 { 700 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 701 "Counter": "0,1,2,3", 702 "EventCode": "0xB0", 703 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 704 "PerPkg": "1", 705 "UMask": "0x1", 706 "Unit": "iMC" 707 }, 708 { 709 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 710 "Counter": "0,1,2,3", 711 "EventCode": "0xB0", 712 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 713 "PerPkg": "1", 714 "UMask": "0x2", 715 "Unit": "iMC" 716 }, 717 { 718 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 719 "Counter": "0,1,2,3", 720 "EventCode": "0xB0", 721 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 722 "PerPkg": "1", 723 "UMask": "0x3", 724 "Unit": "iMC" 725 }, 726 { 727 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 728 "Counter": "0,1,2,3", 729 "EventCode": "0xB0", 730 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 731 "PerPkg": "1", 732 "UMask": "0x4", 733 "Unit": "iMC" 734 }, 735 { 736 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 737 "Counter": "0,1,2,3", 738 "EventCode": "0xB0", 739 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 740 "PerPkg": "1", 741 "UMask": "0x5", 742 "Unit": "iMC" 743 }, 744 { 745 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 746 "Counter": "0,1,2,3", 747 "EventCode": "0xB0", 748 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 749 "PerPkg": "1", 750 "UMask": "0x6", 751 "Unit": "iMC" 752 }, 753 { 754 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 755 "Counter": "0,1,2,3", 756 "EventCode": "0xB0", 757 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 758 "PerPkg": "1", 759 "UMask": "0x7", 760 "Unit": "iMC" 761 }, 762 { 763 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 764 "Counter": "0,1,2,3", 765 "EventCode": "0xB0", 766 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 767 "PerPkg": "1", 768 "UMask": "0x8", 769 "Unit": "iMC" 770 }, 771 { 772 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 773 "Counter": "0,1,2,3", 774 "EventCode": "0xB0", 775 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 776 "PerPkg": "1", 777 "UMask": "0x9", 778 "Unit": "iMC" 779 }, 780 { 781 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 782 "Counter": "0,1,2,3", 783 "EventCode": "0xB0", 784 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 785 "PerPkg": "1", 786 "UMask": "0xA", 787 "Unit": "iMC" 788 }, 789 { 790 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 791 "Counter": "0,1,2,3", 792 "EventCode": "0xB0", 793 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 794 "PerPkg": "1", 795 "UMask": "0xB", 796 "Unit": "iMC" 797 }, 798 { 799 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 800 "Counter": "0,1,2,3", 801 "EventCode": "0xB0", 802 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 803 "PerPkg": "1", 804 "UMask": "0xC", 805 "Unit": "iMC" 806 }, 807 { 808 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 809 "Counter": "0,1,2,3", 810 "EventCode": "0xB0", 811 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 812 "PerPkg": "1", 813 "UMask": "0xD", 814 "Unit": "iMC" 815 }, 816 { 817 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 818 "Counter": "0,1,2,3", 819 "EventCode": "0xB0", 820 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 821 "PerPkg": "1", 822 "UMask": "0xE", 823 "Unit": "iMC" 824 }, 825 { 826 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 827 "Counter": "0,1,2,3", 828 "EventCode": "0xB0", 829 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 830 "PerPkg": "1", 831 "UMask": "0xF", 832 "Unit": "iMC" 833 }, 834 { 835 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 836 "Counter": "0,1,2,3", 837 "EventCode": "0xB0", 838 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 839 "PerPkg": "1", 840 "UMask": "0x10", 841 "Unit": "iMC" 842 }, 843 { 844 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 845 "Counter": "0,1,2,3", 846 "EventCode": "0xB0", 847 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 848 "PerPkg": "1", 849 "UMask": "0x11", 850 "Unit": "iMC" 851 }, 852 { 853 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 854 "Counter": "0,1,2,3", 855 "EventCode": "0xB0", 856 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 857 "PerPkg": "1", 858 "UMask": "0x12", 859 "Unit": "iMC" 860 }, 861 { 862 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 863 "Counter": "0,1,2,3", 864 "EventCode": "0xB0", 865 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 866 "PerPkg": "1", 867 "UMask": "0x13", 868 "Unit": "iMC" 869 }, 870 { 871 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 872 "Counter": "0,1,2,3", 873 "EventCode": "0xB0", 874 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 875 "PerPkg": "1", 876 "UMask": "0x14", 877 "Unit": "iMC" 878 }, 879 { 880 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 881 "Counter": "0,1,2,3", 882 "EventCode": "0xB1", 883 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 884 "PerPkg": "1", 885 "Unit": "iMC" 886 }, 887 { 888 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 889 "Counter": "0,1,2,3", 890 "EventCode": "0xB1", 891 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 892 "PerPkg": "1", 893 "UMask": "0x1", 894 "Unit": "iMC" 895 }, 896 { 897 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 898 "Counter": "0,1,2,3", 899 "EventCode": "0xB1", 900 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 901 "PerPkg": "1", 902 "UMask": "0x2", 903 "Unit": "iMC" 904 }, 905 { 906 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 907 "Counter": "0,1,2,3", 908 "EventCode": "0xB1", 909 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 910 "PerPkg": "1", 911 "UMask": "0x3", 912 "Unit": "iMC" 913 }, 914 { 915 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 916 "Counter": "0,1,2,3", 917 "EventCode": "0xB1", 918 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 919 "PerPkg": "1", 920 "UMask": "0x4", 921 "Unit": "iMC" 922 }, 923 { 924 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 925 "Counter": "0,1,2,3", 926 "EventCode": "0xB1", 927 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 928 "PerPkg": "1", 929 "UMask": "0x5", 930 "Unit": "iMC" 931 }, 932 { 933 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 934 "Counter": "0,1,2,3", 935 "EventCode": "0xB1", 936 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 937 "PerPkg": "1", 938 "UMask": "0x6", 939 "Unit": "iMC" 940 }, 941 { 942 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 943 "Counter": "0,1,2,3", 944 "EventCode": "0xB1", 945 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 946 "PerPkg": "1", 947 "UMask": "0x7", 948 "Unit": "iMC" 949 }, 950 { 951 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 952 "Counter": "0,1,2,3", 953 "EventCode": "0xB1", 954 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 955 "PerPkg": "1", 956 "UMask": "0x8", 957 "Unit": "iMC" 958 }, 959 { 960 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 961 "Counter": "0,1,2,3", 962 "EventCode": "0xB1", 963 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 964 "PerPkg": "1", 965 "UMask": "0x9", 966 "Unit": "iMC" 967 }, 968 { 969 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 970 "Counter": "0,1,2,3", 971 "EventCode": "0xB1", 972 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 973 "PerPkg": "1", 974 "UMask": "0xA", 975 "Unit": "iMC" 976 }, 977 { 978 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 979 "Counter": "0,1,2,3", 980 "EventCode": "0xB1", 981 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 982 "PerPkg": "1", 983 "UMask": "0xB", 984 "Unit": "iMC" 985 }, 986 { 987 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 988 "Counter": "0,1,2,3", 989 "EventCode": "0xB1", 990 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 991 "PerPkg": "1", 992 "UMask": "0xC", 993 "Unit": "iMC" 994 }, 995 { 996 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 997 "Counter": "0,1,2,3", 998 "EventCode": "0xB1", 999 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 1000 "PerPkg": "1", 1001 "UMask": "0xD", 1002 "Unit": "iMC" 1003 }, 1004 { 1005 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 1006 "Counter": "0,1,2,3", 1007 "EventCode": "0xB1", 1008 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 1009 "PerPkg": "1", 1010 "UMask": "0xE", 1011 "Unit": "iMC" 1012 }, 1013 { 1014 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 1015 "Counter": "0,1,2,3", 1016 "EventCode": "0xB1", 1017 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 1018 "PerPkg": "1", 1019 "UMask": "0xF", 1020 "Unit": "iMC" 1021 }, 1022 { 1023 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 1024 "Counter": "0,1,2,3", 1025 "EventCode": "0xB1", 1026 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 1027 "PerPkg": "1", 1028 "UMask": "0x10", 1029 "Unit": "iMC" 1030 }, 1031 { 1032 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 1033 "Counter": "0,1,2,3", 1034 "EventCode": "0xB1", 1035 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 1036 "PerPkg": "1", 1037 "UMask": "0x11", 1038 "Unit": "iMC" 1039 }, 1040 { 1041 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 1042 "Counter": "0,1,2,3", 1043 "EventCode": "0xB1", 1044 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 1045 "PerPkg": "1", 1046 "UMask": "0x12", 1047 "Unit": "iMC" 1048 }, 1049 { 1050 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 1051 "Counter": "0,1,2,3", 1052 "EventCode": "0xB1", 1053 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 1054 "PerPkg": "1", 1055 "UMask": "0x13", 1056 "Unit": "iMC" 1057 }, 1058 { 1059 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 1060 "Counter": "0,1,2,3", 1061 "EventCode": "0xB1", 1062 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 1063 "PerPkg": "1", 1064 "UMask": "0x14", 1065 "Unit": "iMC" 1066 }, 1067 { 1068 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 1069 "Counter": "0,1,2,3", 1070 "EventCode": "0xB2", 1071 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 1072 "PerPkg": "1", 1073 "Unit": "iMC" 1074 }, 1075 { 1076 "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", 1077 "Counter": "0,1,2,3", 1078 "EventCode": "0xB2", 1079 "EventName": "UNC_M_RD_CAS_RANK2.BANK1", 1080 "PerPkg": "1", 1081 "UMask": "0x1", 1082 "Unit": "iMC" 1083 }, 1084 { 1085 "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", 1086 "Counter": "0,1,2,3", 1087 "EventCode": "0xB2", 1088 "EventName": "UNC_M_RD_CAS_RANK2.BANK2", 1089 "PerPkg": "1", 1090 "UMask": "0x2", 1091 "Unit": "iMC" 1092 }, 1093 { 1094 "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", 1095 "Counter": "0,1,2,3", 1096 "EventCode": "0xB2", 1097 "EventName": "UNC_M_RD_CAS_RANK2.BANK3", 1098 "PerPkg": "1", 1099 "UMask": "0x3", 1100 "Unit": "iMC" 1101 }, 1102 { 1103 "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", 1104 "Counter": "0,1,2,3", 1105 "EventCode": "0xB2", 1106 "EventName": "UNC_M_RD_CAS_RANK2.BANK4", 1107 "PerPkg": "1", 1108 "UMask": "0x4", 1109 "Unit": "iMC" 1110 }, 1111 { 1112 "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", 1113 "Counter": "0,1,2,3", 1114 "EventCode": "0xB2", 1115 "EventName": "UNC_M_RD_CAS_RANK2.BANK5", 1116 "PerPkg": "1", 1117 "UMask": "0x5", 1118 "Unit": "iMC" 1119 }, 1120 { 1121 "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", 1122 "Counter": "0,1,2,3", 1123 "EventCode": "0xB2", 1124 "EventName": "UNC_M_RD_CAS_RANK2.BANK6", 1125 "PerPkg": "1", 1126 "UMask": "0x6", 1127 "Unit": "iMC" 1128 }, 1129 { 1130 "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", 1131 "Counter": "0,1,2,3", 1132 "EventCode": "0xB2", 1133 "EventName": "UNC_M_RD_CAS_RANK2.BANK7", 1134 "PerPkg": "1", 1135 "UMask": "0x7", 1136 "Unit": "iMC" 1137 }, 1138 { 1139 "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", 1140 "Counter": "0,1,2,3", 1141 "EventCode": "0xB2", 1142 "EventName": "UNC_M_RD_CAS_RANK2.BANK8", 1143 "PerPkg": "1", 1144 "UMask": "0x8", 1145 "Unit": "iMC" 1146 }, 1147 { 1148 "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", 1149 "Counter": "0,1,2,3", 1150 "EventCode": "0xB2", 1151 "EventName": "UNC_M_RD_CAS_RANK2.BANK9", 1152 "PerPkg": "1", 1153 "UMask": "0x9", 1154 "Unit": "iMC" 1155 }, 1156 { 1157 "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", 1158 "Counter": "0,1,2,3", 1159 "EventCode": "0xB2", 1160 "EventName": "UNC_M_RD_CAS_RANK2.BANK10", 1161 "PerPkg": "1", 1162 "UMask": "0xA", 1163 "Unit": "iMC" 1164 }, 1165 { 1166 "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", 1167 "Counter": "0,1,2,3", 1168 "EventCode": "0xB2", 1169 "EventName": "UNC_M_RD_CAS_RANK2.BANK11", 1170 "PerPkg": "1", 1171 "UMask": "0xB", 1172 "Unit": "iMC" 1173 }, 1174 { 1175 "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", 1176 "Counter": "0,1,2,3", 1177 "EventCode": "0xB2", 1178 "EventName": "UNC_M_RD_CAS_RANK2.BANK12", 1179 "PerPkg": "1", 1180 "UMask": "0xC", 1181 "Unit": "iMC" 1182 }, 1183 { 1184 "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", 1185 "Counter": "0,1,2,3", 1186 "EventCode": "0xB2", 1187 "EventName": "UNC_M_RD_CAS_RANK2.BANK13", 1188 "PerPkg": "1", 1189 "UMask": "0xD", 1190 "Unit": "iMC" 1191 }, 1192 { 1193 "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", 1194 "Counter": "0,1,2,3", 1195 "EventCode": "0xB2", 1196 "EventName": "UNC_M_RD_CAS_RANK2.BANK14", 1197 "PerPkg": "1", 1198 "UMask": "0xE", 1199 "Unit": "iMC" 1200 }, 1201 { 1202 "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", 1203 "Counter": "0,1,2,3", 1204 "EventCode": "0xB2", 1205 "EventName": "UNC_M_RD_CAS_RANK2.BANK15", 1206 "PerPkg": "1", 1207 "UMask": "0xF", 1208 "Unit": "iMC" 1209 }, 1210 { 1211 "BriefDescription": "RD_CAS Access to Rank 2; All Banks", 1212 "Counter": "0,1,2,3", 1213 "EventCode": "0xB2", 1214 "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", 1215 "PerPkg": "1", 1216 "UMask": "0x10", 1217 "Unit": "iMC" 1218 }, 1219 { 1220 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", 1221 "Counter": "0,1,2,3", 1222 "EventCode": "0xB2", 1223 "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", 1224 "PerPkg": "1", 1225 "UMask": "0x11", 1226 "Unit": "iMC" 1227 }, 1228 { 1229 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", 1230 "Counter": "0,1,2,3", 1231 "EventCode": "0xB2", 1232 "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", 1233 "PerPkg": "1", 1234 "UMask": "0x12", 1235 "Unit": "iMC" 1236 }, 1237 { 1238 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", 1239 "Counter": "0,1,2,3", 1240 "EventCode": "0xB2", 1241 "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", 1242 "PerPkg": "1", 1243 "UMask": "0x13", 1244 "Unit": "iMC" 1245 }, 1246 { 1247 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", 1248 "Counter": "0,1,2,3", 1249 "EventCode": "0xB2", 1250 "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", 1251 "PerPkg": "1", 1252 "UMask": "0x14", 1253 "Unit": "iMC" 1254 }, 1255 { 1256 "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", 1257 "Counter": "0,1,2,3", 1258 "EventCode": "0xB3", 1259 "EventName": "UNC_M_RD_CAS_RANK3.BANK0", 1260 "PerPkg": "1", 1261 "Unit": "iMC" 1262 }, 1263 { 1264 "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", 1265 "Counter": "0,1,2,3", 1266 "EventCode": "0xB3", 1267 "EventName": "UNC_M_RD_CAS_RANK3.BANK1", 1268 "PerPkg": "1", 1269 "UMask": "0x1", 1270 "Unit": "iMC" 1271 }, 1272 { 1273 "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", 1274 "Counter": "0,1,2,3", 1275 "EventCode": "0xB3", 1276 "EventName": "UNC_M_RD_CAS_RANK3.BANK2", 1277 "PerPkg": "1", 1278 "UMask": "0x2", 1279 "Unit": "iMC" 1280 }, 1281 { 1282 "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", 1283 "Counter": "0,1,2,3", 1284 "EventCode": "0xB3", 1285 "EventName": "UNC_M_RD_CAS_RANK3.BANK3", 1286 "PerPkg": "1", 1287 "UMask": "0x3", 1288 "Unit": "iMC" 1289 }, 1290 { 1291 "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", 1292 "Counter": "0,1,2,3", 1293 "EventCode": "0xB3", 1294 "EventName": "UNC_M_RD_CAS_RANK3.BANK4", 1295 "PerPkg": "1", 1296 "UMask": "0x4", 1297 "Unit": "iMC" 1298 }, 1299 { 1300 "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", 1301 "Counter": "0,1,2,3", 1302 "EventCode": "0xB3", 1303 "EventName": "UNC_M_RD_CAS_RANK3.BANK5", 1304 "PerPkg": "1", 1305 "UMask": "0x5", 1306 "Unit": "iMC" 1307 }, 1308 { 1309 "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", 1310 "Counter": "0,1,2,3", 1311 "EventCode": "0xB3", 1312 "EventName": "UNC_M_RD_CAS_RANK3.BANK6", 1313 "PerPkg": "1", 1314 "UMask": "0x6", 1315 "Unit": "iMC" 1316 }, 1317 { 1318 "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", 1319 "Counter": "0,1,2,3", 1320 "EventCode": "0xB3", 1321 "EventName": "UNC_M_RD_CAS_RANK3.BANK7", 1322 "PerPkg": "1", 1323 "UMask": "0x7", 1324 "Unit": "iMC" 1325 }, 1326 { 1327 "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", 1328 "Counter": "0,1,2,3", 1329 "EventCode": "0xB3", 1330 "EventName": "UNC_M_RD_CAS_RANK3.BANK8", 1331 "PerPkg": "1", 1332 "UMask": "0x8", 1333 "Unit": "iMC" 1334 }, 1335 { 1336 "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", 1337 "Counter": "0,1,2,3", 1338 "EventCode": "0xB3", 1339 "EventName": "UNC_M_RD_CAS_RANK3.BANK9", 1340 "PerPkg": "1", 1341 "UMask": "0x9", 1342 "Unit": "iMC" 1343 }, 1344 { 1345 "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", 1346 "Counter": "0,1,2,3", 1347 "EventCode": "0xB3", 1348 "EventName": "UNC_M_RD_CAS_RANK3.BANK10", 1349 "PerPkg": "1", 1350 "UMask": "0xA", 1351 "Unit": "iMC" 1352 }, 1353 { 1354 "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", 1355 "Counter": "0,1,2,3", 1356 "EventCode": "0xB3", 1357 "EventName": "UNC_M_RD_CAS_RANK3.BANK11", 1358 "PerPkg": "1", 1359 "UMask": "0xB", 1360 "Unit": "iMC" 1361 }, 1362 { 1363 "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", 1364 "Counter": "0,1,2,3", 1365 "EventCode": "0xB3", 1366 "EventName": "UNC_M_RD_CAS_RANK3.BANK12", 1367 "PerPkg": "1", 1368 "UMask": "0xC", 1369 "Unit": "iMC" 1370 }, 1371 { 1372 "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", 1373 "Counter": "0,1,2,3", 1374 "EventCode": "0xB3", 1375 "EventName": "UNC_M_RD_CAS_RANK3.BANK13", 1376 "PerPkg": "1", 1377 "UMask": "0xD", 1378 "Unit": "iMC" 1379 }, 1380 { 1381 "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", 1382 "Counter": "0,1,2,3", 1383 "EventCode": "0xB3", 1384 "EventName": "UNC_M_RD_CAS_RANK3.BANK14", 1385 "PerPkg": "1", 1386 "UMask": "0xE", 1387 "Unit": "iMC" 1388 }, 1389 { 1390 "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", 1391 "Counter": "0,1,2,3", 1392 "EventCode": "0xB3", 1393 "EventName": "UNC_M_RD_CAS_RANK3.BANK15", 1394 "PerPkg": "1", 1395 "UMask": "0xF", 1396 "Unit": "iMC" 1397 }, 1398 { 1399 "BriefDescription": "RD_CAS Access to Rank 3; All Banks", 1400 "Counter": "0,1,2,3", 1401 "EventCode": "0xB3", 1402 "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", 1403 "PerPkg": "1", 1404 "UMask": "0x10", 1405 "Unit": "iMC" 1406 }, 1407 { 1408 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", 1409 "Counter": "0,1,2,3", 1410 "EventCode": "0xB3", 1411 "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", 1412 "PerPkg": "1", 1413 "UMask": "0x11", 1414 "Unit": "iMC" 1415 }, 1416 { 1417 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", 1418 "Counter": "0,1,2,3", 1419 "EventCode": "0xB3", 1420 "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", 1421 "PerPkg": "1", 1422 "UMask": "0x12", 1423 "Unit": "iMC" 1424 }, 1425 { 1426 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", 1427 "Counter": "0,1,2,3", 1428 "EventCode": "0xB3", 1429 "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", 1430 "PerPkg": "1", 1431 "UMask": "0x13", 1432 "Unit": "iMC" 1433 }, 1434 { 1435 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", 1436 "Counter": "0,1,2,3", 1437 "EventCode": "0xB3", 1438 "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", 1439 "PerPkg": "1", 1440 "UMask": "0x14", 1441 "Unit": "iMC" 1442 }, 1443 { 1444 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 1445 "Counter": "0,1,2,3", 1446 "EventCode": "0xB4", 1447 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 1448 "PerPkg": "1", 1449 "Unit": "iMC" 1450 }, 1451 { 1452 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 1453 "Counter": "0,1,2,3", 1454 "EventCode": "0xB4", 1455 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 1456 "PerPkg": "1", 1457 "UMask": "0x1", 1458 "Unit": "iMC" 1459 }, 1460 { 1461 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 1462 "Counter": "0,1,2,3", 1463 "EventCode": "0xB4", 1464 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 1465 "PerPkg": "1", 1466 "UMask": "0x2", 1467 "Unit": "iMC" 1468 }, 1469 { 1470 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 1471 "Counter": "0,1,2,3", 1472 "EventCode": "0xB4", 1473 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 1474 "PerPkg": "1", 1475 "UMask": "0x3", 1476 "Unit": "iMC" 1477 }, 1478 { 1479 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 1480 "Counter": "0,1,2,3", 1481 "EventCode": "0xB4", 1482 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 1483 "PerPkg": "1", 1484 "UMask": "0x4", 1485 "Unit": "iMC" 1486 }, 1487 { 1488 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 1489 "Counter": "0,1,2,3", 1490 "EventCode": "0xB4", 1491 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 1492 "PerPkg": "1", 1493 "UMask": "0x5", 1494 "Unit": "iMC" 1495 }, 1496 { 1497 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 1498 "Counter": "0,1,2,3", 1499 "EventCode": "0xB4", 1500 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 1501 "PerPkg": "1", 1502 "UMask": "0x6", 1503 "Unit": "iMC" 1504 }, 1505 { 1506 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 1507 "Counter": "0,1,2,3", 1508 "EventCode": "0xB4", 1509 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 1510 "PerPkg": "1", 1511 "UMask": "0x7", 1512 "Unit": "iMC" 1513 }, 1514 { 1515 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 1516 "Counter": "0,1,2,3", 1517 "EventCode": "0xB4", 1518 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 1519 "PerPkg": "1", 1520 "UMask": "0x8", 1521 "Unit": "iMC" 1522 }, 1523 { 1524 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 1525 "Counter": "0,1,2,3", 1526 "EventCode": "0xB4", 1527 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 1528 "PerPkg": "1", 1529 "UMask": "0x9", 1530 "Unit": "iMC" 1531 }, 1532 { 1533 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1534 "Counter": "0,1,2,3", 1535 "EventCode": "0xB4", 1536 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1537 "PerPkg": "1", 1538 "UMask": "0xA", 1539 "Unit": "iMC" 1540 }, 1541 { 1542 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1543 "Counter": "0,1,2,3", 1544 "EventCode": "0xB4", 1545 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1546 "PerPkg": "1", 1547 "UMask": "0xB", 1548 "Unit": "iMC" 1549 }, 1550 { 1551 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1552 "Counter": "0,1,2,3", 1553 "EventCode": "0xB4", 1554 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1555 "PerPkg": "1", 1556 "UMask": "0xC", 1557 "Unit": "iMC" 1558 }, 1559 { 1560 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1561 "Counter": "0,1,2,3", 1562 "EventCode": "0xB4", 1563 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1564 "PerPkg": "1", 1565 "UMask": "0xD", 1566 "Unit": "iMC" 1567 }, 1568 { 1569 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1570 "Counter": "0,1,2,3", 1571 "EventCode": "0xB4", 1572 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1573 "PerPkg": "1", 1574 "UMask": "0xE", 1575 "Unit": "iMC" 1576 }, 1577 { 1578 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1579 "Counter": "0,1,2,3", 1580 "EventCode": "0xB4", 1581 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1582 "PerPkg": "1", 1583 "UMask": "0xF", 1584 "Unit": "iMC" 1585 }, 1586 { 1587 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 1588 "Counter": "0,1,2,3", 1589 "EventCode": "0xB4", 1590 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 1591 "PerPkg": "1", 1592 "UMask": "0x10", 1593 "Unit": "iMC" 1594 }, 1595 { 1596 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1597 "Counter": "0,1,2,3", 1598 "EventCode": "0xB4", 1599 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1600 "PerPkg": "1", 1601 "UMask": "0x11", 1602 "Unit": "iMC" 1603 }, 1604 { 1605 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1606 "Counter": "0,1,2,3", 1607 "EventCode": "0xB4", 1608 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1609 "PerPkg": "1", 1610 "UMask": "0x12", 1611 "Unit": "iMC" 1612 }, 1613 { 1614 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1615 "Counter": "0,1,2,3", 1616 "EventCode": "0xB4", 1617 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1618 "PerPkg": "1", 1619 "UMask": "0x13", 1620 "Unit": "iMC" 1621 }, 1622 { 1623 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1624 "Counter": "0,1,2,3", 1625 "EventCode": "0xB4", 1626 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1627 "PerPkg": "1", 1628 "UMask": "0x14", 1629 "Unit": "iMC" 1630 }, 1631 { 1632 "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", 1633 "Counter": "0,1,2,3", 1634 "EventCode": "0xB5", 1635 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1636 "PerPkg": "1", 1637 "Unit": "iMC" 1638 }, 1639 { 1640 "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", 1641 "Counter": "0,1,2,3", 1642 "EventCode": "0xB5", 1643 "EventName": "UNC_M_RD_CAS_RANK5.BANK1", 1644 "PerPkg": "1", 1645 "UMask": "0x1", 1646 "Unit": "iMC" 1647 }, 1648 { 1649 "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", 1650 "Counter": "0,1,2,3", 1651 "EventCode": "0xB5", 1652 "EventName": "UNC_M_RD_CAS_RANK5.BANK2", 1653 "PerPkg": "1", 1654 "UMask": "0x2", 1655 "Unit": "iMC" 1656 }, 1657 { 1658 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1659 "Counter": "0,1,2,3", 1660 "EventCode": "0xB5", 1661 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1662 "PerPkg": "1", 1663 "UMask": "0x3", 1664 "Unit": "iMC" 1665 }, 1666 { 1667 "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", 1668 "Counter": "0,1,2,3", 1669 "EventCode": "0xB5", 1670 "EventName": "UNC_M_RD_CAS_RANK5.BANK4", 1671 "PerPkg": "1", 1672 "UMask": "0x4", 1673 "Unit": "iMC" 1674 }, 1675 { 1676 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1677 "Counter": "0,1,2,3", 1678 "EventCode": "0xB5", 1679 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1680 "PerPkg": "1", 1681 "UMask": "0x5", 1682 "Unit": "iMC" 1683 }, 1684 { 1685 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1686 "Counter": "0,1,2,3", 1687 "EventCode": "0xB5", 1688 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1689 "PerPkg": "1", 1690 "UMask": "0x6", 1691 "Unit": "iMC" 1692 }, 1693 { 1694 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1695 "Counter": "0,1,2,3", 1696 "EventCode": "0xB5", 1697 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1698 "PerPkg": "1", 1699 "UMask": "0x7", 1700 "Unit": "iMC" 1701 }, 1702 { 1703 "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", 1704 "Counter": "0,1,2,3", 1705 "EventCode": "0xB5", 1706 "EventName": "UNC_M_RD_CAS_RANK5.BANK8", 1707 "PerPkg": "1", 1708 "UMask": "0x8", 1709 "Unit": "iMC" 1710 }, 1711 { 1712 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1713 "Counter": "0,1,2,3", 1714 "EventCode": "0xB5", 1715 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1716 "PerPkg": "1", 1717 "UMask": "0x9", 1718 "Unit": "iMC" 1719 }, 1720 { 1721 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1722 "Counter": "0,1,2,3", 1723 "EventCode": "0xB5", 1724 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1725 "PerPkg": "1", 1726 "UMask": "0xA", 1727 "Unit": "iMC" 1728 }, 1729 { 1730 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1731 "Counter": "0,1,2,3", 1732 "EventCode": "0xB5", 1733 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1734 "PerPkg": "1", 1735 "UMask": "0xB", 1736 "Unit": "iMC" 1737 }, 1738 { 1739 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1740 "Counter": "0,1,2,3", 1741 "EventCode": "0xB5", 1742 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1743 "PerPkg": "1", 1744 "UMask": "0xC", 1745 "Unit": "iMC" 1746 }, 1747 { 1748 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1749 "Counter": "0,1,2,3", 1750 "EventCode": "0xB5", 1751 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1752 "PerPkg": "1", 1753 "UMask": "0xD", 1754 "Unit": "iMC" 1755 }, 1756 { 1757 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1758 "Counter": "0,1,2,3", 1759 "EventCode": "0xB5", 1760 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1761 "PerPkg": "1", 1762 "UMask": "0xE", 1763 "Unit": "iMC" 1764 }, 1765 { 1766 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1767 "Counter": "0,1,2,3", 1768 "EventCode": "0xB5", 1769 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1770 "PerPkg": "1", 1771 "UMask": "0xF", 1772 "Unit": "iMC" 1773 }, 1774 { 1775 "BriefDescription": "RD_CAS Access to Rank 5; All Banks", 1776 "Counter": "0,1,2,3", 1777 "EventCode": "0xB5", 1778 "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", 1779 "PerPkg": "1", 1780 "UMask": "0x10", 1781 "Unit": "iMC" 1782 }, 1783 { 1784 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1785 "Counter": "0,1,2,3", 1786 "EventCode": "0xB5", 1787 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1788 "PerPkg": "1", 1789 "UMask": "0x11", 1790 "Unit": "iMC" 1791 }, 1792 { 1793 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1794 "Counter": "0,1,2,3", 1795 "EventCode": "0xB5", 1796 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1797 "PerPkg": "1", 1798 "UMask": "0x12", 1799 "Unit": "iMC" 1800 }, 1801 { 1802 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1803 "Counter": "0,1,2,3", 1804 "EventCode": "0xB5", 1805 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1806 "PerPkg": "1", 1807 "UMask": "0x13", 1808 "Unit": "iMC" 1809 }, 1810 { 1811 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1812 "Counter": "0,1,2,3", 1813 "EventCode": "0xB5", 1814 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1815 "PerPkg": "1", 1816 "UMask": "0x14", 1817 "Unit": "iMC" 1818 }, 1819 { 1820 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1821 "Counter": "0,1,2,3", 1822 "EventCode": "0xB6", 1823 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1824 "PerPkg": "1", 1825 "Unit": "iMC" 1826 }, 1827 { 1828 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1829 "Counter": "0,1,2,3", 1830 "EventCode": "0xB6", 1831 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1832 "PerPkg": "1", 1833 "UMask": "0x1", 1834 "Unit": "iMC" 1835 }, 1836 { 1837 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1838 "Counter": "0,1,2,3", 1839 "EventCode": "0xB6", 1840 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1841 "PerPkg": "1", 1842 "UMask": "0x2", 1843 "Unit": "iMC" 1844 }, 1845 { 1846 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1847 "Counter": "0,1,2,3", 1848 "EventCode": "0xB6", 1849 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1850 "PerPkg": "1", 1851 "UMask": "0x3", 1852 "Unit": "iMC" 1853 }, 1854 { 1855 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1856 "Counter": "0,1,2,3", 1857 "EventCode": "0xB6", 1858 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1859 "PerPkg": "1", 1860 "UMask": "0x4", 1861 "Unit": "iMC" 1862 }, 1863 { 1864 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1865 "Counter": "0,1,2,3", 1866 "EventCode": "0xB6", 1867 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1868 "PerPkg": "1", 1869 "UMask": "0x5", 1870 "Unit": "iMC" 1871 }, 1872 { 1873 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1874 "Counter": "0,1,2,3", 1875 "EventCode": "0xB6", 1876 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1877 "PerPkg": "1", 1878 "UMask": "0x6", 1879 "Unit": "iMC" 1880 }, 1881 { 1882 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1883 "Counter": "0,1,2,3", 1884 "EventCode": "0xB6", 1885 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1886 "PerPkg": "1", 1887 "UMask": "0x7", 1888 "Unit": "iMC" 1889 }, 1890 { 1891 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1892 "Counter": "0,1,2,3", 1893 "EventCode": "0xB6", 1894 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1895 "PerPkg": "1", 1896 "UMask": "0x8", 1897 "Unit": "iMC" 1898 }, 1899 { 1900 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1901 "Counter": "0,1,2,3", 1902 "EventCode": "0xB6", 1903 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1904 "PerPkg": "1", 1905 "UMask": "0x9", 1906 "Unit": "iMC" 1907 }, 1908 { 1909 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1910 "Counter": "0,1,2,3", 1911 "EventCode": "0xB6", 1912 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1913 "PerPkg": "1", 1914 "UMask": "0xA", 1915 "Unit": "iMC" 1916 }, 1917 { 1918 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1919 "Counter": "0,1,2,3", 1920 "EventCode": "0xB6", 1921 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1922 "PerPkg": "1", 1923 "UMask": "0xB", 1924 "Unit": "iMC" 1925 }, 1926 { 1927 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1928 "Counter": "0,1,2,3", 1929 "EventCode": "0xB6", 1930 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1931 "PerPkg": "1", 1932 "UMask": "0xC", 1933 "Unit": "iMC" 1934 }, 1935 { 1936 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1937 "Counter": "0,1,2,3", 1938 "EventCode": "0xB6", 1939 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1940 "PerPkg": "1", 1941 "UMask": "0xD", 1942 "Unit": "iMC" 1943 }, 1944 { 1945 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1946 "Counter": "0,1,2,3", 1947 "EventCode": "0xB6", 1948 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1949 "PerPkg": "1", 1950 "UMask": "0xE", 1951 "Unit": "iMC" 1952 }, 1953 { 1954 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1955 "Counter": "0,1,2,3", 1956 "EventCode": "0xB6", 1957 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1958 "PerPkg": "1", 1959 "UMask": "0xF", 1960 "Unit": "iMC" 1961 }, 1962 { 1963 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1964 "Counter": "0,1,2,3", 1965 "EventCode": "0xB6", 1966 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1967 "PerPkg": "1", 1968 "UMask": "0x10", 1969 "Unit": "iMC" 1970 }, 1971 { 1972 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1973 "Counter": "0,1,2,3", 1974 "EventCode": "0xB6", 1975 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1976 "PerPkg": "1", 1977 "UMask": "0x11", 1978 "Unit": "iMC" 1979 }, 1980 { 1981 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1982 "Counter": "0,1,2,3", 1983 "EventCode": "0xB6", 1984 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1985 "PerPkg": "1", 1986 "UMask": "0x12", 1987 "Unit": "iMC" 1988 }, 1989 { 1990 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1991 "Counter": "0,1,2,3", 1992 "EventCode": "0xB6", 1993 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1994 "PerPkg": "1", 1995 "UMask": "0x13", 1996 "Unit": "iMC" 1997 }, 1998 { 1999 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 2000 "Counter": "0,1,2,3", 2001 "EventCode": "0xB6", 2002 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 2003 "PerPkg": "1", 2004 "UMask": "0x14", 2005 "Unit": "iMC" 2006 }, 2007 { 2008 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 2009 "Counter": "0,1,2,3", 2010 "EventCode": "0xB7", 2011 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 2012 "PerPkg": "1", 2013 "Unit": "iMC" 2014 }, 2015 { 2016 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 2017 "Counter": "0,1,2,3", 2018 "EventCode": "0xB7", 2019 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 2020 "PerPkg": "1", 2021 "UMask": "0x1", 2022 "Unit": "iMC" 2023 }, 2024 { 2025 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 2026 "Counter": "0,1,2,3", 2027 "EventCode": "0xB7", 2028 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 2029 "PerPkg": "1", 2030 "UMask": "0x2", 2031 "Unit": "iMC" 2032 }, 2033 { 2034 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 2035 "Counter": "0,1,2,3", 2036 "EventCode": "0xB7", 2037 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 2038 "PerPkg": "1", 2039 "UMask": "0x3", 2040 "Unit": "iMC" 2041 }, 2042 { 2043 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 2044 "Counter": "0,1,2,3", 2045 "EventCode": "0xB7", 2046 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 2047 "PerPkg": "1", 2048 "UMask": "0x4", 2049 "Unit": "iMC" 2050 }, 2051 { 2052 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 2053 "Counter": "0,1,2,3", 2054 "EventCode": "0xB7", 2055 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 2056 "PerPkg": "1", 2057 "UMask": "0x5", 2058 "Unit": "iMC" 2059 }, 2060 { 2061 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 2062 "Counter": "0,1,2,3", 2063 "EventCode": "0xB7", 2064 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 2065 "PerPkg": "1", 2066 "UMask": "0x6", 2067 "Unit": "iMC" 2068 }, 2069 { 2070 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 2071 "Counter": "0,1,2,3", 2072 "EventCode": "0xB7", 2073 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 2074 "PerPkg": "1", 2075 "UMask": "0x7", 2076 "Unit": "iMC" 2077 }, 2078 { 2079 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 2080 "Counter": "0,1,2,3", 2081 "EventCode": "0xB7", 2082 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 2083 "PerPkg": "1", 2084 "UMask": "0x8", 2085 "Unit": "iMC" 2086 }, 2087 { 2088 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 2089 "Counter": "0,1,2,3", 2090 "EventCode": "0xB7", 2091 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 2092 "PerPkg": "1", 2093 "UMask": "0x9", 2094 "Unit": "iMC" 2095 }, 2096 { 2097 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 2098 "Counter": "0,1,2,3", 2099 "EventCode": "0xB7", 2100 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 2101 "PerPkg": "1", 2102 "UMask": "0xA", 2103 "Unit": "iMC" 2104 }, 2105 { 2106 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 2107 "Counter": "0,1,2,3", 2108 "EventCode": "0xB7", 2109 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 2110 "PerPkg": "1", 2111 "UMask": "0xB", 2112 "Unit": "iMC" 2113 }, 2114 { 2115 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 2116 "Counter": "0,1,2,3", 2117 "EventCode": "0xB7", 2118 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 2119 "PerPkg": "1", 2120 "UMask": "0xC", 2121 "Unit": "iMC" 2122 }, 2123 { 2124 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 2125 "Counter": "0,1,2,3", 2126 "EventCode": "0xB7", 2127 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 2128 "PerPkg": "1", 2129 "UMask": "0xD", 2130 "Unit": "iMC" 2131 }, 2132 { 2133 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 2134 "Counter": "0,1,2,3", 2135 "EventCode": "0xB7", 2136 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 2137 "PerPkg": "1", 2138 "UMask": "0xE", 2139 "Unit": "iMC" 2140 }, 2141 { 2142 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 2143 "Counter": "0,1,2,3", 2144 "EventCode": "0xB7", 2145 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 2146 "PerPkg": "1", 2147 "UMask": "0xF", 2148 "Unit": "iMC" 2149 }, 2150 { 2151 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 2152 "Counter": "0,1,2,3", 2153 "EventCode": "0xB7", 2154 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 2155 "PerPkg": "1", 2156 "UMask": "0x10", 2157 "Unit": "iMC" 2158 }, 2159 { 2160 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 2161 "Counter": "0,1,2,3", 2162 "EventCode": "0xB7", 2163 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 2164 "PerPkg": "1", 2165 "UMask": "0x11", 2166 "Unit": "iMC" 2167 }, 2168 { 2169 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 2170 "Counter": "0,1,2,3", 2171 "EventCode": "0xB7", 2172 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 2173 "PerPkg": "1", 2174 "UMask": "0x12", 2175 "Unit": "iMC" 2176 }, 2177 { 2178 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 2179 "Counter": "0,1,2,3", 2180 "EventCode": "0xB7", 2181 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 2182 "PerPkg": "1", 2183 "UMask": "0x13", 2184 "Unit": "iMC" 2185 }, 2186 { 2187 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 2188 "Counter": "0,1,2,3", 2189 "EventCode": "0xB7", 2190 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 2191 "PerPkg": "1", 2192 "UMask": "0x14", 2193 "Unit": "iMC" 2194 }, 2195 { 2196 "BriefDescription": "Read Pending Queue Full Cycles", 2197 "Counter": "0,1,2,3", 2198 "EventCode": "0x12", 2199 "EventName": "UNC_M_RPQ_CYCLES_FULL", 2200 "PerPkg": "1", 2201 "Unit": "iMC" 2202 }, 2203 { 2204 "BriefDescription": "Read Pending Queue Not Empty", 2205 "Counter": "0,1,2,3", 2206 "EventCode": "0x11", 2207 "EventName": "UNC_M_RPQ_CYCLES_NE", 2208 "PerPkg": "1", 2209 "Unit": "iMC" 2210 }, 2211 { 2212 "BriefDescription": "Scoreboard Accesses; Read Accepts", 2213 "Counter": "0,1,2,3", 2214 "EventCode": "0xD2", 2215 "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", 2216 "PerPkg": "1", 2217 "UMask": "0x1", 2218 "Unit": "iMC" 2219 }, 2220 { 2221 "BriefDescription": "Scoreboard Accesses; Read Rejects", 2222 "Counter": "0,1,2,3", 2223 "EventCode": "0xD2", 2224 "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", 2225 "PerPkg": "1", 2226 "UMask": "0x2", 2227 "Unit": "iMC" 2228 }, 2229 { 2230 "BriefDescription": "Scoreboard Accesses; NM read completions", 2231 "Counter": "0,1,2,3", 2232 "EventCode": "0xD2", 2233 "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", 2234 "PerPkg": "1", 2235 "UMask": "0x4", 2236 "Unit": "iMC" 2237 }, 2238 { 2239 "BriefDescription": "Scoreboard Accesses; NM write completions", 2240 "Counter": "0,1,2,3", 2241 "EventCode": "0xD2", 2242 "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", 2243 "PerPkg": "1", 2244 "UMask": "0x8", 2245 "Unit": "iMC" 2246 }, 2247 { 2248 "BriefDescription": "Scoreboard Accesses; FM read completions", 2249 "Counter": "0,1,2,3", 2250 "EventCode": "0xD2", 2251 "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", 2252 "PerPkg": "1", 2253 "UMask": "0x10", 2254 "Unit": "iMC" 2255 }, 2256 { 2257 "BriefDescription": "Scoreboard Accesses; FM write completions", 2258 "Counter": "0,1,2,3", 2259 "EventCode": "0xD2", 2260 "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", 2261 "PerPkg": "1", 2262 "UMask": "0x20", 2263 "Unit": "iMC" 2264 }, 2265 { 2266 "BriefDescription": "Scoreboard Accesses; Write Accepts", 2267 "Counter": "0,1,2,3", 2268 "EventCode": "0xD2", 2269 "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", 2270 "PerPkg": "1", 2271 "UMask": "0x40", 2272 "Unit": "iMC" 2273 }, 2274 { 2275 "BriefDescription": "Scoreboard Accesses; Write Rejects", 2276 "Counter": "0,1,2,3", 2277 "EventCode": "0xD2", 2278 "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", 2279 "PerPkg": "1", 2280 "UMask": "0x80", 2281 "Unit": "iMC" 2282 }, 2283 { 2284 "BriefDescription": "Alloc", 2285 "Counter": "0,1,2,3", 2286 "EventCode": "0xD9", 2287 "EventName": "UNC_M_SB_CANARY.ALLOC", 2288 "PerPkg": "1", 2289 "UMask": "0x1", 2290 "Unit": "iMC" 2291 }, 2292 { 2293 "BriefDescription": "Dealloc", 2294 "Counter": "0,1,2,3", 2295 "EventCode": "0xD9", 2296 "EventName": "UNC_M_SB_CANARY.DEALLOC", 2297 "PerPkg": "1", 2298 "UMask": "0x2", 2299 "Unit": "iMC" 2300 }, 2301 { 2302 "BriefDescription": "Reject", 2303 "Counter": "0,1,2,3", 2304 "EventCode": "0xD9", 2305 "EventName": "UNC_M_SB_CANARY.REJ", 2306 "PerPkg": "1", 2307 "UMask": "0x4", 2308 "Unit": "iMC" 2309 }, 2310 { 2311 "BriefDescription": "Valid", 2312 "Counter": "0,1,2,3", 2313 "EventCode": "0xD9", 2314 "EventName": "UNC_M_SB_CANARY.VLD", 2315 "PerPkg": "1", 2316 "UMask": "0x8", 2317 "Unit": "iMC" 2318 }, 2319 { 2320 "BriefDescription": "Near Mem Read Starved", 2321 "Counter": "0,1,2,3", 2322 "EventCode": "0xD9", 2323 "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", 2324 "PerPkg": "1", 2325 "UMask": "0x10", 2326 "Unit": "iMC" 2327 }, 2328 { 2329 "BriefDescription": "Near Mem Write Starved", 2330 "Counter": "0,1,2,3", 2331 "EventCode": "0xD9", 2332 "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", 2333 "PerPkg": "1", 2334 "UMask": "0x20", 2335 "Unit": "iMC" 2336 }, 2337 { 2338 "BriefDescription": "Far Mem Read Starved", 2339 "Counter": "0,1,2,3", 2340 "EventCode": "0xD9", 2341 "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", 2342 "PerPkg": "1", 2343 "UMask": "0x40", 2344 "Unit": "iMC" 2345 }, 2346 { 2347 "BriefDescription": "Far Mem Write Starved", 2348 "Counter": "0,1,2,3", 2349 "EventCode": "0xD9", 2350 "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", 2351 "PerPkg": "1", 2352 "UMask": "0x80", 2353 "Unit": "iMC" 2354 }, 2355 { 2356 "BriefDescription": "Scoreboard Cycles Full", 2357 "Counter": "0,1,2,3", 2358 "EventCode": "0xD1", 2359 "EventName": "UNC_M_SB_CYCLES_FULL", 2360 "PerPkg": "1", 2361 "Unit": "iMC" 2362 }, 2363 { 2364 "BriefDescription": "Scoreboard Cycles Not-Empty", 2365 "Counter": "0,1,2,3", 2366 "EventCode": "0xD0", 2367 "EventName": "UNC_M_SB_CYCLES_NE", 2368 "PerPkg": "1", 2369 "Unit": "iMC" 2370 }, 2371 { 2372 "BriefDescription": "Scoreboard Inserts; Reads", 2373 "Counter": "0,1,2,3", 2374 "EventCode": "0xD6", 2375 "EventName": "UNC_M_SB_INSERTS.RDS", 2376 "PerPkg": "1", 2377 "UMask": "0x1", 2378 "Unit": "iMC" 2379 }, 2380 { 2381 "BriefDescription": "Scoreboard Inserts; Writes", 2382 "Counter": "0,1,2,3", 2383 "EventCode": "0xD6", 2384 "EventName": "UNC_M_SB_INSERTS.WRS", 2385 "PerPkg": "1", 2386 "UMask": "0x2", 2387 "Unit": "iMC" 2388 }, 2389 { 2390 "BriefDescription": "Scoreboard Inserts; Block region reads", 2391 "Counter": "0,1,2,3", 2392 "EventCode": "0xD6", 2393 "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", 2394 "PerPkg": "1", 2395 "UMask": "0x10", 2396 "Unit": "iMC" 2397 }, 2398 { 2399 "BriefDescription": "Scoreboard Inserts; Block region writes", 2400 "Counter": "0,1,2,3", 2401 "EventCode": "0xD6", 2402 "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", 2403 "PerPkg": "1", 2404 "UMask": "0x20", 2405 "Unit": "iMC" 2406 }, 2407 { 2408 "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)", 2409 "Counter": "0,1,2,3", 2410 "EventCode": "0xD6", 2411 "EventName": "UNC_M_SB_INSERTS.DEALLOC", 2412 "PerPkg": "1", 2413 "UMask": "0x40", 2414 "Unit": "iMC" 2415 }, 2416 { 2417 "BriefDescription": "Scoreboard Inserts; Patrol inserts", 2418 "Counter": "0,1,2,3", 2419 "EventCode": "0xD6", 2420 "EventName": "UNC_M_SB_INSERTS.PATROL", 2421 "PerPkg": "1", 2422 "UMask": "0x80", 2423 "Unit": "iMC" 2424 }, 2425 { 2426 "BriefDescription": "Scoreboard Occupancy; Reads", 2427 "Counter": "0,1,2,3", 2428 "EventCode": "0xD5", 2429 "EventName": "UNC_M_SB_OCCUPANCY.RDS", 2430 "PerPkg": "1", 2431 "UMask": "0x1", 2432 "Unit": "iMC" 2433 }, 2434 { 2435 "BriefDescription": "Scoreboard Occupancy; Writes", 2436 "Counter": "0,1,2,3", 2437 "EventCode": "0xD5", 2438 "EventName": "UNC_M_SB_OCCUPANCY.WRS", 2439 "PerPkg": "1", 2440 "UMask": "0x2", 2441 "Unit": "iMC" 2442 }, 2443 { 2444 "BriefDescription": "Scoreboard Occupancy; Block region reads", 2445 "Counter": "0,1,2,3", 2446 "EventCode": "0xD5", 2447 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", 2448 "PerPkg": "1", 2449 "UMask": "0x20", 2450 "Unit": "iMC" 2451 }, 2452 { 2453 "BriefDescription": "Scoreboard Occupancy; Block region writes", 2454 "Counter": "0,1,2,3", 2455 "EventCode": "0xD5", 2456 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", 2457 "PerPkg": "1", 2458 "UMask": "0x40", 2459 "Unit": "iMC" 2460 }, 2461 { 2462 "BriefDescription": "Scoreboard Occupancy; Patrol", 2463 "Counter": "0,1,2,3", 2464 "EventCode": "0xD5", 2465 "EventName": "UNC_M_SB_OCCUPANCY.PATROL", 2466 "PerPkg": "1", 2467 "UMask": "0x80", 2468 "Unit": "iMC" 2469 }, 2470 { 2471 "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict", 2472 "Counter": "0,1,2,3", 2473 "EventCode": "0xD4", 2474 "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", 2475 "PerPkg": "1", 2476 "UMask": "0x1", 2477 "Unit": "iMC" 2478 }, 2479 { 2480 "BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict", 2481 "Counter": "0,1,2,3", 2482 "EventCode": "0xD4", 2483 "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", 2484 "PerPkg": "1", 2485 "UMask": "0x2", 2486 "Unit": "iMC" 2487 }, 2488 { 2489 "BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict", 2490 "Counter": "0,1,2,3", 2491 "EventCode": "0xD4", 2492 "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", 2493 "PerPkg": "1", 2494 "UMask": "0x4", 2495 "Unit": "iMC" 2496 }, 2497 { 2498 "BriefDescription": "Near Mem Read - Set", 2499 "Counter": "0,1,2,3", 2500 "EventCode": "0xD7", 2501 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET", 2502 "PerPkg": "1", 2503 "UMask": "0x1", 2504 "Unit": "iMC" 2505 }, 2506 { 2507 "BriefDescription": "Far Mem Read - Set", 2508 "Counter": "0,1,2,3", 2509 "EventCode": "0xD7", 2510 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET", 2511 "PerPkg": "1", 2512 "UMask": "0x2", 2513 "Unit": "iMC" 2514 }, 2515 { 2516 "BriefDescription": "Near Mem Write - Set", 2517 "Counter": "0,1,2,3", 2518 "EventCode": "0xD7", 2519 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET", 2520 "PerPkg": "1", 2521 "UMask": "0x4", 2522 "Unit": "iMC" 2523 }, 2524 { 2525 "BriefDescription": "Far Mem Write - Set", 2526 "Counter": "0,1,2,3", 2527 "EventCode": "0xD7", 2528 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET", 2529 "PerPkg": "1", 2530 "UMask": "0x8", 2531 "Unit": "iMC" 2532 }, 2533 { 2534 "BriefDescription": "Near Mem Read - Clear", 2535 "Counter": "0,1,2,3", 2536 "EventCode": "0xD7", 2537 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR", 2538 "PerPkg": "1", 2539 "UMask": "0x10", 2540 "Unit": "iMC" 2541 }, 2542 { 2543 "BriefDescription": "Far Mem Read - Clear", 2544 "Counter": "0,1,2,3", 2545 "EventCode": "0xD7", 2546 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR", 2547 "PerPkg": "1", 2548 "UMask": "0x20", 2549 "Unit": "iMC" 2550 }, 2551 { 2552 "BriefDescription": "Near Mem Write - Clear", 2553 "Counter": "0,1,2,3", 2554 "EventCode": "0xD7", 2555 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR", 2556 "PerPkg": "1", 2557 "UMask": "0x40", 2558 "Unit": "iMC" 2559 }, 2560 { 2561 "BriefDescription": "Far Mem Write - Clear", 2562 "Counter": "0,1,2,3", 2563 "EventCode": "0xD7", 2564 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR", 2565 "PerPkg": "1", 2566 "UMask": "0x80", 2567 "Unit": "iMC" 2568 }, 2569 { 2570 "BriefDescription": "Near Mem Read", 2571 "Counter": "0,1,2,3", 2572 "EventCode": "0xD8", 2573 "EventName": "UNC_M_SB_STRV_OCC.NMRD", 2574 "PerPkg": "1", 2575 "UMask": "0x1", 2576 "Unit": "iMC" 2577 }, 2578 { 2579 "BriefDescription": "Far Mem Read", 2580 "Counter": "0,1,2,3", 2581 "EventCode": "0xD8", 2582 "EventName": "UNC_M_SB_STRV_OCC.FMRD", 2583 "PerPkg": "1", 2584 "UMask": "0x2", 2585 "Unit": "iMC" 2586 }, 2587 { 2588 "BriefDescription": "Near Mem Write", 2589 "Counter": "0,1,2,3", 2590 "EventCode": "0xD8", 2591 "EventName": "UNC_M_SB_STRV_OCC.NMWR", 2592 "PerPkg": "1", 2593 "UMask": "0x4", 2594 "Unit": "iMC" 2595 }, 2596 { 2597 "BriefDescription": "Far Mem Write", 2598 "Counter": "0,1,2,3", 2599 "EventCode": "0xD8", 2600 "EventName": "UNC_M_SB_STRV_OCC.FMWR", 2601 "PerPkg": "1", 2602 "UMask": "0x8", 2603 "Unit": "iMC" 2604 }, 2605 { 2606 "BriefDescription": "UNC_M_SB_TAGGED.NEW", 2607 "Counter": "0,1,2,3", 2608 "EventCode": "0xDD", 2609 "EventName": "UNC_M_SB_TAGGED.NEW", 2610 "PerPkg": "1", 2611 "UMask": "0x1", 2612 "Unit": "iMC" 2613 }, 2614 { 2615 "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", 2616 "Counter": "0,1,2,3", 2617 "EventCode": "0xDD", 2618 "EventName": "UNC_M_SB_TAGGED.RD_HIT", 2619 "PerPkg": "1", 2620 "UMask": "0x2", 2621 "Unit": "iMC" 2622 }, 2623 { 2624 "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", 2625 "Counter": "0,1,2,3", 2626 "EventCode": "0xDD", 2627 "EventName": "UNC_M_SB_TAGGED.RD_MISS", 2628 "PerPkg": "1", 2629 "UMask": "0x4", 2630 "Unit": "iMC" 2631 }, 2632 { 2633 "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", 2634 "Counter": "0,1,2,3", 2635 "EventCode": "0xDD", 2636 "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", 2637 "PerPkg": "1", 2638 "UMask": "0x8", 2639 "Unit": "iMC" 2640 }, 2641 { 2642 "BriefDescription": "UNC_M_SB_TAGGED.OCC", 2643 "Counter": "0,1,2,3", 2644 "EventCode": "0xDD", 2645 "EventName": "UNC_M_SB_TAGGED.OCC", 2646 "PerPkg": "1", 2647 "UMask": "0x80", 2648 "Unit": "iMC" 2649 }, 2650 { 2651 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 2652 "Counter": "0,1,2,3", 2653 "EventCode": "0xC0", 2654 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 2655 "PerPkg": "1", 2656 "UMask": "0x1", 2657 "Unit": "iMC" 2658 }, 2659 { 2660 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2661 "Counter": "0,1,2,3", 2662 "EventCode": "0xC0", 2663 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 2664 "PerPkg": "1", 2665 "UMask": "0x2", 2666 "Unit": "iMC" 2667 }, 2668 { 2669 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2670 "Counter": "0,1,2,3", 2671 "EventCode": "0xC0", 2672 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 2673 "PerPkg": "1", 2674 "UMask": "0x4", 2675 "Unit": "iMC" 2676 }, 2677 { 2678 "BriefDescription": "Write Pending Queue Full Cycles", 2679 "Counter": "0,1,2,3", 2680 "EventCode": "0x22", 2681 "EventName": "UNC_M_WPQ_CYCLES_FULL", 2682 "PerPkg": "1", 2683 "Unit": "iMC" 2684 }, 2685 { 2686 "BriefDescription": "Write Pending Queue Not Empty", 2687 "Counter": "0,1,2,3", 2688 "EventCode": "0x21", 2689 "EventName": "UNC_M_WPQ_CYCLES_NE", 2690 "PerPkg": "1", 2691 "Unit": "iMC" 2692 }, 2693 { 2694 "BriefDescription": "Write Pending Queue CAM Match", 2695 "Counter": "0,1,2,3", 2696 "EventCode": "0x23", 2697 "EventName": "UNC_M_WPQ_READ_HIT", 2698 "PerPkg": "1", 2699 "Unit": "iMC" 2700 }, 2701 { 2702 "BriefDescription": "Write Pending Queue CAM Match", 2703 "Counter": "0,1,2,3", 2704 "EventCode": "0x24", 2705 "EventName": "UNC_M_WPQ_WRITE_HIT", 2706 "PerPkg": "1", 2707 "Unit": "iMC" 2708 }, 2709 { 2710 "BriefDescription": "Not getting the requested Major Mode", 2711 "Counter": "0,1,2,3", 2712 "EventCode": "0xC1", 2713 "EventName": "UNC_M_WRONG_MM", 2714 "PerPkg": "1", 2715 "Unit": "iMC" 2716 }, 2717 { 2718 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 2719 "Counter": "0,1,2,3", 2720 "EventCode": "0xB8", 2721 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 2722 "PerPkg": "1", 2723 "Unit": "iMC" 2724 }, 2725 { 2726 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 2727 "Counter": "0,1,2,3", 2728 "EventCode": "0xB8", 2729 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 2730 "PerPkg": "1", 2731 "UMask": "0x1", 2732 "Unit": "iMC" 2733 }, 2734 { 2735 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 2736 "Counter": "0,1,2,3", 2737 "EventCode": "0xB8", 2738 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 2739 "PerPkg": "1", 2740 "UMask": "0x2", 2741 "Unit": "iMC" 2742 }, 2743 { 2744 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 2745 "Counter": "0,1,2,3", 2746 "EventCode": "0xB8", 2747 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 2748 "PerPkg": "1", 2749 "UMask": "0x3", 2750 "Unit": "iMC" 2751 }, 2752 { 2753 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 2754 "Counter": "0,1,2,3", 2755 "EventCode": "0xB8", 2756 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 2757 "PerPkg": "1", 2758 "UMask": "0x4", 2759 "Unit": "iMC" 2760 }, 2761 { 2762 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 2763 "Counter": "0,1,2,3", 2764 "EventCode": "0xB8", 2765 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 2766 "PerPkg": "1", 2767 "UMask": "0x5", 2768 "Unit": "iMC" 2769 }, 2770 { 2771 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 2772 "Counter": "0,1,2,3", 2773 "EventCode": "0xB8", 2774 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 2775 "PerPkg": "1", 2776 "UMask": "0x6", 2777 "Unit": "iMC" 2778 }, 2779 { 2780 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 2781 "Counter": "0,1,2,3", 2782 "EventCode": "0xB8", 2783 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 2784 "PerPkg": "1", 2785 "UMask": "0x7", 2786 "Unit": "iMC" 2787 }, 2788 { 2789 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 2790 "Counter": "0,1,2,3", 2791 "EventCode": "0xB8", 2792 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 2793 "PerPkg": "1", 2794 "UMask": "0x8", 2795 "Unit": "iMC" 2796 }, 2797 { 2798 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 2799 "Counter": "0,1,2,3", 2800 "EventCode": "0xB8", 2801 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 2802 "PerPkg": "1", 2803 "UMask": "0x9", 2804 "Unit": "iMC" 2805 }, 2806 { 2807 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 2808 "Counter": "0,1,2,3", 2809 "EventCode": "0xB8", 2810 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 2811 "PerPkg": "1", 2812 "UMask": "0xA", 2813 "Unit": "iMC" 2814 }, 2815 { 2816 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 2817 "Counter": "0,1,2,3", 2818 "EventCode": "0xB8", 2819 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 2820 "PerPkg": "1", 2821 "UMask": "0xB", 2822 "Unit": "iMC" 2823 }, 2824 { 2825 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 2826 "Counter": "0,1,2,3", 2827 "EventCode": "0xB8", 2828 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 2829 "PerPkg": "1", 2830 "UMask": "0xC", 2831 "Unit": "iMC" 2832 }, 2833 { 2834 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 2835 "Counter": "0,1,2,3", 2836 "EventCode": "0xB8", 2837 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 2838 "PerPkg": "1", 2839 "UMask": "0xD", 2840 "Unit": "iMC" 2841 }, 2842 { 2843 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 2844 "Counter": "0,1,2,3", 2845 "EventCode": "0xB8", 2846 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 2847 "PerPkg": "1", 2848 "UMask": "0xE", 2849 "Unit": "iMC" 2850 }, 2851 { 2852 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 2853 "Counter": "0,1,2,3", 2854 "EventCode": "0xB8", 2855 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 2856 "PerPkg": "1", 2857 "UMask": "0xF", 2858 "Unit": "iMC" 2859 }, 2860 { 2861 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 2862 "Counter": "0,1,2,3", 2863 "EventCode": "0xB8", 2864 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 2865 "PerPkg": "1", 2866 "UMask": "0x10", 2867 "Unit": "iMC" 2868 }, 2869 { 2870 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 2871 "Counter": "0,1,2,3", 2872 "EventCode": "0xB8", 2873 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 2874 "PerPkg": "1", 2875 "UMask": "0x11", 2876 "Unit": "iMC" 2877 }, 2878 { 2879 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 2880 "Counter": "0,1,2,3", 2881 "EventCode": "0xB8", 2882 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 2883 "PerPkg": "1", 2884 "UMask": "0x12", 2885 "Unit": "iMC" 2886 }, 2887 { 2888 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 2889 "Counter": "0,1,2,3", 2890 "EventCode": "0xB8", 2891 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 2892 "PerPkg": "1", 2893 "UMask": "0x13", 2894 "Unit": "iMC" 2895 }, 2896 { 2897 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 2898 "Counter": "0,1,2,3", 2899 "EventCode": "0xB8", 2900 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 2901 "PerPkg": "1", 2902 "UMask": "0x14", 2903 "Unit": "iMC" 2904 }, 2905 { 2906 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 2907 "Counter": "0,1,2,3", 2908 "EventCode": "0xB9", 2909 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2910 "PerPkg": "1", 2911 "Unit": "iMC" 2912 }, 2913 { 2914 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 2915 "Counter": "0,1,2,3", 2916 "EventCode": "0xB9", 2917 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 2918 "PerPkg": "1", 2919 "UMask": "0x1", 2920 "Unit": "iMC" 2921 }, 2922 { 2923 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 2924 "Counter": "0,1,2,3", 2925 "EventCode": "0xB9", 2926 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 2927 "PerPkg": "1", 2928 "UMask": "0x2", 2929 "Unit": "iMC" 2930 }, 2931 { 2932 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2933 "Counter": "0,1,2,3", 2934 "EventCode": "0xB9", 2935 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2936 "PerPkg": "1", 2937 "UMask": "0x3", 2938 "Unit": "iMC" 2939 }, 2940 { 2941 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 2942 "Counter": "0,1,2,3", 2943 "EventCode": "0xB9", 2944 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 2945 "PerPkg": "1", 2946 "UMask": "0x4", 2947 "Unit": "iMC" 2948 }, 2949 { 2950 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2951 "Counter": "0,1,2,3", 2952 "EventCode": "0xB9", 2953 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2954 "PerPkg": "1", 2955 "UMask": "0x5", 2956 "Unit": "iMC" 2957 }, 2958 { 2959 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2960 "Counter": "0,1,2,3", 2961 "EventCode": "0xB9", 2962 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2963 "PerPkg": "1", 2964 "UMask": "0x6", 2965 "Unit": "iMC" 2966 }, 2967 { 2968 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2969 "Counter": "0,1,2,3", 2970 "EventCode": "0xB9", 2971 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2972 "PerPkg": "1", 2973 "UMask": "0x7", 2974 "Unit": "iMC" 2975 }, 2976 { 2977 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 2978 "Counter": "0,1,2,3", 2979 "EventCode": "0xB9", 2980 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 2981 "PerPkg": "1", 2982 "UMask": "0x8", 2983 "Unit": "iMC" 2984 }, 2985 { 2986 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2987 "Counter": "0,1,2,3", 2988 "EventCode": "0xB9", 2989 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2990 "PerPkg": "1", 2991 "UMask": "0x9", 2992 "Unit": "iMC" 2993 }, 2994 { 2995 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2996 "Counter": "0,1,2,3", 2997 "EventCode": "0xB9", 2998 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 2999 "PerPkg": "1", 3000 "UMask": "0xA", 3001 "Unit": "iMC" 3002 }, 3003 { 3004 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 3005 "Counter": "0,1,2,3", 3006 "EventCode": "0xB9", 3007 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 3008 "PerPkg": "1", 3009 "UMask": "0xB", 3010 "Unit": "iMC" 3011 }, 3012 { 3013 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 3014 "Counter": "0,1,2,3", 3015 "EventCode": "0xB9", 3016 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 3017 "PerPkg": "1", 3018 "UMask": "0xC", 3019 "Unit": "iMC" 3020 }, 3021 { 3022 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 3023 "Counter": "0,1,2,3", 3024 "EventCode": "0xB9", 3025 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 3026 "PerPkg": "1", 3027 "UMask": "0xD", 3028 "Unit": "iMC" 3029 }, 3030 { 3031 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 3032 "Counter": "0,1,2,3", 3033 "EventCode": "0xB9", 3034 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 3035 "PerPkg": "1", 3036 "UMask": "0xE", 3037 "Unit": "iMC" 3038 }, 3039 { 3040 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 3041 "Counter": "0,1,2,3", 3042 "EventCode": "0xB9", 3043 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 3044 "PerPkg": "1", 3045 "UMask": "0xF", 3046 "Unit": "iMC" 3047 }, 3048 { 3049 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 3050 "Counter": "0,1,2,3", 3051 "EventCode": "0xB9", 3052 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 3053 "PerPkg": "1", 3054 "UMask": "0x10", 3055 "Unit": "iMC" 3056 }, 3057 { 3058 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 3059 "Counter": "0,1,2,3", 3060 "EventCode": "0xB9", 3061 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 3062 "PerPkg": "1", 3063 "UMask": "0x11", 3064 "Unit": "iMC" 3065 }, 3066 { 3067 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 3068 "Counter": "0,1,2,3", 3069 "EventCode": "0xB9", 3070 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 3071 "PerPkg": "1", 3072 "UMask": "0x12", 3073 "Unit": "iMC" 3074 }, 3075 { 3076 "BriefDescription": "WR_CAS Access to Rank 1; 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Bank 7", 4097 "Counter": "0,1,2,3", 4098 "EventCode": "0xBF", 4099 "EventName": "UNC_M_WR_CAS_RANK7.BANK7", 4100 "PerPkg": "1", 4101 "UMask": "0x7", 4102 "Unit": "iMC" 4103 }, 4104 { 4105 "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", 4106 "Counter": "0,1,2,3", 4107 "EventCode": "0xBF", 4108 "EventName": "UNC_M_WR_CAS_RANK7.BANK8", 4109 "PerPkg": "1", 4110 "UMask": "0x8", 4111 "Unit": "iMC" 4112 }, 4113 { 4114 "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", 4115 "Counter": "0,1,2,3", 4116 "EventCode": "0xBF", 4117 "EventName": "UNC_M_WR_CAS_RANK7.BANK9", 4118 "PerPkg": "1", 4119 "UMask": "0x9", 4120 "Unit": "iMC" 4121 }, 4122 { 4123 "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", 4124 "Counter": "0,1,2,3", 4125 "EventCode": "0xBF", 4126 "EventName": "UNC_M_WR_CAS_RANK7.BANK10", 4127 "PerPkg": "1", 4128 "UMask": "0xA", 4129 "Unit": "iMC" 4130 }, 4131 { 4132 "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", 4133 "Counter": "0,1,2,3", 4134 "EventCode": "0xBF", 4135 "EventName": "UNC_M_WR_CAS_RANK7.BANK11", 4136 "PerPkg": "1", 4137 "UMask": "0xB", 4138 "Unit": "iMC" 4139 }, 4140 { 4141 "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", 4142 "Counter": "0,1,2,3", 4143 "EventCode": "0xBF", 4144 "EventName": "UNC_M_WR_CAS_RANK7.BANK12", 4145 "PerPkg": "1", 4146 "UMask": "0xC", 4147 "Unit": "iMC" 4148 }, 4149 { 4150 "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", 4151 "Counter": "0,1,2,3", 4152 "EventCode": "0xBF", 4153 "EventName": "UNC_M_WR_CAS_RANK7.BANK13", 4154 "PerPkg": "1", 4155 "UMask": "0xD", 4156 "Unit": "iMC" 4157 }, 4158 { 4159 "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", 4160 "Counter": "0,1,2,3", 4161 "EventCode": "0xBF", 4162 "EventName": "UNC_M_WR_CAS_RANK7.BANK14", 4163 "PerPkg": "1", 4164 "UMask": "0xE", 4165 "Unit": "iMC" 4166 }, 4167 { 4168 "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", 4169 "Counter": "0,1,2,3", 4170 "EventCode": "0xBF", 4171 "EventName": "UNC_M_WR_CAS_RANK7.BANK15", 4172 "PerPkg": "1", 4173 "UMask": "0xF", 4174 "Unit": "iMC" 4175 }, 4176 { 4177 "BriefDescription": "WR_CAS Access to Rank 7; All Banks", 4178 "Counter": "0,1,2,3", 4179 "EventCode": "0xBF", 4180 "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", 4181 "PerPkg": "1", 4182 "UMask": "0x10", 4183 "Unit": "iMC" 4184 }, 4185 { 4186 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 4187 "Counter": "0,1,2,3", 4188 "EventCode": "0xBF", 4189 "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", 4190 "PerPkg": "1", 4191 "UMask": "0x11", 4192 "Unit": "iMC" 4193 }, 4194 { 4195 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 4196 "Counter": "0,1,2,3", 4197 "EventCode": "0xBF", 4198 "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", 4199 "PerPkg": "1", 4200 "UMask": "0x12", 4201 "Unit": "iMC" 4202 }, 4203 { 4204 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 4205 "Counter": "0,1,2,3", 4206 "EventCode": "0xBF", 4207 "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", 4208 "PerPkg": "1", 4209 "UMask": "0x13", 4210 "Unit": "iMC" 4211 }, 4212 { 4213 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 4214 "Counter": "0,1,2,3", 4215 "EventCode": "0xBF", 4216 "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", 4217 "PerPkg": "1", 4218 "UMask": "0x14", 4219 "Unit": "iMC" 4220 }, 4221 { 4222 "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter", 4223 "Counter": "FIXED", 4224 "EventCode": "0xff", 4225 "EventName": "UNC_M_CLOCKTICKS_F", 4226 "PerPkg": "1", 4227 "Unit": "iMC" 4228 }, 4229 { 4230 "BriefDescription": "PMM Occupancy", 4231 "Counter": "0,1,2,3", 4232 "EventCode": "0xE0", 4233 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", 4234 "PerPkg": "1", 4235 "UMask": "0x4", 4236 "Unit": "iMC" 4237 }, 4238 { 4239 "BriefDescription": "PMM Read Queue Cycles Not Empty", 4240 "Counter": "0,1,2,3", 4241 "EventCode": "0xE1", 4242 "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", 4243 "PerPkg": "1", 4244 "Unit": "iMC" 4245 }, 4246 { 4247 "BriefDescription": "PMM Read Queue Cycles Full", 4248 "Counter": "0,1,2,3", 4249 "EventCode": "0xE2", 4250 "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", 4251 "PerPkg": "1", 4252 "Unit": "iMC" 4253 }, 4254 { 4255 "BriefDescription": "RPQ GNTs", 4256 "Counter": "0,1,2,3", 4257 "EventCode": "0xEA", 4258 "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", 4259 "PerPkg": "1", 4260 "UMask": "0x10", 4261 "Unit": "iMC" 4262 }, 4263 { 4264 "BriefDescription": "Underfill GNTs", 4265 "Counter": "0,1,2,3", 4266 "EventCode": "0xEA", 4267 "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", 4268 "PerPkg": "1", 4269 "UMask": "0x20", 4270 "Unit": "iMC" 4271 }, 4272 { 4273 "BriefDescription": "Misc GNTs", 4274 "Counter": "0,1,2,3", 4275 "EventCode": "0xEA", 4276 "EventName": "UNC_M_PMM_CMD1.MISC_GNT", 4277 "PerPkg": "1", 4278 "UMask": "0x40", 4279 "Unit": "iMC" 4280 }, 4281 { 4282 "BriefDescription": "Misc Commands (error, flow ACKs)", 4283 "Counter": "0,1,2,3", 4284 "EventCode": "0xEA", 4285 "EventName": "UNC_M_PMM_CMD1.MISC", 4286 "PerPkg": "1", 4287 "UMask": "0x80", 4288 "Unit": "iMC" 4289 }, 4290 { 4291 "BriefDescription": "Opportunistic Reads", 4292 "Counter": "0,1,2,3", 4293 "EventCode": "0xEB", 4294 "EventName": "UNC_M_PMM_CMD2.OPP_RD", 4295 "PerPkg": "1", 4296 "UMask": "0x1", 4297 "Unit": "iMC" 4298 }, 4299 { 4300 "BriefDescription": "Expected No data packet (ERID matched NDP encoding)", 4301 "Counter": "0,1,2,3", 4302 "EventCode": "0xEB", 4303 "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", 4304 "PerPkg": "1", 4305 "UMask": "0x2", 4306 "Unit": "iMC" 4307 }, 4308 { 4309 "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)", 4310 "Counter": "0,1,2,3", 4311 "EventCode": "0xEB", 4312 "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", 4313 "PerPkg": "1", 4314 "UMask": "0x4", 4315 "Unit": "iMC" 4316 }, 4317 { 4318 "BriefDescription": "Read Requests - Slot 0", 4319 "Counter": "0,1,2,3", 4320 "EventCode": "0xEB", 4321 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", 4322 "PerPkg": "1", 4323 "UMask": "0x8", 4324 "Unit": "iMC" 4325 }, 4326 { 4327 "BriefDescription": "Read Requests - Slot 1", 4328 "Counter": "0,1,2,3", 4329 "EventCode": "0xEB", 4330 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", 4331 "PerPkg": "1", 4332 "UMask": "0x10", 4333 "Unit": "iMC" 4334 }, 4335 { 4336 "BriefDescription": "PMM ECC Errors", 4337 "Counter": "0,1,2,3", 4338 "EventCode": "0xEB", 4339 "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", 4340 "PerPkg": "1", 4341 "UMask": "0x20", 4342 "Unit": "iMC" 4343 }, 4344 { 4345 "BriefDescription": "PMM ERID detectable parity error", 4346 "Counter": "0,1,2,3", 4347 "EventCode": "0xEB", 4348 "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", 4349 "PerPkg": "1", 4350 "UMask": "0x40", 4351 "Unit": "iMC" 4352 }, 4353 { 4354 "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode", 4355 "Counter": "0,1,2,3", 4356 "EventCode": "0xEC", 4357 "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC", 4358 "PerPkg": "1", 4359 "UMask": "0x1", 4360 "Unit": "iMC" 4361 }, 4362 { 4363 "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode", 4364 "Counter": "0,1,2,3", 4365 "EventCode": "0xEC", 4366 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC", 4367 "PerPkg": "1", 4368 "UMask": "0x4", 4369 "Unit": "iMC" 4370 }, 4371 { 4372 "BriefDescription": "PMM Major Mode", 4373 "Counter": "0,1,2,3", 4374 "EventCode": "0xEC", 4375 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER", 4376 "PerPkg": "1", 4377 "UMask": "0x20", 4378 "Unit": "iMC" 4379 }, 4380 { 4381 "BriefDescription": "PMM Major Mode", 4382 "Counter": "0,1,2,3", 4383 "EventCode": "0xEC", 4384 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT", 4385 "PerPkg": "1", 4386 "UMask": "0x40", 4387 "Unit": "iMC" 4388 }, 4389 { 4390 "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC", 4391 "Counter": "0,1,2,3", 4392 "EventCode": "0xED", 4393 "EventName": "UNC_M_MAJMODE2.DRAM_CYC", 4394 "PerPkg": "1", 4395 "UMask": "0x2", 4396 "Unit": "iMC" 4397 }, 4398 { 4399 "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER", 4400 "Counter": "0,1,2,3", 4401 "EventCode": "0xED", 4402 "EventName": "UNC_M_MAJMODE2.DRAM_ENTER", 4403 "PerPkg": "1", 4404 "UMask": "0x8", 4405 "Unit": "iMC" 4406 }, 4407 { 4408 "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER", 4409 "Counter": "0,1,2,3", 4410 "EventCode": "0xED", 4411 "EventName": "UNC_M_MAJMODE2.PMM_ENTER", 4412 "PerPkg": "1", 4413 "UMask": "0x4", 4414 "Unit": "iMC" 4415 }, 4416 { 4417 "BriefDescription": "PMM Write Queue Cycles Full", 4418 "Counter": "0,1,2,3", 4419 "EventCode": "0xE6", 4420 "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", 4421 "PerPkg": "1", 4422 "Unit": "iMC" 4423 }, 4424 { 4425 "BriefDescription": "PMM Write Queue Cycles Not Empty", 4426 "Counter": "0,1,2,3", 4427 "EventCode": "0xE5", 4428 "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", 4429 "PerPkg": "1", 4430 "Unit": "iMC" 4431 }, 4432 { 4433 "BriefDescription": "PMM Occupancy", 4434 "Counter": "0,1,2,3", 4435 "EventCode": "0xE4", 4436 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", 4437 "PerPkg": "1", 4438 "UMask": "0x2", 4439 "Unit": "iMC" 4440 }, 4441 { 4442 "BriefDescription": "PMM Occupancy", 4443 "Counter": "0,1,2,3", 4444 "EventCode": "0xE4", 4445 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", 4446 "PerPkg": "1", 4447 "UMask": "0x4", 4448 "Unit": "iMC" 4449 }, 4450 { 4451 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT", 4452 "Counter": "0,1,2,3", 4453 "EventCode": "0xE8", 4454 "EventName": "UNC_M_PMM_WPQ_PCOMMIT", 4455 "PerPkg": "1", 4456 "Unit": "iMC" 4457 }, 4458 { 4459 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC", 4460 "Counter": "0,1,2,3", 4461 "EventCode": "0xE9", 4462 "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC", 4463 "PerPkg": "1", 4464 "Unit": "iMC" 4465 }, 4466 { 4467 "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode", 4468 "Counter": "0,1,2,3", 4469 "EventCode": "0xEC", 4470 "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC", 4471 "PerPkg": "1", 4472 "UMask": "0x2", 4473 "Unit": "iMC" 4474 }, 4475 { 4476 "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC", 4477 "Counter": "0,1,2,3", 4478 "EventCode": "0xED", 4479 "EventName": "UNC_M_MAJMODE2.PMM_CYC", 4480 "PerPkg": "1", 4481 "UMask": "0x1", 4482 "Unit": "iMC" 4483 }, 4484 { 4485 "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", 4486 "Counter": "0,1,2,3", 4487 "EventCode": "0xDD", 4488 "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", 4489 "PerPkg": "1", 4490 "UMask": "0x10", 4491 "Unit": "iMC" 4492 }, 4493 { 4494 "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", 4495 "Counter": "0,1,2,3", 4496 "EventCode": "0xDD", 4497 "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", 4498 "PerPkg": "1", 4499 "UMask": "0x20", 4500 "Unit": "iMC" 4501 }, 4502 { 4503 "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", 4504 "Counter": "0,1,2,3", 4505 "EventCode": "0xDD", 4506 "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", 4507 "PerPkg": "1", 4508 "UMask": "0x40", 4509 "Unit": "iMC" 4510 }, 4511 { 4512 "BriefDescription": "Scoreboard Inserts; Persistent Mem writes", 4513 "Counter": "0,1,2,3", 4514 "EventCode": "0xD6", 4515 "EventName": "UNC_M_SB_INSERTS.PMM_WRS", 4516 "PerPkg": "1", 4517 "UMask": "0x08", 4518 "Unit": "iMC" 4519 }, 4520 { 4521 "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes", 4522 "Counter": "0,1,2,3", 4523 "EventCode": "0xD5", 4524 "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", 4525 "PerPkg": "1", 4526 "UMask": "0x08", 4527 "Unit": "iMC" 4528 }, 4529 { 4530 "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads", 4531 "Counter": "0,1,2,3", 4532 "EventCode": "0xD5", 4533 "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", 4534 "PerPkg": "1", 4535 "UMask": "0x04", 4536 "Unit": "iMC" 4537 }, 4538 { 4539 "BriefDescription": "Scoreboard Inserts; Persistent Mem reads", 4540 "Counter": "0,1,2,3", 4541 "EventCode": "0xD6", 4542 "EventName": "UNC_M_SB_INSERTS.PMM_RDS", 4543 "PerPkg": "1", 4544 "UMask": "0x04", 4545 "Unit": "iMC" 4546 } 4547] 4548