1[
2    {
3        "BriefDescription": "L1D data line replacements",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x51",
7        "EventName": "L1D.REPLACEMENT",
8        "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
9        "SampleAfterValue": "2000003",
10        "UMask": "0x1"
11    },
12    {
13        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "CounterMask": "1",
17        "EventCode": "0x48",
18        "EventName": "L1D_PEND_MISS.FB_FULL",
19        "SampleAfterValue": "2000003",
20        "UMask": "0x2"
21    },
22    {
23        "BriefDescription": "L1D miss outstanding duration in cycles",
24        "Counter": "2",
25        "CounterHTOff": "2",
26        "EventCode": "0x48",
27        "EventName": "L1D_PEND_MISS.PENDING",
28        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
29        "SampleAfterValue": "2000003",
30        "UMask": "0x1"
31    },
32    {
33        "BriefDescription": "Cycles with L1D load Misses outstanding.",
34        "Counter": "2",
35        "CounterHTOff": "2",
36        "CounterMask": "1",
37        "EventCode": "0x48",
38        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
39        "SampleAfterValue": "2000003",
40        "UMask": "0x1"
41    },
42    {
43        "AnyThread": "1",
44        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
45        "Counter": "2",
46        "CounterHTOff": "2",
47        "CounterMask": "1",
48        "EventCode": "0x48",
49        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
50        "SampleAfterValue": "2000003",
51        "UMask": "0x1"
52    },
53    {
54        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
55        "Counter": "0,1,2,3",
56        "CounterHTOff": "0,1,2,3,4,5,6,7",
57        "EventCode": "0x48",
58        "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
59        "SampleAfterValue": "2000003",
60        "UMask": "0x2"
61    },
62    {
63        "BriefDescription": "Not rejected writebacks that hit L2 cache",
64        "Counter": "0,1,2,3",
65        "CounterHTOff": "0,1,2,3,4,5,6,7",
66        "EventCode": "0x27",
67        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
68        "PublicDescription": "Not rejected writebacks that hit L2 cache.",
69        "SampleAfterValue": "200003",
70        "UMask": "0x50"
71    },
72    {
73        "BriefDescription": "L2 cache lines filling L2",
74        "Counter": "0,1,2,3",
75        "CounterHTOff": "0,1,2,3,4,5,6,7",
76        "EventCode": "0xF1",
77        "EventName": "L2_LINES_IN.ALL",
78        "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
79        "SampleAfterValue": "100003",
80        "UMask": "0x7"
81    },
82    {
83        "BriefDescription": "L2 cache lines in E state filling L2",
84        "Counter": "0,1,2,3",
85        "CounterHTOff": "0,1,2,3,4,5,6,7",
86        "EventCode": "0xF1",
87        "EventName": "L2_LINES_IN.E",
88        "PublicDescription": "L2 cache lines in E state filling L2.",
89        "SampleAfterValue": "100003",
90        "UMask": "0x4"
91    },
92    {
93        "BriefDescription": "L2 cache lines in I state filling L2",
94        "Counter": "0,1,2,3",
95        "CounterHTOff": "0,1,2,3,4,5,6,7",
96        "EventCode": "0xF1",
97        "EventName": "L2_LINES_IN.I",
98        "PublicDescription": "L2 cache lines in I state filling L2.",
99        "SampleAfterValue": "100003",
100        "UMask": "0x1"
101    },
102    {
103        "BriefDescription": "L2 cache lines in S state filling L2",
104        "Counter": "0,1,2,3",
105        "CounterHTOff": "0,1,2,3,4,5,6,7",
106        "EventCode": "0xF1",
107        "EventName": "L2_LINES_IN.S",
108        "PublicDescription": "L2 cache lines in S state filling L2.",
109        "SampleAfterValue": "100003",
110        "UMask": "0x2"
111    },
112    {
113        "BriefDescription": "Clean L2 cache lines evicted by demand",
114        "Counter": "0,1,2,3",
115        "CounterHTOff": "0,1,2,3,4,5,6,7",
116        "EventCode": "0xF2",
117        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
118        "PublicDescription": "Clean L2 cache lines evicted by demand.",
119        "SampleAfterValue": "100003",
120        "UMask": "0x5"
121    },
122    {
123        "BriefDescription": "Dirty L2 cache lines evicted by demand",
124        "Counter": "0,1,2,3",
125        "CounterHTOff": "0,1,2,3,4,5,6,7",
126        "EventCode": "0xF2",
127        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
128        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
129        "SampleAfterValue": "100003",
130        "UMask": "0x6"
131    },
132    {
133        "BriefDescription": "L2 code requests",
134        "Counter": "0,1,2,3",
135        "CounterHTOff": "0,1,2,3,4,5,6,7",
136        "EventCode": "0x24",
137        "EventName": "L2_RQSTS.ALL_CODE_RD",
138        "PublicDescription": "Counts all L2 code requests.",
139        "SampleAfterValue": "200003",
140        "UMask": "0xe4"
141    },
142    {
143        "BriefDescription": "Demand Data Read requests",
144        "Counter": "0,1,2,3",
145        "CounterHTOff": "0,1,2,3,4,5,6,7",
146        "Errata": "HSD78, HSM80",
147        "EventCode": "0x24",
148        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
149        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
150        "SampleAfterValue": "200003",
151        "UMask": "0xe1"
152    },
153    {
154        "BriefDescription": "Demand requests that miss L2 cache",
155        "Counter": "0,1,2,3",
156        "CounterHTOff": "0,1,2,3,4,5,6,7",
157        "Errata": "HSD78, HSM80",
158        "EventCode": "0x24",
159        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
160        "PublicDescription": "Demand requests that miss L2 cache.",
161        "SampleAfterValue": "200003",
162        "UMask": "0x27"
163    },
164    {
165        "BriefDescription": "Demand requests to L2 cache",
166        "Counter": "0,1,2,3",
167        "CounterHTOff": "0,1,2,3,4,5,6,7",
168        "Errata": "HSD78, HSM80",
169        "EventCode": "0x24",
170        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
171        "PublicDescription": "Demand requests to L2 cache.",
172        "SampleAfterValue": "200003",
173        "UMask": "0xe7"
174    },
175    {
176        "BriefDescription": "Requests from L2 hardware prefetchers",
177        "Counter": "0,1,2,3",
178        "CounterHTOff": "0,1,2,3,4,5,6,7",
179        "EventCode": "0x24",
180        "EventName": "L2_RQSTS.ALL_PF",
181        "PublicDescription": "Counts all L2 HW prefetcher requests.",
182        "SampleAfterValue": "200003",
183        "UMask": "0xf8"
184    },
185    {
186        "BriefDescription": "RFO requests to L2 cache",
187        "Counter": "0,1,2,3",
188        "CounterHTOff": "0,1,2,3,4,5,6,7",
189        "EventCode": "0x24",
190        "EventName": "L2_RQSTS.ALL_RFO",
191        "PublicDescription": "Counts all L2 store RFO requests.",
192        "SampleAfterValue": "200003",
193        "UMask": "0xe2"
194    },
195    {
196        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
197        "Counter": "0,1,2,3",
198        "CounterHTOff": "0,1,2,3,4,5,6,7",
199        "EventCode": "0x24",
200        "EventName": "L2_RQSTS.CODE_RD_HIT",
201        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
202        "SampleAfterValue": "200003",
203        "UMask": "0xc4"
204    },
205    {
206        "BriefDescription": "L2 cache misses when fetching instructions",
207        "Counter": "0,1,2,3",
208        "CounterHTOff": "0,1,2,3,4,5,6,7",
209        "EventCode": "0x24",
210        "EventName": "L2_RQSTS.CODE_RD_MISS",
211        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
212        "SampleAfterValue": "200003",
213        "UMask": "0x24"
214    },
215    {
216        "BriefDescription": "Demand Data Read requests that hit L2 cache",
217        "Counter": "0,1,2,3",
218        "CounterHTOff": "0,1,2,3,4,5,6,7",
219        "Errata": "HSD78, HSM80",
220        "EventCode": "0x24",
221        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
222        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
223        "SampleAfterValue": "200003",
224        "UMask": "0xc1"
225    },
226    {
227        "BriefDescription": "Demand Data Read miss L2, no rejects",
228        "Counter": "0,1,2,3",
229        "CounterHTOff": "0,1,2,3,4,5,6,7",
230        "Errata": "HSD78, HSM80",
231        "EventCode": "0x24",
232        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
233        "PublicDescription": "Demand data read requests that missed L2, no rejects.",
234        "SampleAfterValue": "200003",
235        "UMask": "0x21"
236    },
237    {
238        "BriefDescription": "L2 prefetch requests that hit L2 cache",
239        "Counter": "0,1,2,3",
240        "CounterHTOff": "0,1,2,3,4,5,6,7",
241        "EventCode": "0x24",
242        "EventName": "L2_RQSTS.L2_PF_HIT",
243        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
244        "SampleAfterValue": "200003",
245        "UMask": "0xd0"
246    },
247    {
248        "BriefDescription": "L2 prefetch requests that miss L2 cache",
249        "Counter": "0,1,2,3",
250        "CounterHTOff": "0,1,2,3,4,5,6,7",
251        "EventCode": "0x24",
252        "EventName": "L2_RQSTS.L2_PF_MISS",
253        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
254        "SampleAfterValue": "200003",
255        "UMask": "0x30"
256    },
257    {
258        "BriefDescription": "All requests that miss L2 cache",
259        "Counter": "0,1,2,3",
260        "CounterHTOff": "0,1,2,3,4,5,6,7",
261        "Errata": "HSD78, HSM80",
262        "EventCode": "0x24",
263        "EventName": "L2_RQSTS.MISS",
264        "PublicDescription": "All requests that missed L2.",
265        "SampleAfterValue": "200003",
266        "UMask": "0x3f"
267    },
268    {
269        "BriefDescription": "All L2 requests",
270        "Counter": "0,1,2,3",
271        "CounterHTOff": "0,1,2,3,4,5,6,7",
272        "Errata": "HSD78, HSM80",
273        "EventCode": "0x24",
274        "EventName": "L2_RQSTS.REFERENCES",
275        "PublicDescription": "All requests to L2 cache.",
276        "SampleAfterValue": "200003",
277        "UMask": "0xff"
278    },
279    {
280        "BriefDescription": "RFO requests that hit L2 cache",
281        "Counter": "0,1,2,3",
282        "CounterHTOff": "0,1,2,3,4,5,6,7",
283        "EventCode": "0x24",
284        "EventName": "L2_RQSTS.RFO_HIT",
285        "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
286        "SampleAfterValue": "200003",
287        "UMask": "0xc2"
288    },
289    {
290        "BriefDescription": "RFO requests that miss L2 cache",
291        "Counter": "0,1,2,3",
292        "CounterHTOff": "0,1,2,3,4,5,6,7",
293        "EventCode": "0x24",
294        "EventName": "L2_RQSTS.RFO_MISS",
295        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
296        "SampleAfterValue": "200003",
297        "UMask": "0x22"
298    },
299    {
300        "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
301        "Counter": "0,1,2,3",
302        "CounterHTOff": "0,1,2,3,4,5,6,7",
303        "EventCode": "0xf0",
304        "EventName": "L2_TRANS.ALL_PF",
305        "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
306        "SampleAfterValue": "200003",
307        "UMask": "0x8"
308    },
309    {
310        "BriefDescription": "Transactions accessing L2 pipe",
311        "Counter": "0,1,2,3",
312        "CounterHTOff": "0,1,2,3,4,5,6,7",
313        "EventCode": "0xf0",
314        "EventName": "L2_TRANS.ALL_REQUESTS",
315        "PublicDescription": "Transactions accessing L2 pipe.",
316        "SampleAfterValue": "200003",
317        "UMask": "0x80"
318    },
319    {
320        "BriefDescription": "L2 cache accesses when fetching instructions",
321        "Counter": "0,1,2,3",
322        "CounterHTOff": "0,1,2,3,4,5,6,7",
323        "EventCode": "0xf0",
324        "EventName": "L2_TRANS.CODE_RD",
325        "PublicDescription": "L2 cache accesses when fetching instructions.",
326        "SampleAfterValue": "200003",
327        "UMask": "0x4"
328    },
329    {
330        "BriefDescription": "Demand Data Read requests that access L2 cache",
331        "Counter": "0,1,2,3",
332        "CounterHTOff": "0,1,2,3,4,5,6,7",
333        "EventCode": "0xf0",
334        "EventName": "L2_TRANS.DEMAND_DATA_RD",
335        "PublicDescription": "Demand data read requests that access L2 cache.",
336        "SampleAfterValue": "200003",
337        "UMask": "0x1"
338    },
339    {
340        "BriefDescription": "L1D writebacks that access L2 cache",
341        "Counter": "0,1,2,3",
342        "CounterHTOff": "0,1,2,3,4,5,6,7",
343        "EventCode": "0xf0",
344        "EventName": "L2_TRANS.L1D_WB",
345        "PublicDescription": "L1D writebacks that access L2 cache.",
346        "SampleAfterValue": "200003",
347        "UMask": "0x10"
348    },
349    {
350        "BriefDescription": "L2 fill requests that access L2 cache",
351        "Counter": "0,1,2,3",
352        "CounterHTOff": "0,1,2,3,4,5,6,7",
353        "EventCode": "0xf0",
354        "EventName": "L2_TRANS.L2_FILL",
355        "PublicDescription": "L2 fill requests that access L2 cache.",
356        "SampleAfterValue": "200003",
357        "UMask": "0x20"
358    },
359    {
360        "BriefDescription": "L2 writebacks that access L2 cache",
361        "Counter": "0,1,2,3",
362        "CounterHTOff": "0,1,2,3,4,5,6,7",
363        "EventCode": "0xf0",
364        "EventName": "L2_TRANS.L2_WB",
365        "PublicDescription": "L2 writebacks that access L2 cache.",
366        "SampleAfterValue": "200003",
367        "UMask": "0x40"
368    },
369    {
370        "BriefDescription": "RFO requests that access L2 cache",
371        "Counter": "0,1,2,3",
372        "CounterHTOff": "0,1,2,3,4,5,6,7",
373        "EventCode": "0xf0",
374        "EventName": "L2_TRANS.RFO",
375        "PublicDescription": "RFO requests that access L2 cache.",
376        "SampleAfterValue": "200003",
377        "UMask": "0x2"
378    },
379    {
380        "BriefDescription": "Cycles when L1D is locked",
381        "Counter": "0,1,2,3",
382        "CounterHTOff": "0,1,2,3,4,5,6,7",
383        "EventCode": "0x63",
384        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
385        "PublicDescription": "Cycles in which the L1D is locked.",
386        "SampleAfterValue": "2000003",
387        "UMask": "0x2"
388    },
389    {
390        "BriefDescription": "Core-originated cacheable demand requests missed L3",
391        "Counter": "0,1,2,3",
392        "CounterHTOff": "0,1,2,3,4,5,6,7",
393        "EventCode": "0x2E",
394        "EventName": "LONGEST_LAT_CACHE.MISS",
395        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
396        "SampleAfterValue": "100003",
397        "UMask": "0x41"
398    },
399    {
400        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
401        "Counter": "0,1,2,3",
402        "CounterHTOff": "0,1,2,3,4,5,6,7",
403        "EventCode": "0x2E",
404        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
405        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
406        "SampleAfterValue": "100003",
407        "UMask": "0x4f"
408    },
409    {
410        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
411        "Counter": "0,1,2,3",
412        "CounterHTOff": "0,1,2,3",
413        "Data_LA": "1",
414        "Errata": "HSD29, HSD25, HSM26, HSM30",
415        "EventCode": "0xD2",
416        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
417        "PEBS": "1",
418        "SampleAfterValue": "20011",
419        "UMask": "0x2"
420    },
421    {
422        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
423        "Counter": "0,1,2,3",
424        "CounterHTOff": "0,1,2,3",
425        "Data_LA": "1",
426        "Errata": "HSD29, HSD25, HSM26, HSM30",
427        "EventCode": "0xD2",
428        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
429        "PEBS": "1",
430        "SampleAfterValue": "20011",
431        "UMask": "0x4"
432    },
433    {
434        "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
435        "Counter": "0,1,2,3",
436        "CounterHTOff": "0,1,2,3",
437        "Data_LA": "1",
438        "Errata": "HSD29, HSD25, HSM26, HSM30",
439        "EventCode": "0xD2",
440        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
441        "PEBS": "1",
442        "SampleAfterValue": "20011",
443        "UMask": "0x1"
444    },
445    {
446        "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
447        "Counter": "0,1,2,3",
448        "CounterHTOff": "0,1,2,3",
449        "Data_LA": "1",
450        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
451        "EventCode": "0xD2",
452        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
453        "PEBS": "1",
454        "SampleAfterValue": "100003",
455        "UMask": "0x8"
456    },
457    {
458        "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
459        "Counter": "0,1,2,3",
460        "CounterHTOff": "0,1,2,3",
461        "Data_LA": "1",
462        "Errata": "HSD74, HSD29, HSD25, HSM30",
463        "EventCode": "0xD3",
464        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
465        "PEBS": "1",
466        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
467        "SampleAfterValue": "100003",
468        "UMask": "0x1"
469    },
470    {
471        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
472        "Counter": "0,1,2,3",
473        "CounterHTOff": "0,1,2,3",
474        "Data_LA": "1",
475        "Errata": "HSM30",
476        "EventCode": "0xD1",
477        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
478        "PEBS": "1",
479        "SampleAfterValue": "100003",
480        "UMask": "0x40"
481    },
482    {
483        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
484        "Counter": "0,1,2,3",
485        "CounterHTOff": "0,1,2,3",
486        "Data_LA": "1",
487        "Errata": "HSD29, HSM30",
488        "EventCode": "0xD1",
489        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
490        "PEBS": "1",
491        "SampleAfterValue": "2000003",
492        "UMask": "0x1"
493    },
494    {
495        "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
496        "Counter": "0,1,2,3",
497        "CounterHTOff": "0,1,2,3",
498        "Data_LA": "1",
499        "Errata": "HSM30",
500        "EventCode": "0xD1",
501        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
502        "PEBS": "1",
503        "PublicDescription": "Retired load uops missed L1 cache as data sources.",
504        "SampleAfterValue": "100003",
505        "UMask": "0x8"
506    },
507    {
508        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
509        "Counter": "0,1,2,3",
510        "CounterHTOff": "0,1,2,3",
511        "Data_LA": "1",
512        "Errata": "HSD76, HSD29, HSM30",
513        "EventCode": "0xD1",
514        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
515        "PEBS": "1",
516        "SampleAfterValue": "100003",
517        "UMask": "0x2"
518    },
519    {
520        "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
521        "Counter": "0,1,2,3",
522        "CounterHTOff": "0,1,2,3",
523        "Data_LA": "1",
524        "Errata": "HSD29, HSM30",
525        "EventCode": "0xD1",
526        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
527        "PEBS": "1",
528        "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
529        "SampleAfterValue": "50021",
530        "UMask": "0x10"
531    },
532    {
533        "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
534        "Counter": "0,1,2,3",
535        "CounterHTOff": "0,1,2,3",
536        "Data_LA": "1",
537        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
538        "EventCode": "0xD1",
539        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
540        "PEBS": "1",
541        "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
542        "SampleAfterValue": "50021",
543        "UMask": "0x4"
544    },
545    {
546        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
547        "Counter": "0,1,2,3",
548        "CounterHTOff": "0,1,2,3",
549        "Data_LA": "1",
550        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
551        "EventCode": "0xD1",
552        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
553        "PEBS": "1",
554        "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
555        "SampleAfterValue": "100003",
556        "UMask": "0x20"
557    },
558    {
559        "BriefDescription": "Retired load uops.",
560        "Counter": "0,1,2,3",
561        "CounterHTOff": "0,1,2,3",
562        "Data_LA": "1",
563        "Errata": "HSD29, HSM30",
564        "EventCode": "0xD0",
565        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
566        "PEBS": "1",
567        "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
568        "SampleAfterValue": "2000003",
569        "UMask": "0x81"
570    },
571    {
572        "BriefDescription": "Retired store uops.",
573        "Counter": "0,1,2,3",
574        "CounterHTOff": "0,1,2,3",
575        "Data_LA": "1",
576        "Errata": "HSD29, HSM30",
577        "EventCode": "0xD0",
578        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
579        "L1_Hit_Indication": "1",
580        "PEBS": "1",
581        "PublicDescription": "Counts all retired store uops.",
582        "SampleAfterValue": "2000003",
583        "UMask": "0x82"
584    },
585    {
586        "BriefDescription": "Retired load uops with locked access.",
587        "Counter": "0,1,2,3",
588        "CounterHTOff": "0,1,2,3",
589        "Data_LA": "1",
590        "Errata": "HSD76, HSD29, HSM30",
591        "EventCode": "0xD0",
592        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
593        "PEBS": "1",
594        "SampleAfterValue": "100003",
595        "UMask": "0x21"
596    },
597    {
598        "BriefDescription": "Retired load uops that split across a cacheline boundary.",
599        "Counter": "0,1,2,3",
600        "CounterHTOff": "0,1,2,3",
601        "Data_LA": "1",
602        "Errata": "HSD29, HSM30",
603        "EventCode": "0xD0",
604        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
605        "PEBS": "1",
606        "SampleAfterValue": "100003",
607        "UMask": "0x41"
608    },
609    {
610        "BriefDescription": "Retired store uops that split across a cacheline boundary.",
611        "Counter": "0,1,2,3",
612        "CounterHTOff": "0,1,2,3",
613        "Data_LA": "1",
614        "Errata": "HSD29, HSM30",
615        "EventCode": "0xD0",
616        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
617        "L1_Hit_Indication": "1",
618        "PEBS": "1",
619        "SampleAfterValue": "100003",
620        "UMask": "0x42"
621    },
622    {
623        "BriefDescription": "Retired load uops that miss the STLB.",
624        "Counter": "0,1,2,3",
625        "CounterHTOff": "0,1,2,3",
626        "Data_LA": "1",
627        "Errata": "HSD29, HSM30",
628        "EventCode": "0xD0",
629        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
630        "PEBS": "1",
631        "SampleAfterValue": "100003",
632        "UMask": "0x11"
633    },
634    {
635        "BriefDescription": "Retired store uops that miss the STLB.",
636        "Counter": "0,1,2,3",
637        "CounterHTOff": "0,1,2,3",
638        "Data_LA": "1",
639        "Errata": "HSD29, HSM30",
640        "EventCode": "0xD0",
641        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
642        "L1_Hit_Indication": "1",
643        "PEBS": "1",
644        "SampleAfterValue": "100003",
645        "UMask": "0x12"
646    },
647    {
648        "BriefDescription": "Demand and prefetch data reads",
649        "Counter": "0,1,2,3",
650        "CounterHTOff": "0,1,2,3,4,5,6,7",
651        "EventCode": "0xB0",
652        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
653        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
654        "SampleAfterValue": "100003",
655        "UMask": "0x8"
656    },
657    {
658        "BriefDescription": "Cacheable and noncacheable code read requests",
659        "Counter": "0,1,2,3",
660        "CounterHTOff": "0,1,2,3,4,5,6,7",
661        "EventCode": "0xB0",
662        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
663        "PublicDescription": "Demand code read requests sent to uncore.",
664        "SampleAfterValue": "100003",
665        "UMask": "0x2"
666    },
667    {
668        "BriefDescription": "Demand Data Read requests sent to uncore",
669        "Counter": "0,1,2,3",
670        "CounterHTOff": "0,1,2,3,4,5,6,7",
671        "Errata": "HSD78, HSM80",
672        "EventCode": "0xb0",
673        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
674        "PublicDescription": "Demand data read requests sent to uncore.",
675        "SampleAfterValue": "100003",
676        "UMask": "0x1"
677    },
678    {
679        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
680        "Counter": "0,1,2,3",
681        "CounterHTOff": "0,1,2,3,4,5,6,7",
682        "EventCode": "0xB0",
683        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
684        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
685        "SampleAfterValue": "100003",
686        "UMask": "0x4"
687    },
688    {
689        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
690        "Counter": "0,1,2,3",
691        "CounterHTOff": "0,1,2,3,4,5,6,7",
692        "EventCode": "0xb2",
693        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
694        "SampleAfterValue": "2000003",
695        "UMask": "0x1"
696    },
697    {
698        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
699        "Counter": "0,1,2,3",
700        "CounterHTOff": "0,1,2,3,4,5,6,7",
701        "Errata": "HSD62, HSD61, HSM63",
702        "EventCode": "0x60",
703        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
704        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
705        "SampleAfterValue": "2000003",
706        "UMask": "0x8"
707    },
708    {
709        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
710        "Counter": "0,1,2,3",
711        "CounterHTOff": "0,1,2,3,4,5,6,7",
712        "CounterMask": "1",
713        "Errata": "HSD62, HSD61, HSM63",
714        "EventCode": "0x60",
715        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
716        "SampleAfterValue": "2000003",
717        "UMask": "0x8"
718    },
719    {
720        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
721        "Counter": "0,1,2,3",
722        "CounterHTOff": "0,1,2,3,4,5,6,7",
723        "CounterMask": "1",
724        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
725        "EventCode": "0x60",
726        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
727        "SampleAfterValue": "2000003",
728        "UMask": "0x1"
729    },
730    {
731        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
732        "Counter": "0,1,2,3",
733        "CounterHTOff": "0,1,2,3,4,5,6,7",
734        "CounterMask": "1",
735        "Errata": "HSD62, HSD61, HSM63",
736        "EventCode": "0x60",
737        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
738        "SampleAfterValue": "2000003",
739        "UMask": "0x4"
740    },
741    {
742        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
743        "Counter": "0,1,2,3",
744        "CounterHTOff": "0,1,2,3,4,5,6,7",
745        "Errata": "HSD62, HSD61, HSM63",
746        "EventCode": "0x60",
747        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
748        "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
749        "SampleAfterValue": "2000003",
750        "UMask": "0x2"
751    },
752    {
753        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
754        "Counter": "0,1,2,3",
755        "CounterHTOff": "0,1,2,3,4,5,6,7",
756        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
757        "EventCode": "0x60",
758        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
759        "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
760        "SampleAfterValue": "2000003",
761        "UMask": "0x1"
762    },
763    {
764        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
765        "Counter": "0,1,2,3",
766        "CounterHTOff": "0,1,2,3,4,5,6,7",
767        "CounterMask": "6",
768        "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
769        "EventCode": "0x60",
770        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
771        "SampleAfterValue": "2000003",
772        "UMask": "0x1"
773    },
774    {
775        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
776        "Counter": "0,1,2,3",
777        "CounterHTOff": "0,1,2,3,4,5,6,7",
778        "Errata": "HSD62, HSD61, HSM63",
779        "EventCode": "0x60",
780        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
781        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
782        "SampleAfterValue": "2000003",
783        "UMask": "0x4"
784    },
785    {
786        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
787        "Counter": "0,1,2,3",
788        "CounterHTOff": "0,1,2,3",
789        "EventCode": "0xB7, 0xBB",
790        "EventName": "OFFCORE_RESPONSE",
791        "SampleAfterValue": "100003",
792        "UMask": "0x1"
793    },
794    {
795        "BriefDescription": "Counts all demand & prefetch code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
796        "Counter": "0,1,2,3",
797        "CounterHTOff": "0,1,2,3",
798        "EventCode": "0xB7, 0xBB",
799        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
800        "MSRIndex": "0x1a6,0x1a7",
801        "MSRValue": "0x4003C0244",
802        "Offcore": "1",
803        "SampleAfterValue": "100003",
804        "UMask": "0x1"
805    },
806    {
807        "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
808        "Counter": "0,1,2,3",
809        "CounterHTOff": "0,1,2,3",
810        "EventCode": "0xB7, 0xBB",
811        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
812        "MSRIndex": "0x1a6,0x1a7",
813        "MSRValue": "0x10003C0091",
814        "Offcore": "1",
815        "SampleAfterValue": "100003",
816        "UMask": "0x1"
817    },
818    {
819        "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
820        "Counter": "0,1,2,3",
821        "CounterHTOff": "0,1,2,3",
822        "EventCode": "0xB7, 0xBB",
823        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
824        "MSRIndex": "0x1a6,0x1a7",
825        "MSRValue": "0x4003C0091",
826        "Offcore": "1",
827        "SampleAfterValue": "100003",
828        "UMask": "0x1"
829    },
830    {
831        "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
832        "Counter": "0,1,2,3",
833        "CounterHTOff": "0,1,2,3",
834        "EventCode": "0xB7, 0xBB",
835        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
836        "MSRIndex": "0x1a6,0x1a7",
837        "MSRValue": "0x10003C07F7",
838        "Offcore": "1",
839        "SampleAfterValue": "100003",
840        "UMask": "0x1"
841    },
842    {
843        "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
844        "Counter": "0,1,2,3",
845        "CounterHTOff": "0,1,2,3",
846        "EventCode": "0xB7, 0xBB",
847        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
848        "MSRIndex": "0x1a6,0x1a7",
849        "MSRValue": "0x4003C07F7",
850        "Offcore": "1",
851        "SampleAfterValue": "100003",
852        "UMask": "0x1"
853    },
854    {
855        "BriefDescription": "Counts all requestshit in the L3",
856        "Counter": "0,1,2,3",
857        "CounterHTOff": "0,1,2,3",
858        "EventCode": "0xB7, 0xBB",
859        "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
860        "MSRIndex": "0x1a6,0x1a7",
861        "MSRValue": "0x3F803C8FFF",
862        "Offcore": "1",
863        "SampleAfterValue": "100003",
864        "UMask": "0x1"
865    },
866    {
867        "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
868        "Counter": "0,1,2,3",
869        "CounterHTOff": "0,1,2,3",
870        "EventCode": "0xB7, 0xBB",
871        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
872        "MSRIndex": "0x1a6,0x1a7",
873        "MSRValue": "0x10003C0122",
874        "Offcore": "1",
875        "SampleAfterValue": "100003",
876        "UMask": "0x1"
877    },
878    {
879        "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
880        "Counter": "0,1,2,3",
881        "CounterHTOff": "0,1,2,3",
882        "EventCode": "0xB7, 0xBB",
883        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
884        "MSRIndex": "0x1a6,0x1a7",
885        "MSRValue": "0x4003C0122",
886        "Offcore": "1",
887        "SampleAfterValue": "100003",
888        "UMask": "0x1"
889    },
890    {
891        "BriefDescription": "Counts all demand code readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
892        "Counter": "0,1,2,3",
893        "CounterHTOff": "0,1,2,3",
894        "EventCode": "0xB7, 0xBB",
895        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
896        "MSRIndex": "0x1a6,0x1a7",
897        "MSRValue": "0x10003C0004",
898        "Offcore": "1",
899        "SampleAfterValue": "100003",
900        "UMask": "0x1"
901    },
902    {
903        "BriefDescription": "Counts all demand code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
904        "Counter": "0,1,2,3",
905        "CounterHTOff": "0,1,2,3",
906        "EventCode": "0xB7, 0xBB",
907        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
908        "MSRIndex": "0x1a6,0x1a7",
909        "MSRValue": "0x4003C0004",
910        "Offcore": "1",
911        "SampleAfterValue": "100003",
912        "UMask": "0x1"
913    },
914    {
915        "BriefDescription": "Counts demand data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
916        "Counter": "0,1,2,3",
917        "CounterHTOff": "0,1,2,3",
918        "EventCode": "0xB7, 0xBB",
919        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
920        "MSRIndex": "0x1a6,0x1a7",
921        "MSRValue": "0x10003C0001",
922        "Offcore": "1",
923        "SampleAfterValue": "100003",
924        "UMask": "0x1"
925    },
926    {
927        "BriefDescription": "Counts demand data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
928        "Counter": "0,1,2,3",
929        "CounterHTOff": "0,1,2,3",
930        "EventCode": "0xB7, 0xBB",
931        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
932        "MSRIndex": "0x1a6,0x1a7",
933        "MSRValue": "0x4003C0001",
934        "Offcore": "1",
935        "SampleAfterValue": "100003",
936        "UMask": "0x1"
937    },
938    {
939        "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
940        "Counter": "0,1,2,3",
941        "CounterHTOff": "0,1,2,3",
942        "EventCode": "0xB7, 0xBB",
943        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
944        "MSRIndex": "0x1a6,0x1a7",
945        "MSRValue": "0x10003C0002",
946        "Offcore": "1",
947        "SampleAfterValue": "100003",
948        "UMask": "0x1"
949    },
950    {
951        "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
952        "Counter": "0,1,2,3",
953        "CounterHTOff": "0,1,2,3",
954        "EventCode": "0xB7, 0xBB",
955        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
956        "MSRIndex": "0x1a6,0x1a7",
957        "MSRValue": "0x4003C0002",
958        "Offcore": "1",
959        "SampleAfterValue": "100003",
960        "UMask": "0x1"
961    },
962    {
963        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readshit in the L3",
964        "Counter": "0,1,2,3",
965        "CounterHTOff": "0,1,2,3",
966        "EventCode": "0xB7, 0xBB",
967        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
968        "MSRIndex": "0x1a6,0x1a7",
969        "MSRValue": "0x3F803C0040",
970        "Offcore": "1",
971        "SampleAfterValue": "100003",
972        "UMask": "0x1"
973    },
974    {
975        "BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3",
976        "Counter": "0,1,2,3",
977        "CounterHTOff": "0,1,2,3",
978        "EventCode": "0xB7, 0xBB",
979        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
980        "MSRIndex": "0x1a6,0x1a7",
981        "MSRValue": "0x3F803C0010",
982        "Offcore": "1",
983        "SampleAfterValue": "100003",
984        "UMask": "0x1"
985    },
986    {
987        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3",
988        "Counter": "0,1,2,3",
989        "CounterHTOff": "0,1,2,3",
990        "EventCode": "0xB7, 0xBB",
991        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
992        "MSRIndex": "0x1a6,0x1a7",
993        "MSRValue": "0x3F803C0020",
994        "Offcore": "1",
995        "SampleAfterValue": "100003",
996        "UMask": "0x1"
997    },
998    {
999        "BriefDescription": "Counts prefetch (that bring data to LLC only) code readshit in the L3",
1000        "Counter": "0,1,2,3",
1001        "CounterHTOff": "0,1,2,3",
1002        "EventCode": "0xB7, 0xBB",
1003        "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
1004        "MSRIndex": "0x1a6,0x1a7",
1005        "MSRValue": "0x3F803C0200",
1006        "Offcore": "1",
1007        "SampleAfterValue": "100003",
1008        "UMask": "0x1"
1009    },
1010    {
1011        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readshit in the L3",
1012        "Counter": "0,1,2,3",
1013        "CounterHTOff": "0,1,2,3",
1014        "EventCode": "0xB7, 0xBB",
1015        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
1016        "MSRIndex": "0x1a6,0x1a7",
1017        "MSRValue": "0x3F803C0080",
1018        "Offcore": "1",
1019        "SampleAfterValue": "100003",
1020        "UMask": "0x1"
1021    },
1022    {
1023        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOshit in the L3",
1024        "Counter": "0,1,2,3",
1025        "CounterHTOff": "0,1,2,3",
1026        "EventCode": "0xB7, 0xBB",
1027        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
1028        "MSRIndex": "0x1a6,0x1a7",
1029        "MSRValue": "0x3F803C0100",
1030        "Offcore": "1",
1031        "SampleAfterValue": "100003",
1032        "UMask": "0x1"
1033    },
1034    {
1035        "BriefDescription": "Split locks in SQ",
1036        "Counter": "0,1,2,3",
1037        "CounterHTOff": "0,1,2,3,4,5,6,7",
1038        "EventCode": "0xf4",
1039        "EventName": "SQ_MISC.SPLIT_LOCK",
1040        "SampleAfterValue": "100003",
1041        "UMask": "0x10"
1042    }
1043]
1044