1[
2    {
3        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xC3",
7        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
8        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
9        "SampleAfterValue": "100003",
10        "UMask": "0x2"
11    },
12    {
13        "BriefDescription": "Loads with latency value being above 128.",
14        "Counter": "3",
15        "CounterHTOff": "3",
16        "EventCode": "0xCD",
17        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
18        "MSRIndex": "0x3F6",
19        "MSRValue": "0x80",
20        "PEBS": "2",
21        "SampleAfterValue": "1009",
22        "TakenAlone": "1",
23        "UMask": "0x1"
24    },
25    {
26        "BriefDescription": "Loads with latency value being above 16.",
27        "Counter": "3",
28        "CounterHTOff": "3",
29        "EventCode": "0xCD",
30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
31        "MSRIndex": "0x3F6",
32        "MSRValue": "0x10",
33        "PEBS": "2",
34        "SampleAfterValue": "20011",
35        "TakenAlone": "1",
36        "UMask": "0x1"
37    },
38    {
39        "BriefDescription": "Loads with latency value being above 256.",
40        "Counter": "3",
41        "CounterHTOff": "3",
42        "EventCode": "0xCD",
43        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
44        "MSRIndex": "0x3F6",
45        "MSRValue": "0x100",
46        "PEBS": "2",
47        "SampleAfterValue": "503",
48        "TakenAlone": "1",
49        "UMask": "0x1"
50    },
51    {
52        "BriefDescription": "Loads with latency value being above 32.",
53        "Counter": "3",
54        "CounterHTOff": "3",
55        "EventCode": "0xCD",
56        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
57        "MSRIndex": "0x3F6",
58        "MSRValue": "0x20",
59        "PEBS": "2",
60        "SampleAfterValue": "100007",
61        "TakenAlone": "1",
62        "UMask": "0x1"
63    },
64    {
65        "BriefDescription": "Loads with latency value being above 4 .",
66        "Counter": "3",
67        "CounterHTOff": "3",
68        "EventCode": "0xCD",
69        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
70        "MSRIndex": "0x3F6",
71        "MSRValue": "0x4",
72        "PEBS": "2",
73        "SampleAfterValue": "100003",
74        "TakenAlone": "1",
75        "UMask": "0x1"
76    },
77    {
78        "BriefDescription": "Loads with latency value being above 512.",
79        "Counter": "3",
80        "CounterHTOff": "3",
81        "EventCode": "0xCD",
82        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
83        "MSRIndex": "0x3F6",
84        "MSRValue": "0x200",
85        "PEBS": "2",
86        "SampleAfterValue": "101",
87        "TakenAlone": "1",
88        "UMask": "0x1"
89    },
90    {
91        "BriefDescription": "Loads with latency value being above 64.",
92        "Counter": "3",
93        "CounterHTOff": "3",
94        "EventCode": "0xCD",
95        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
96        "MSRIndex": "0x3F6",
97        "MSRValue": "0x40",
98        "PEBS": "2",
99        "SampleAfterValue": "2003",
100        "TakenAlone": "1",
101        "UMask": "0x1"
102    },
103    {
104        "BriefDescription": "Loads with latency value being above 8.",
105        "Counter": "3",
106        "CounterHTOff": "3",
107        "EventCode": "0xCD",
108        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
109        "MSRIndex": "0x3F6",
110        "MSRValue": "0x8",
111        "PEBS": "2",
112        "SampleAfterValue": "50021",
113        "TakenAlone": "1",
114        "UMask": "0x1"
115    },
116    {
117        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
118        "Counter": "3",
119        "CounterHTOff": "3",
120        "EventCode": "0xCD",
121        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
122        "PEBS": "2",
123        "PRECISE_STORE": "1",
124        "SampleAfterValue": "2000003",
125        "TakenAlone": "1",
126        "UMask": "0x2"
127    },
128    {
129        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
130        "Counter": "0,1,2,3",
131        "CounterHTOff": "0,1,2,3,4,5,6,7",
132        "EventCode": "0x05",
133        "EventName": "MISALIGN_MEM_REF.LOADS",
134        "SampleAfterValue": "2000003",
135        "UMask": "0x1"
136    },
137    {
138        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
139        "Counter": "0,1,2,3",
140        "CounterHTOff": "0,1,2,3,4,5,6,7",
141        "EventCode": "0x05",
142        "EventName": "MISALIGN_MEM_REF.STORES",
143        "SampleAfterValue": "2000003",
144        "UMask": "0x2"
145    },
146    {
147        "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
148        "Counter": "0,1,2,3",
149        "CounterHTOff": "0,1,2,3",
150        "EventCode": "0xB7, 0xBB",
151        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
152        "MSRIndex": "0x1a6,0x1a7",
153        "MSRValue": "0x3FFFC20077",
154        "Offcore": "1",
155        "SampleAfterValue": "100003",
156        "UMask": "0x1"
157    },
158    {
159        "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
160        "Counter": "0,1,2,3",
161        "CounterHTOff": "0,1,2,3",
162        "EventCode": "0xB7, 0xBB",
163        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
164        "MSRIndex": "0x1a6,0x1a7",
165        "MSRValue": "0x600400077",
166        "Offcore": "1",
167        "SampleAfterValue": "100003",
168        "UMask": "0x1"
169    },
170    {
171        "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
172        "Counter": "0,1,2,3",
173        "CounterHTOff": "0,1,2,3",
174        "EventCode": "0xB7, 0xBB",
175        "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
176        "MSRIndex": "0x1a6,0x1a7",
177        "MSRValue": "0x187FC20077",
178        "Offcore": "1",
179        "SampleAfterValue": "100003",
180        "UMask": "0x1"
181    },
182    {
183        "BriefDescription": "Counts all demand code reads that miss the LLC",
184        "Counter": "0,1,2,3",
185        "CounterHTOff": "0,1,2,3",
186        "EventCode": "0xB7, 0xBB",
187        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
188        "MSRIndex": "0x1a6,0x1a7",
189        "MSRValue": "0x3fffc20004",
190        "Offcore": "1",
191        "SampleAfterValue": "100003",
192        "UMask": "0x1"
193    },
194    {
195        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",
196        "Counter": "0,1,2,3",
197        "CounterHTOff": "0,1,2,3",
198        "EventCode": "0xB7, 0xBB",
199        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
200        "MSRIndex": "0x1a6,0x1a7",
201        "MSRValue": "0x600400004",
202        "Offcore": "1",
203        "SampleAfterValue": "100003",
204        "UMask": "0x1"
205    },
206    {
207        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",
208        "Counter": "0,1,2,3",
209        "CounterHTOff": "0,1,2,3",
210        "EventCode": "0xB7, 0xBB",
211        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
212        "MSRIndex": "0x1a6,0x1a7",
213        "MSRValue": "0x67f800004",
214        "Offcore": "1",
215        "SampleAfterValue": "100003",
216        "UMask": "0x1"
217    },
218    {
219        "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
220        "Counter": "0,1,2,3",
221        "CounterHTOff": "0,1,2,3",
222        "EventCode": "0xB7, 0xBB",
223        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
224        "MSRIndex": "0x1a6,0x1a7",
225        "MSRValue": "0x107fc00004",
226        "Offcore": "1",
227        "SampleAfterValue": "100003",
228        "UMask": "0x1"
229    },
230    {
231        "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",
232        "Counter": "0,1,2,3",
233        "CounterHTOff": "0,1,2,3",
234        "EventCode": "0xB7, 0xBB",
235        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
236        "MSRIndex": "0x1a6,0x1a7",
237        "MSRValue": "0x87f820004",
238        "Offcore": "1",
239        "SampleAfterValue": "100003",
240        "UMask": "0x1"
241    },
242    {
243        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",
244        "Counter": "0,1,2,3",
245        "CounterHTOff": "0,1,2,3",
246        "EventCode": "0xB7, 0xBB",
247        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
248        "MSRIndex": "0x1a6,0x1a7",
249        "MSRValue": "0x67fc00001",
250        "Offcore": "1",
251        "SampleAfterValue": "100003",
252        "UMask": "0x1"
253    },
254    {
255        "BriefDescription": "Counts demand data reads that miss in the LLC",
256        "Counter": "0,1,2,3",
257        "CounterHTOff": "0,1,2,3",
258        "EventCode": "0xB7, 0xBB",
259        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
260        "MSRIndex": "0x1a6,0x1a7",
261        "MSRValue": "0x3fffc20001",
262        "Offcore": "1",
263        "SampleAfterValue": "100003",
264        "UMask": "0x1"
265    },
266    {
267        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",
268        "Counter": "0,1,2,3",
269        "CounterHTOff": "0,1,2,3",
270        "EventCode": "0xB7, 0xBB",
271        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
272        "MSRIndex": "0x1a6,0x1a7",
273        "MSRValue": "0x600400001",
274        "Offcore": "1",
275        "SampleAfterValue": "100003",
276        "UMask": "0x1"
277    },
278    {
279        "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",
280        "Counter": "0,1,2,3",
281        "CounterHTOff": "0,1,2,3",
282        "EventCode": "0xB7, 0xBB",
283        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
284        "MSRIndex": "0x1a6,0x1a7",
285        "MSRValue": "0x67f800001",
286        "Offcore": "1",
287        "SampleAfterValue": "100003",
288        "UMask": "0x1"
289    },
290    {
291        "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
292        "Counter": "0,1,2,3",
293        "CounterHTOff": "0,1,2,3",
294        "EventCode": "0xB7, 0xBB",
295        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
296        "MSRIndex": "0x1a6,0x1a7",
297        "MSRValue": "0x107fc00001",
298        "Offcore": "1",
299        "SampleAfterValue": "100003",
300        "UMask": "0x1"
301    },
302    {
303        "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",
304        "Counter": "0,1,2,3",
305        "CounterHTOff": "0,1,2,3",
306        "EventCode": "0xB7, 0xBB",
307        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
308        "MSRIndex": "0x1a6,0x1a7",
309        "MSRValue": "0x87f820001",
310        "Offcore": "1",
311        "SampleAfterValue": "100003",
312        "UMask": "0x1"
313    },
314    {
315        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",
316        "Counter": "0,1,2,3",
317        "CounterHTOff": "0,1,2,3",
318        "EventCode": "0xB7, 0xBB",
319        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
320        "MSRIndex": "0x1a6,0x1a7",
321        "MSRValue": "0x3fffc20040",
322        "Offcore": "1",
323        "SampleAfterValue": "100003",
324        "UMask": "0x1"
325    },
326    {
327        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",
328        "Counter": "0,1,2,3",
329        "CounterHTOff": "0,1,2,3",
330        "EventCode": "0xB7, 0xBB",
331        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
332        "MSRIndex": "0x1a6,0x1a7",
333        "MSRValue": "0x67fc00010",
334        "Offcore": "1",
335        "SampleAfterValue": "100003",
336        "UMask": "0x1"
337    },
338    {
339        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
340        "Counter": "0,1,2,3",
341        "CounterHTOff": "0,1,2,3",
342        "EventCode": "0xB7, 0xBB",
343        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
344        "MSRIndex": "0x1a6,0x1a7",
345        "MSRValue": "0x3fffc20010",
346        "Offcore": "1",
347        "SampleAfterValue": "100003",
348        "UMask": "0x1"
349    },
350    {
351        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",
352        "Counter": "0,1,2,3",
353        "CounterHTOff": "0,1,2,3",
354        "EventCode": "0xB7, 0xBB",
355        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
356        "MSRIndex": "0x1a6,0x1a7",
357        "MSRValue": "0x600400010",
358        "Offcore": "1",
359        "SampleAfterValue": "100003",
360        "UMask": "0x1"
361    },
362    {
363        "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",
364        "Counter": "0,1,2,3",
365        "CounterHTOff": "0,1,2,3",
366        "EventCode": "0xB7, 0xBB",
367        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
368        "MSRIndex": "0x1a6,0x1a7",
369        "MSRValue": "0x67f800010",
370        "Offcore": "1",
371        "SampleAfterValue": "100003",
372        "UMask": "0x1"
373    },
374    {
375        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
376        "Counter": "0,1,2,3",
377        "CounterHTOff": "0,1,2,3",
378        "EventCode": "0xB7, 0xBB",
379        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
380        "MSRIndex": "0x1a6,0x1a7",
381        "MSRValue": "0x107fc00010",
382        "Offcore": "1",
383        "SampleAfterValue": "100003",
384        "UMask": "0x1"
385    },
386    {
387        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",
388        "Counter": "0,1,2,3",
389        "CounterHTOff": "0,1,2,3",
390        "EventCode": "0xB7, 0xBB",
391        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
392        "MSRIndex": "0x1a6,0x1a7",
393        "MSRValue": "0x87f820010",
394        "Offcore": "1",
395        "SampleAfterValue": "100003",
396        "UMask": "0x1"
397    },
398    {
399        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
400        "Counter": "0,1,2,3",
401        "CounterHTOff": "0,1,2,3",
402        "EventCode": "0xB7, 0xBB",
403        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
404        "MSRIndex": "0x1a6,0x1a7",
405        "MSRValue": "0x3fffc20200",
406        "Offcore": "1",
407        "SampleAfterValue": "100003",
408        "UMask": "0x1"
409    },
410    {
411        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
412        "Counter": "0,1,2,3",
413        "CounterHTOff": "0,1,2,3",
414        "EventCode": "0xB7, 0xBB",
415        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
416        "MSRIndex": "0x1a6,0x1a7",
417        "MSRValue": "0x3fffc20080",
418        "Offcore": "1",
419        "SampleAfterValue": "100003",
420        "UMask": "0x1"
421    }
422]
423