1[
2    {
3        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x2e",
7        "EventName": "LONGEST_LAT_CACHE.MISS",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "SampleAfterValue": "200003",
10        "UMask": "0x41",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0x2e",
18        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
19        "PEBScounters": "0,1,2,3,4,5,6,7",
20        "SampleAfterValue": "200003",
21        "UMask": "0x4f",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Counts the number of load ops retired.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5,6,7",
28        "Data_LA": "1",
29        "EventCode": "0xd0",
30        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
31        "PEBS": "1",
32        "PEBScounters": "0,1,2,3,4,5,6,7",
33        "SampleAfterValue": "200003",
34        "UMask": "0x81",
35        "Unit": "cpu_atom"
36    },
37    {
38        "BriefDescription": "Counts the number of store ops retired.",
39        "CollectPEBSRecord": "2",
40        "Counter": "0,1,2,3,4,5,6,7",
41        "Data_LA": "1",
42        "EventCode": "0xd0",
43        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
44        "PEBS": "1",
45        "PEBScounters": "0,1,2,3,4,5,6,7",
46        "SampleAfterValue": "200003",
47        "UMask": "0x82",
48        "Unit": "cpu_atom"
49    },
50    {
51        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
52        "CollectPEBSRecord": "3",
53        "Counter": "0,1,2,3,4,5,6,7",
54        "Data_LA": "1",
55        "EventCode": "0xd0",
56        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
57        "MSRIndex": "0x3F6",
58        "MSRValue": "0x80",
59        "PEBS": "2",
60        "PEBScounters": "0,1,2,3,4,5,6,7",
61        "SampleAfterValue": "1000003",
62        "TakenAlone": "1",
63        "UMask": "0x5",
64        "Unit": "cpu_atom"
65    },
66    {
67        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
68        "CollectPEBSRecord": "3",
69        "Counter": "0,1,2,3,4,5,6,7",
70        "Data_LA": "1",
71        "EventCode": "0xd0",
72        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
73        "MSRIndex": "0x3F6",
74        "MSRValue": "0x10",
75        "PEBS": "2",
76        "PEBScounters": "0,1,2,3,4,5,6,7",
77        "SampleAfterValue": "1000003",
78        "TakenAlone": "1",
79        "UMask": "0x5",
80        "Unit": "cpu_atom"
81    },
82    {
83        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
84        "CollectPEBSRecord": "3",
85        "Counter": "0,1,2,3,4,5,6,7",
86        "Data_LA": "1",
87        "EventCode": "0xd0",
88        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
89        "MSRIndex": "0x3F6",
90        "MSRValue": "0x100",
91        "PEBS": "2",
92        "PEBScounters": "0,1,2,3,4,5,6,7",
93        "SampleAfterValue": "1000003",
94        "TakenAlone": "1",
95        "UMask": "0x5",
96        "Unit": "cpu_atom"
97    },
98    {
99        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
100        "CollectPEBSRecord": "3",
101        "Counter": "0,1,2,3,4,5,6,7",
102        "Data_LA": "1",
103        "EventCode": "0xd0",
104        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
105        "MSRIndex": "0x3F6",
106        "MSRValue": "0x20",
107        "PEBS": "2",
108        "PEBScounters": "0,1,2,3,4,5,6,7",
109        "SampleAfterValue": "1000003",
110        "TakenAlone": "1",
111        "UMask": "0x5",
112        "Unit": "cpu_atom"
113    },
114    {
115        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
116        "CollectPEBSRecord": "3",
117        "Counter": "0,1,2,3,4,5,6,7",
118        "Data_LA": "1",
119        "EventCode": "0xd0",
120        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
121        "MSRIndex": "0x3F6",
122        "MSRValue": "0x4",
123        "PEBS": "2",
124        "PEBScounters": "0,1,2,3,4,5,6,7",
125        "SampleAfterValue": "1000003",
126        "TakenAlone": "1",
127        "UMask": "0x5",
128        "Unit": "cpu_atom"
129    },
130    {
131        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
132        "CollectPEBSRecord": "3",
133        "Counter": "0,1,2,3,4,5,6,7",
134        "Data_LA": "1",
135        "EventCode": "0xd0",
136        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
137        "MSRIndex": "0x3F6",
138        "MSRValue": "0x200",
139        "PEBS": "2",
140        "PEBScounters": "0,1,2,3,4,5,6,7",
141        "SampleAfterValue": "1000003",
142        "TakenAlone": "1",
143        "UMask": "0x5",
144        "Unit": "cpu_atom"
145    },
146    {
147        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
148        "CollectPEBSRecord": "3",
149        "Counter": "0,1,2,3,4,5,6,7",
150        "Data_LA": "1",
151        "EventCode": "0xd0",
152        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
153        "MSRIndex": "0x3F6",
154        "MSRValue": "0x40",
155        "PEBS": "2",
156        "PEBScounters": "0,1,2,3,4,5,6,7",
157        "SampleAfterValue": "1000003",
158        "TakenAlone": "1",
159        "UMask": "0x5",
160        "Unit": "cpu_atom"
161    },
162    {
163        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
164        "CollectPEBSRecord": "3",
165        "Counter": "0,1,2,3,4,5,6,7",
166        "Data_LA": "1",
167        "EventCode": "0xd0",
168        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
169        "MSRIndex": "0x3F6",
170        "MSRValue": "0x8",
171        "PEBS": "2",
172        "PEBScounters": "0,1,2,3,4,5,6,7",
173        "SampleAfterValue": "1000003",
174        "TakenAlone": "1",
175        "UMask": "0x5",
176        "Unit": "cpu_atom"
177    },
178    {
179        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
180        "CollectPEBSRecord": "3",
181        "Counter": "0,1,2,3,4,5,6,7",
182        "Data_LA": "1",
183        "EventCode": "0xd0",
184        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
185        "PEBS": "2",
186        "PEBScounters": "0,1,2,3,4,5,6,7",
187        "SampleAfterValue": "1000003",
188        "UMask": "0x6",
189        "Unit": "cpu_atom"
190    },
191    {
192        "BriefDescription": "L2 code requests",
193        "CollectPEBSRecord": "2",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x24",
196        "EventName": "L2_RQSTS.ALL_CODE_RD",
197        "PEBScounters": "0,1,2,3",
198        "SampleAfterValue": "200003",
199        "UMask": "0xe4",
200        "Unit": "cpu_core"
201    },
202    {
203        "BriefDescription": "Demand Data Read access L2 cache",
204        "CollectPEBSRecord": "2",
205        "Counter": "0,1,2,3",
206        "EventCode": "0x24",
207        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
208        "PEBScounters": "0,1,2,3",
209        "SampleAfterValue": "200003",
210        "UMask": "0xe1",
211        "Unit": "cpu_core"
212    },
213    {
214        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
215        "CollectPEBSRecord": "2",
216        "Counter": "0,1,2,3,4,5,6,7",
217        "EventCode": "0x2e",
218        "EventName": "LONGEST_LAT_CACHE.MISS",
219        "PEBScounters": "0,1,2,3,4,5,6,7",
220        "SampleAfterValue": "100003",
221        "UMask": "0x41",
222        "Unit": "cpu_core"
223    },
224    {
225        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
226        "CollectPEBSRecord": "2",
227        "Counter": "0,1,2,3,4,5,6,7",
228        "EventCode": "0x2e",
229        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
230        "PEBScounters": "0,1,2,3,4,5,6,7",
231        "SampleAfterValue": "100003",
232        "UMask": "0x4f",
233        "Unit": "cpu_core"
234    },
235    {
236        "BriefDescription": "Retired load instructions.",
237        "CollectPEBSRecord": "2",
238        "Counter": "0,1,2,3",
239        "Data_LA": "1",
240        "EventCode": "0xd0",
241        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
242        "PEBS": "1",
243        "PEBScounters": "0,1,2,3",
244        "SampleAfterValue": "1000003",
245        "UMask": "0x81",
246        "Unit": "cpu_core"
247    },
248    {
249        "BriefDescription": "Retired store instructions.",
250        "CollectPEBSRecord": "2",
251        "Counter": "0,1,2,3",
252        "Data_LA": "1",
253        "EventCode": "0xd0",
254        "EventName": "MEM_INST_RETIRED.ALL_STORES",
255        "L1_Hit_Indication": "1",
256        "PEBS": "1",
257        "PEBScounters": "0,1,2,3",
258        "SampleAfterValue": "1000003",
259        "UMask": "0x82",
260        "Unit": "cpu_core"
261    }
262]
263