1[
2    {
3        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
4        "EventCode": "0x84",
5        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
6        "PerPkg": "1",
7        "UMask": "0x1",
8        "Unit": "ARB"
9    },
10    {
11        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
12        "EventCode": "0x80",
13        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
14        "PerPkg": "1",
15        "UMask": "0x1",
16        "Unit": "ARB"
17    },
18    {
19        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
20        "CounterMask": "1",
21        "EventCode": "0x80",
22        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
23        "PerPkg": "1",
24        "UMask": "0x1",
25        "Unit": "ARB"
26    },
27    {
28        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
29        "EventCode": "0x80",
30        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
31        "PerPkg": "1",
32        "UMask": "0x2",
33        "Unit": "ARB"
34    },
35    {
36        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
37        "EventCode": "0x81",
38        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
39        "PerPkg": "1",
40        "UMask": "0x1",
41        "Unit": "ARB"
42    },
43    {
44        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
45        "EventCode": "0x81",
46        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
47        "PerPkg": "1",
48        "UMask": "0x2",
49        "Unit": "ARB"
50    },
51    {
52        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
53        "EventCode": "0x81",
54        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
55        "PerPkg": "1",
56        "UMask": "0x2",
57        "Unit": "ARB"
58    },
59    {
60        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
61        "EventCode": "0x81",
62        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
63        "PerPkg": "1",
64        "UMask": "0x20",
65        "Unit": "ARB"
66    }
67]
68