1[
2    {
3        "BriefDescription": "Pre-charge for reads",
4        "Counter": "0,1,2,3",
5        "CounterType": "PGMABLE",
6        "EventCode": "0x02",
7        "EventName": "UNC_M_PRE_COUNT.RD",
8        "PerPkg": "1",
9        "UMask": "0x04",
10        "Unit": "iMC"
11    },
12    {
13        "BriefDescription": "Pre-charge for writes",
14        "Counter": "0,1,2,3",
15        "CounterType": "PGMABLE",
16        "EventCode": "0x02",
17        "EventName": "UNC_M_PRE_COUNT.WR",
18        "PerPkg": "1",
19        "UMask": "0x08",
20        "Unit": "iMC"
21    },
22    {
23        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
24        "Counter": "0,1,2,3",
25        "CounterType": "PGMABLE",
26        "EventCode": "0x04",
27        "EventName": "LLC_MISSES.MEM_READ",
28        "PerPkg": "1",
29        "ScaleUnit": "64Bytes",
30        "UMask": "0x0f",
31        "Unit": "iMC"
32    },
33    {
34        "BriefDescription": "read requests to memory controller",
35        "Counter": "0,1,2,3",
36        "CounterType": "PGMABLE",
37        "EventCode": "0x04",
38        "EventName": "UNC_M_CAS_COUNT.RD",
39        "PerPkg": "1",
40        "ScaleUnit": "64Bytes",
41        "UMask": "0x0f",
42        "Unit": "iMC"
43    },
44    {
45        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
46        "Counter": "0,1,2,3",
47        "CounterType": "PGMABLE",
48        "EventCode": "0x04",
49        "EventName": "LLC_MISSES.MEM_WRITE",
50        "PerPkg": "1",
51        "ScaleUnit": "64Bytes",
52        "UMask": "0x30",
53        "Unit": "iMC"
54    },
55    {
56        "BriefDescription": "write requests to memory controller",
57        "Counter": "0,1,2,3",
58        "CounterType": "PGMABLE",
59        "EventCode": "0x04",
60        "EventName": "UNC_M_CAS_COUNT.WR",
61        "PerPkg": "1",
62        "ScaleUnit": "64Bytes",
63        "UMask": "0x30",
64        "Unit": "iMC"
65    },
66    {
67        "BriefDescription": "All DRAM CAS commands issued",
68        "Counter": "0,1,2,3",
69        "CounterType": "PGMABLE",
70        "EventCode": "0x04",
71        "EventName": "UNC_M_CAS_COUNT.ALL",
72        "PerPkg": "1",
73        "UMask": "0x3f",
74        "Unit": "iMC"
75    },
76    {
77        "BriefDescription": "Number of DRAM Refreshes Issued",
78        "Counter": "0,1,2,3",
79        "CounterType": "PGMABLE",
80        "EventCode": "0x45",
81        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
82        "PerPkg": "1",
83        "UMask": "0x01",
84        "Unit": "iMC"
85    },
86    {
87        "BriefDescription": "Number of DRAM Refreshes Issued",
88        "Counter": "0,1,2,3",
89        "CounterType": "PGMABLE",
90        "EventCode": "0x45",
91        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
92        "PerPkg": "1",
93        "UMask": "0x02",
94        "Unit": "iMC"
95    },
96    {
97        "BriefDescription": "Number of DRAM Refreshes Issued",
98        "Counter": "0,1,2,3",
99        "CounterType": "PGMABLE",
100        "EventCode": "0x45",
101        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
102        "PerPkg": "1",
103        "UMask": "0x04",
104        "Unit": "iMC"
105    },
106    {
107        "BriefDescription": "Read Pending Queue Allocations",
108        "Counter": "0,1,2,3",
109        "CounterType": "PGMABLE",
110        "EventCode": "0x10",
111        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
112        "PerPkg": "1",
113        "UMask": "0x01",
114        "Unit": "iMC"
115    },
116    {
117        "BriefDescription": "Read Pending Queue Allocations",
118        "Counter": "0,1,2,3",
119        "CounterType": "PGMABLE",
120        "EventCode": "0x10",
121        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
122        "PerPkg": "1",
123        "UMask": "0x02",
124        "Unit": "iMC"
125    },
126    {
127        "BriefDescription": "Write Pending Queue Allocations",
128        "Counter": "0,1,2,3",
129        "CounterType": "PGMABLE",
130        "EventCode": "0x20",
131        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
132        "PerPkg": "1",
133        "UMask": "0x01",
134        "Unit": "iMC"
135    },
136    {
137        "BriefDescription": "Write Pending Queue Allocations",
138        "Counter": "0,1,2,3",
139        "CounterType": "PGMABLE",
140        "EventCode": "0x20",
141        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
142        "PerPkg": "1",
143        "UMask": "0x02",
144        "Unit": "iMC"
145    },
146    {
147        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
148        "Counter": "0,1,2,3",
149        "CounterType": "PGMABLE",
150        "EventCode": "0x02",
151        "EventName": "UNC_M_PRE_COUNT.PGT",
152        "PerPkg": "1",
153        "UMask": "0x10",
154        "Unit": "iMC"
155    },
156    {
157        "BriefDescription": "Memory controller clock ticks",
158        "Counter": "0,1,2,3",
159        "CounterType": "PGMABLE",
160        "EventName": "UNC_M_CLOCKTICKS",
161        "PerPkg": "1",
162        "Unit": "iMC"
163    },
164    {
165        "BriefDescription": "Half clockticks for IMC",
166        "Counter": "FIXED",
167        "CounterType": "FIXED",
168        "EventCode": "0xff",
169        "EventName": "UNC_M_HCLOCKTICKS",
170        "PerPkg": "1",
171        "Unit": "iMC"
172    },
173    {
174        "BriefDescription": "Read Pending Queue Occupancy",
175        "Counter": "0,1,2,3",
176        "CounterType": "PGMABLE",
177        "EventCode": "0x80",
178        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
179        "PerPkg": "1",
180        "Unit": "iMC"
181    },
182    {
183        "BriefDescription": "Read Pending Queue Occupancy",
184        "Counter": "0,1,2,3",
185        "CounterType": "PGMABLE",
186        "EventCode": "0x81",
187        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
188        "PerPkg": "1",
189        "Unit": "iMC"
190    },
191    {
192        "BriefDescription": "Write Pending Queue Occupancy",
193        "Counter": "0,1,2,3",
194        "CounterType": "PGMABLE",
195        "EventCode": "0x82",
196        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
197        "PerPkg": "1",
198        "Unit": "iMC"
199    },
200    {
201        "BriefDescription": "Write Pending Queue Occupancy",
202        "Counter": "0,1,2,3",
203        "CounterType": "PGMABLE",
204        "EventCode": "0x83",
205        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
206        "PerPkg": "1",
207        "Unit": "iMC"
208    },
209    {
210        "BriefDescription": "DRAM Activate Count : All Activates",
211        "Counter": "0,1,2,3",
212        "CounterType": "PGMABLE",
213        "EventCode": "0x01",
214        "EventName": "UNC_M_ACT_COUNT.ALL",
215        "PerPkg": "1",
216        "UMask": "0x0B",
217        "Unit": "iMC"
218    },
219    {
220        "BriefDescription": "DRAM Precharge commands",
221        "Counter": "0,1,2,3",
222        "CounterType": "PGMABLE",
223        "EventCode": "0x02",
224        "EventName": "UNC_M_PRE_COUNT.ALL",
225        "PerPkg": "1",
226        "UMask": "0x1C",
227        "Unit": "iMC"
228    },
229    {
230        "BriefDescription": "Read Data Buffer Inserts",
231        "Counter": "0,1,2,3",
232        "CounterType": "PGMABLE",
233        "EventCode": "0x17",
234        "EventName": "UNC_M_RDB_INSERTS",
235        "PerPkg": "1",
236        "Unit": "iMC"
237    },
238    {
239        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
240        "Counter": "0,1,2,3",
241        "CounterType": "PGMABLE",
242        "EventCode": "0x04",
243        "EventName": "UNC_M_CAS_COUNT.RD_REG",
244        "PerPkg": "1",
245        "UMask": "0x01",
246        "Unit": "iMC"
247    },
248    {
249        "BriefDescription": "DRAM underfill read CAS commands issued",
250        "Counter": "0,1,2,3",
251        "CounterType": "PGMABLE",
252        "EventCode": "0x04",
253        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
254        "PerPkg": "1",
255        "UMask": "0x04",
256        "Unit": "iMC"
257    },
258    {
259        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
260        "Counter": "0,1,2,3",
261        "CounterType": "PGMABLE",
262        "EventCode": "0x01",
263        "EventName": "UNC_M_ACT_COUNT.BYP",
264        "PerPkg": "1",
265        "UMask": "0x08",
266        "Unit": "iMC"
267    },
268    {
269        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
270        "Counter": "0,1,2,3",
271        "CounterType": "PGMABLE",
272        "EventCode": "0x04",
273        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
274        "PerPkg": "1",
275        "UMask": "0x02",
276        "Unit": "iMC"
277    },
278    {
279        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
280        "Counter": "0,1,2,3",
281        "CounterType": "PGMABLE",
282        "EventCode": "0x04",
283        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
284        "PerPkg": "1",
285        "UMask": "0x08",
286        "Unit": "iMC"
287    },
288    {
289        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
290        "Counter": "0,1,2,3",
291        "CounterType": "PGMABLE",
292        "EventCode": "0x04",
293        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
294        "PerPkg": "1",
295        "UMask": "0x20",
296        "Unit": "iMC"
297    },
298    {
299        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
300        "Counter": "0,1,2,3",
301        "CounterType": "PGMABLE",
302        "EventCode": "0x47",
303        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
304        "PerPkg": "1",
305        "UMask": "0x01",
306        "Unit": "iMC"
307    },
308    {
309        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
310        "Counter": "0,1,2,3",
311        "CounterType": "PGMABLE",
312        "EventCode": "0x47",
313        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
314        "PerPkg": "1",
315        "UMask": "0x02",
316        "Unit": "iMC"
317    },
318    {
319        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
320        "Counter": "0,1,2,3",
321        "CounterType": "PGMABLE",
322        "EventCode": "0x47",
323        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
324        "PerPkg": "1",
325        "UMask": "0x04",
326        "Unit": "iMC"
327    },
328    {
329        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
330        "Counter": "0,1,2,3",
331        "CounterType": "PGMABLE",
332        "EventCode": "0x47",
333        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
334        "PerPkg": "1",
335        "UMask": "0x08",
336        "Unit": "iMC"
337    },
338    {
339        "BriefDescription": "Throttle Cycles for Rank 0",
340        "Counter": "0,1,2,3",
341        "CounterType": "PGMABLE",
342        "EventCode": "0x86",
343        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
344        "PerPkg": "1",
345        "UMask": "0x01",
346        "Unit": "iMC"
347    },
348    {
349        "BriefDescription": "Throttle Cycles for Rank 0",
350        "Counter": "0,1,2,3",
351        "CounterType": "PGMABLE",
352        "EventCode": "0x86",
353        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
354        "PerPkg": "1",
355        "UMask": "0x02",
356        "Unit": "iMC"
357    },
358    {
359        "BriefDescription": "Throttle Cycles for Rank 0",
360        "Counter": "0,1,2,3",
361        "CounterType": "PGMABLE",
362        "EventCode": "0x46",
363        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
364        "PerPkg": "1",
365        "UMask": "0x01",
366        "Unit": "iMC"
367    },
368    {
369        "BriefDescription": "Throttle Cycles for Rank 0",
370        "Counter": "0,1,2,3",
371        "CounterType": "PGMABLE",
372        "EventCode": "0x46",
373        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
374        "PerPkg": "1",
375        "UMask": "0x02",
376        "Unit": "iMC"
377    },
378    {
379        "BriefDescription": "Read Pending Queue Not Empty",
380        "Counter": "0,1,2,3",
381        "CounterType": "PGMABLE",
382        "EventCode": "0x11",
383        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
384        "PerPkg": "1",
385        "UMask": "0x01",
386        "Unit": "iMC"
387    },
388    {
389        "BriefDescription": "Read Pending Queue Not Empty",
390        "Counter": "0,1,2,3",
391        "CounterType": "PGMABLE",
392        "EventCode": "0x11",
393        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
394        "PerPkg": "1",
395        "UMask": "0x02",
396        "Unit": "iMC"
397    },
398    {
399        "BriefDescription": "Write Pending Queue Not Empty",
400        "Counter": "0,1,2,3",
401        "CounterType": "PGMABLE",
402        "EventCode": "0x21",
403        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
404        "PerPkg": "1",
405        "UMask": "0x01",
406        "Unit": "iMC"
407    },
408    {
409        "BriefDescription": "Write Pending Queue Not Empty",
410        "Counter": "0,1,2,3",
411        "CounterType": "PGMABLE",
412        "EventCode": "0x21",
413        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
414        "PerPkg": "1",
415        "UMask": "0x02",
416        "Unit": "iMC"
417    },
418    {
419        "BriefDescription": "Write Pending Queue CAM Match",
420        "Counter": "0,1,2,3",
421        "CounterType": "PGMABLE",
422        "EventCode": "0x23",
423        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
424        "PerPkg": "1",
425        "UMask": "0x01",
426        "Unit": "iMC"
427    },
428    {
429        "BriefDescription": "Write Pending Queue CAM Match",
430        "Counter": "0,1,2,3",
431        "CounterType": "PGMABLE",
432        "EventCode": "0x23",
433        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
434        "PerPkg": "1",
435        "UMask": "0x02",
436        "Unit": "iMC"
437    },
438    {
439        "BriefDescription": "Write Pending Queue CAM Match",
440        "Counter": "0,1,2,3",
441        "CounterType": "PGMABLE",
442        "EventCode": "0x24",
443        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
444        "PerPkg": "1",
445        "UMask": "0x01",
446        "Unit": "iMC"
447    },
448    {
449        "BriefDescription": "Write Pending Queue CAM Match",
450        "Counter": "0,1,2,3",
451        "CounterType": "PGMABLE",
452        "EventCode": "0x24",
453        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
454        "PerPkg": "1",
455        "UMask": "0x02",
456        "Unit": "iMC"
457    },
458    {
459        "BriefDescription": "UNC_M_PCLS.RD",
460        "Counter": "0,1,2,3",
461        "CounterType": "PGMABLE",
462        "EventCode": "0xA0",
463        "EventName": "UNC_M_PCLS.RD",
464        "PerPkg": "1",
465        "UMask": "0x01",
466        "Unit": "iMC"
467    },
468    {
469        "BriefDescription": "UNC_M_PCLS.WR",
470        "Counter": "0,1,2,3",
471        "CounterType": "PGMABLE",
472        "EventCode": "0xA0",
473        "EventName": "UNC_M_PCLS.WR",
474        "PerPkg": "1",
475        "UMask": "0x02",
476        "Unit": "iMC"
477    },
478    {
479        "BriefDescription": "UNC_M_PCLS.TOTAL",
480        "Counter": "0,1,2,3",
481        "CounterType": "PGMABLE",
482        "EventCode": "0xA0",
483        "EventName": "UNC_M_PCLS.TOTAL",
484        "PerPkg": "1",
485        "UMask": "0x04",
486        "Unit": "iMC"
487    },
488    {
489        "BriefDescription": "DRAM Precharge All Commands",
490        "Counter": "0,1,2,3",
491        "CounterType": "PGMABLE",
492        "EventCode": "0x44",
493        "EventName": "UNC_M_DRAM_PRE_ALL",
494        "PerPkg": "1",
495        "Unit": "iMC"
496    },
497    {
498        "BriefDescription": "UNC_M_PARITY_ERRORS",
499        "Counter": "0,1,2,3",
500        "CounterType": "PGMABLE",
501        "EventCode": "0x2c",
502        "EventName": "UNC_M_PARITY_ERRORS",
503        "PerPkg": "1",
504        "Unit": "iMC"
505    },
506    {
507        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
508        "Counter": "0,1,2,3",
509        "CounterType": "PGMABLE",
510        "EventCode": "0x85",
511        "EventName": "UNC_M_POWER_CHANNEL_PPD",
512        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
513        "MetricName": "power_channel_ppd %",
514        "PerPkg": "1",
515        "Unit": "iMC"
516    },
517    {
518        "BriefDescription": "Cycles Memory is in self refresh power mode",
519        "Counter": "0,1,2,3",
520        "CounterType": "PGMABLE",
521        "EventCode": "0x43",
522        "EventName": "UNC_M_POWER_SELF_REFRESH",
523        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
524        "MetricName": "power_self_refresh %",
525        "PerPkg": "1",
526        "Unit": "iMC"
527    },
528    {
529        "BriefDescription": "Read Data Buffer Full",
530        "Counter": "0,1,2,3",
531        "CounterType": "PGMABLE",
532        "EventCode": "0x19",
533        "EventName": "UNC_M_RDB_FULL",
534        "PerPkg": "1",
535        "Unit": "iMC"
536    },
537    {
538        "BriefDescription": "Read Data Buffer Not Empty",
539        "Counter": "0,1,2,3",
540        "CounterType": "PGMABLE",
541        "EventCode": "0x18",
542        "EventName": "UNC_M_RDB_NOT_EMPTY",
543        "PerPkg": "1",
544        "Unit": "iMC"
545    },
546    {
547        "BriefDescription": "Read Data Buffer Occupancy",
548        "Counter": "0,1,2,3",
549        "CounterType": "PGMABLE",
550        "EventCode": "0x1A",
551        "EventName": "UNC_M_RDB_OCCUPANCY",
552        "PerPkg": "1",
553        "Unit": "iMC"
554    },
555    {
556        "BriefDescription": "Read Pending Queue Full Cycles",
557        "Counter": "0,1,2,3",
558        "CounterType": "PGMABLE",
559        "EventCode": "0x12",
560        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
561        "PerPkg": "1",
562        "Unit": "iMC"
563    },
564    {
565        "BriefDescription": "Read Pending Queue Full Cycles",
566        "Counter": "0,1,2,3",
567        "CounterType": "PGMABLE",
568        "EventCode": "0x15",
569        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
570        "PerPkg": "1",
571        "Unit": "iMC"
572    },
573    {
574        "BriefDescription": "Write Pending Queue Full Cycles",
575        "Counter": "0,1,2,3",
576        "CounterType": "PGMABLE",
577        "EventCode": "0x22",
578        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
579        "PerPkg": "1",
580        "Unit": "iMC"
581    },
582    {
583        "BriefDescription": "Write Pending Queue Full Cycles",
584        "Counter": "0,1,2,3",
585        "CounterType": "PGMABLE",
586        "EventCode": "0x16",
587        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
588        "PerPkg": "1",
589        "Unit": "iMC"
590    },
591    {
592        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
593        "Counter": "0,1,2,3",
594        "CounterType": "PGMABLE",
595        "EventCode": "0x04",
596        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
597        "PerPkg": "1",
598        "UMask": "0x10",
599        "Unit": "iMC"
600    },
601    {
602        "BriefDescription": "Pre-charges due to page misses",
603        "Counter": "0,1,2,3",
604        "CounterType": "PGMABLE",
605        "EventCode": "0x02",
606        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
607        "PerPkg": "1",
608        "UMask": "0x0c",
609        "Unit": "iMC"
610    },
611    {
612        "BriefDescription": "Free running counter that increments for the Memory Controller",
613        "Counter": "4",
614        "CounterType": "FREERUN",
615        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
616        "PerPkg": "1",
617        "Unit": "iMC"
618    }
619]
620