1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RISC-V processor specific defines 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 */ 7 #ifndef SELFTEST_KVM_PROCESSOR_H 8 #define SELFTEST_KVM_PROCESSOR_H 9 10 #include "kvm_util.h" 11 #include <linux/stringify.h> 12 13 static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, 14 uint64_t size) 15 { 16 return KVM_REG_RISCV | type | idx | size; 17 } 18 19 #if __riscv_xlen == 64 20 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64 21 #else 22 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 23 #endif 24 25 #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ 26 KVM_REG_RISCV_CONFIG_REG(name), \ 27 KVM_REG_SIZE_ULONG) 28 29 #define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \ 30 KVM_REG_RISCV_CORE_REG(name), \ 31 KVM_REG_SIZE_ULONG) 32 33 #define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ 34 KVM_REG_RISCV_CSR_REG(name), \ 35 KVM_REG_SIZE_ULONG) 36 37 #define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \ 38 KVM_REG_RISCV_TIMER_REG(name), \ 39 KVM_REG_SIZE_U64) 40 41 /* L3 index Bit[47:39] */ 42 #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL 43 #define PGTBL_L3_INDEX_SHIFT 39 44 #define PGTBL_L3_BLOCK_SHIFT 39 45 #define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL 46 #define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1)) 47 /* L2 index Bit[38:30] */ 48 #define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL 49 #define PGTBL_L2_INDEX_SHIFT 30 50 #define PGTBL_L2_BLOCK_SHIFT 30 51 #define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL 52 #define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1)) 53 /* L1 index Bit[29:21] */ 54 #define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL 55 #define PGTBL_L1_INDEX_SHIFT 21 56 #define PGTBL_L1_BLOCK_SHIFT 21 57 #define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL 58 #define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1)) 59 /* L0 index Bit[20:12] */ 60 #define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL 61 #define PGTBL_L0_INDEX_SHIFT 12 62 #define PGTBL_L0_BLOCK_SHIFT 12 63 #define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL 64 #define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1)) 65 66 #define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL 67 #define PGTBL_PTE_ADDR_SHIFT 10 68 #define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL 69 #define PGTBL_PTE_RSW_SHIFT 8 70 #define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL 71 #define PGTBL_PTE_DIRTY_SHIFT 7 72 #define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL 73 #define PGTBL_PTE_ACCESSED_SHIFT 6 74 #define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL 75 #define PGTBL_PTE_GLOBAL_SHIFT 5 76 #define PGTBL_PTE_USER_MASK 0x0000000000000010ULL 77 #define PGTBL_PTE_USER_SHIFT 4 78 #define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL 79 #define PGTBL_PTE_EXECUTE_SHIFT 3 80 #define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL 81 #define PGTBL_PTE_WRITE_SHIFT 2 82 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL 83 #define PGTBL_PTE_READ_SHIFT 1 84 #define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \ 85 PGTBL_PTE_DIRTY_MASK | \ 86 PGTBL_PTE_EXECUTE_MASK | \ 87 PGTBL_PTE_WRITE_MASK | \ 88 PGTBL_PTE_READ_MASK) 89 #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL 90 #define PGTBL_PTE_VALID_SHIFT 0 91 92 #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE 93 #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT 94 95 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 96 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 97 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 98 #define SATP_ASID_BITS 16 99 #define SATP_ASID_SHIFT 44 100 #define SATP_ASID_MASK _AC(0xFFFF, UL) 101 102 #define SBI_EXT_EXPERIMENTAL_START 0x08000000 103 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF 104 105 #define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END 106 #define KVM_RISCV_SELFTESTS_SBI_UCALL 0 107 #define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 108 109 struct sbiret { 110 long error; 111 long value; 112 }; 113 114 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 115 unsigned long arg1, unsigned long arg2, 116 unsigned long arg3, unsigned long arg4, 117 unsigned long arg5); 118 119 #endif /* SELFTEST_KVM_PROCESSOR_H */ 120