1=pod
2
3=head1 NAME
4
5OPENSSL_ia32cap - finding the IA-32 processor capabilities
6
7=head1 SYNOPSIS
8
9 unsigned long *OPENSSL_ia32cap_loc(void);
10 #define OPENSSL_ia32cap (*(OPENSSL_ia32cap_loc()))
11
12=head1 DESCRIPTION
13
14Value returned by OPENSSL_ia32cap_loc() is address of a variable
15containing IA-32 processor capabilities bit vector as it appears in EDX
16register after executing CPUID instruction with EAX=1 input value (see
17Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
18platforms only. The variable is normally set up automatically upon
19toolkit initialization, but can be manipulated afterwards to modify
20crypto library behaviour. For the moment of this writing six bits are
21significant, namely:
22
231. bit #28 denoting Hyperthreading, which is used to distiguish
24   cores with shared cache;
252. bit #26 denoting SSE2 support;
263. bit #25 denoting SSE support;
274. bit #23 denoting MMX support;
285. bit #20, reserved by Intel, is used to choose between RC4 code
29   pathes;
306. bit #4 denoting presence of Time-Stamp Counter.
31
32For example, clearing bit #26 at run-time disables high-performance
33SSE2 code present in the crypto library. You might have to do this if
34target OpenSSL application is executed on SSE2 capable CPU, but under
35control of OS which does not support SSE2 extentions. Even though you
36can manipulate the value programmatically, you most likely will find it
37more appropriate to set up an environment variable with the same name
38prior starting target application, e.g. on Intel P4 processor 'env
39OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
40without modifying the application source code. Alternatively you can
41reconfigure the toolkit with no-sse2 option and recompile.
42
43=cut
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