1 /* $NetBSD: atomic.h,v 1.5 2014/12/10 04:38:00 christos Exp $ */ 2 3 /* 4 * Copyright (C) 2005, 2007 Internet Systems Consortium, Inc. ("ISC") 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH 11 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 12 * AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT, 13 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 14 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE 15 * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Id: atomic.h,v 1.3 2007/06/19 23:47:18 tbox Exp */ 20 21 #ifndef ISC_ATOMIC_H 22 #define ISC_ATOMIC_H 1 23 24 #include <isc/platform.h> 25 #include <isc/types.h> 26 27 #ifdef ISC_PLATFORM_USEGCCASM 28 /* 29 * This routine atomically increments the value stored in 'p' by 'val', and 30 * returns the previous value. 31 */ 32 static __inline isc_int32_t 33 isc_atomic_xadd(isc_int32_t *p, int val) { 34 isc_int32_t orig; 35 36 /* add is a cheat, since MIPS has no mov instruction */ 37 __asm__ volatile ( 38 "1:" 39 "ll $3, %1\n" 40 "add %0, $0, $3\n" 41 "add $3, $3, %2\n" 42 "sc $3, %1\n" 43 "beq $3, 0, 1b" 44 : "=&r"(orig) 45 : "m"(*p), "r"(val) 46 : "memory", "$3" 47 ); 48 49 return (orig); 50 } 51 52 /* 53 * This routine atomically stores the value 'val' in 'p'. 54 */ 55 static __inline void 56 isc_atomic_store(isc_int32_t *p, isc_int32_t val) { 57 __asm__ volatile ( 58 "1:" 59 "ll $3, %0\n" 60 "add $3, $0, %1\n" 61 "sc $3, %0\n" 62 "beq $3, 0, 1b" 63 : 64 : "m"(*p), "r"(val) 65 : "memory", "$3" 66 ); 67 } 68 69 /* 70 * This routine atomically replaces the value in 'p' with 'val', if the 71 * original value is equal to 'cmpval'. The original value is returned in any 72 * case. 73 */ 74 static __inline isc_int32_t 75 isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) { 76 isc_int32_t orig; 77 78 __asm__ volatile( 79 "1:" 80 "ll $3, %1\n" 81 "add %0, $0, $3\n" 82 "bne $3, %2, 2f\n" 83 "add $3, $0, %3\n" 84 "sc $3, %1\n" 85 "beq $3, 0, 1b\n" 86 "2:" 87 : "=&r"(orig) 88 : "m"(*p), "r"(cmpval), "r"(val) 89 : "memory", "$3" 90 ); 91 92 return (orig); 93 } 94 95 #else /* !ISC_PLATFORM_USEGCCASM */ 96 97 #error "unsupported compiler. disable atomic ops by --disable-atomic" 98 99 #endif 100 #endif /* ISC_ATOMIC_H */ 101