1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
DefineStd(MacroBuilder & Builder,StringRef MacroName,const LangOptions & Opts)42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
48 if (Opts.GNUMode)
49 Builder.defineMacro(MacroName);
50
51 // Define __unix.
52 Builder.defineMacro("__" + MacroName);
53
54 // Define __unix__.
55 Builder.defineMacro("__" + MacroName + "__");
56 }
57
defineCPUMacros(MacroBuilder & Builder,StringRef CPUName,bool Tuning=true)58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 bool Tuning = true) {
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
62 if (Tuning)
63 Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
76 public:
OSTargetInfo(const llvm::Triple & Triple)77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82 }
83
84 };
85 } // end anonymous namespace
86
87
getDarwinDefines(MacroBuilder & Builder,const LangOptions & Opts,const llvm::Triple & Triple,StringRef & PlatformName,VersionTuple & PlatformMinVersion)88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
99
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 else
108 Builder.defineMacro("__strong", "");
109
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
114 }
115
116 if (Opts.Static)
117 Builder.defineMacro("__STATIC__");
118 else
119 Builder.defineMacro("__DYNAMIC__");
120
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
123
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
129 } else {
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132 }
133
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139 return;
140 }
141
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145 char Str[6];
146 Str[0] = '0' + Maj;
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
151 Str[5] = '\0';
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153 Str);
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
158 // version.
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 char Str[7];
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
166 Str[4] = '\0';
167 } else {
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
175 Str[6] = '\0';
176 }
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178 }
179
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
183
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186
187 namespace {
188 template<typename Target>
189 class DarwinTargetInfo : public OSTargetInfo<Target> {
190 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192 MacroBuilder &Builder) const override {
193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194 this->PlatformMinVersion);
195 }
196
197 public:
DarwinTargetInfo(const llvm::Triple & Triple)198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200 this->MCountName = "\01mcount";
201 }
202
isValidSectionSpecifier(StringRef SR) const203 std::string isValidSectionSpecifier(StringRef SR) const override {
204 // Let MCSectionMachO validate this.
205 StringRef Segment, Section;
206 unsigned TAA, StubSize;
207 bool HasTAA;
208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209 TAA, HasTAA, StubSize);
210 }
211
getStaticInitSectionSpecifier() const212 const char *getStaticInitSectionSpecifier() const override {
213 // FIXME: We should return 0 when building kexts.
214 return "__TEXT,__StaticInit,regular,pure_instructions";
215 }
216
217 /// Darwin does not support protected visibility. Darwin's "default"
218 /// is very similar to ELF's "protected"; Darwin requires a "weak"
219 /// attribute on declarations that can be dynamically replaced.
hasProtectedVisibility() const220 bool hasProtectedVisibility() const override {
221 return false;
222 }
223 };
224
225
226 // DragonFlyBSD Target
227 template<typename Target>
228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231 MacroBuilder &Builder) const override {
232 // DragonFly defines; list based off of gcc output
233 Builder.defineMacro("__DragonFly__");
234 Builder.defineMacro("__DragonFly_cc_version", "100001");
235 Builder.defineMacro("__ELF__");
236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237 Builder.defineMacro("__tune_i386__");
238 DefineStd(Builder, "unix", Opts);
239 }
240 public:
DragonFlyBSDTargetInfo(const llvm::Triple & Triple)241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242 : OSTargetInfo<Target>(Triple) {
243 this->UserLabelPrefix = "";
244
245 switch (Triple.getArch()) {
246 default:
247 case llvm::Triple::x86:
248 case llvm::Triple::x86_64:
249 this->MCountName = ".mcount";
250 break;
251 }
252 }
253 };
254
255 // FreeBSD Target
256 template<typename Target>
257 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260 MacroBuilder &Builder) const override {
261 // FreeBSD defines; list based off of gcc output
262
263 unsigned Release = Triple.getOSMajorVersion();
264 if (Release == 0U)
265 Release = 8;
266
267 Builder.defineMacro("__FreeBSD__", Twine(Release));
268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270 DefineStd(Builder, "unix", Opts);
271 Builder.defineMacro("__ELF__");
272
273 // On FreeBSD, wchar_t contains the number of the code point as
274 // used by the character set of the locale. These character sets are
275 // not necessarily a superset of ASCII.
276 //
277 // FIXME: This is wrong; the macro refers to the numerical values
278 // of wchar_t *literals*, which are not locale-dependent. However,
279 // FreeBSD systems apparently depend on us getting this wrong, and
280 // setting this to 1 is conforming even if all the basic source
281 // character literals have the same encoding as char and wchar_t.
282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
283 }
284 public:
FreeBSDTargetInfo(const llvm::Triple & Triple)285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
286 this->UserLabelPrefix = "";
287
288 switch (Triple.getArch()) {
289 default:
290 case llvm::Triple::x86:
291 case llvm::Triple::x86_64:
292 this->MCountName = ".mcount";
293 break;
294 case llvm::Triple::mips:
295 case llvm::Triple::mipsel:
296 case llvm::Triple::ppc:
297 case llvm::Triple::ppc64:
298 case llvm::Triple::ppc64le:
299 this->MCountName = "_mcount";
300 break;
301 case llvm::Triple::arm:
302 this->MCountName = "__mcount";
303 break;
304 }
305 }
306 };
307
308 // GNU/kFreeBSD Target
309 template<typename Target>
310 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
311 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
313 MacroBuilder &Builder) const override {
314 // GNU/kFreeBSD defines; list based off of gcc output
315
316 DefineStd(Builder, "unix", Opts);
317 Builder.defineMacro("__FreeBSD_kernel__");
318 Builder.defineMacro("__GLIBC__");
319 Builder.defineMacro("__ELF__");
320 if (Opts.POSIXThreads)
321 Builder.defineMacro("_REENTRANT");
322 if (Opts.CPlusPlus)
323 Builder.defineMacro("_GNU_SOURCE");
324 }
325 public:
KFreeBSDTargetInfo(const llvm::Triple & Triple)326 KFreeBSDTargetInfo(const llvm::Triple &Triple)
327 : OSTargetInfo<Target>(Triple) {
328 this->UserLabelPrefix = "";
329 }
330 };
331
332 // Minix Target
333 template<typename Target>
334 class MinixTargetInfo : public OSTargetInfo<Target> {
335 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
337 MacroBuilder &Builder) const override {
338 // Minix defines; list based off of gcc output
339 Builder.defineMacro("__minix", "3");
340 Builder.defineMacro("__minix__", "3");
341 Builder.defineMacro("__Minix__", "3");
342 Builder.defineMacro("__unix__");
343 Builder.defineMacro("__ELF__");
344 if (Opts.POSIXThreads)
345 Builder.defineMacro("_POSIX_THREADS");
346
347 switch (Triple.getArch()) {
348 default:
349 break;
350 case llvm::Triple::arm:
351 case llvm::Triple::armeb:
352 case llvm::Triple::thumb:
353 case llvm::Triple::thumbeb:
354 Builder.defineMacro("__ARM_DWARF_EH__");
355 break;
356 }
357 }
358 public:
MinixTargetInfo(const llvm::Triple & Triple)359 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
360 this->UserLabelPrefix = "";
361 this->MCountName = "_mcount";
362 }
363 };
364
365 // Linux target
366 template<typename Target>
367 class LinuxTargetInfo : public OSTargetInfo<Target> {
368 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const369 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
370 MacroBuilder &Builder) const override {
371 // Linux defines; list based off of gcc output
372 DefineStd(Builder, "unix", Opts);
373 DefineStd(Builder, "linux", Opts);
374 Builder.defineMacro("__gnu_linux__");
375 Builder.defineMacro("__ELF__");
376 if (Triple.getEnvironment() == llvm::Triple::Android)
377 Builder.defineMacro("__ANDROID__", "1");
378 if (Opts.POSIXThreads)
379 Builder.defineMacro("_REENTRANT");
380 if (Opts.CPlusPlus)
381 Builder.defineMacro("_GNU_SOURCE");
382 }
383 public:
LinuxTargetInfo(const llvm::Triple & Triple)384 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
385 this->UserLabelPrefix = "";
386 this->WIntType = TargetInfo::UnsignedInt;
387
388 switch (Triple.getArch()) {
389 default:
390 break;
391 case llvm::Triple::ppc:
392 case llvm::Triple::ppc64:
393 case llvm::Triple::ppc64le:
394 this->MCountName = "_mcount";
395 break;
396 }
397 }
398
getStaticInitSectionSpecifier() const399 const char *getStaticInitSectionSpecifier() const override {
400 return ".text.startup";
401 }
402 };
403
404 // NetBSD Target
405 template<typename Target>
406 class NetBSDTargetInfo : public OSTargetInfo<Target> {
407 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const408 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
409 MacroBuilder &Builder) const override {
410 // NetBSD defines; list based off of gcc output
411 Builder.defineMacro("__NetBSD__");
412 Builder.defineMacro("__unix__");
413 Builder.defineMacro("__ELF__");
414 if (Opts.POSIXThreads)
415 Builder.defineMacro("_POSIX_THREADS");
416
417 switch (Triple.getArch()) {
418 default:
419 break;
420 case llvm::Triple::arm:
421 case llvm::Triple::armeb:
422 case llvm::Triple::thumb:
423 case llvm::Triple::thumbeb:
424 Builder.defineMacro("__ARM_DWARF_EH__");
425 break;
426 }
427 }
428 public:
NetBSDTargetInfo(const llvm::Triple & Triple)429 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
430 this->UserLabelPrefix = "";
431 this->MCountName = "_mcount";
432 }
433 };
434
435 // OpenBSD Target
436 template<typename Target>
437 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
438 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const439 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
440 MacroBuilder &Builder) const override {
441 // OpenBSD defines; list based off of gcc output
442
443 Builder.defineMacro("__OpenBSD__");
444 DefineStd(Builder, "unix", Opts);
445 Builder.defineMacro("__ELF__");
446 if (Opts.POSIXThreads)
447 Builder.defineMacro("_REENTRANT");
448 }
449 public:
OpenBSDTargetInfo(const llvm::Triple & Triple)450 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
451 this->UserLabelPrefix = "";
452 this->TLSSupported = false;
453
454 switch (Triple.getArch()) {
455 default:
456 case llvm::Triple::x86:
457 case llvm::Triple::x86_64:
458 case llvm::Triple::arm:
459 case llvm::Triple::sparc:
460 this->MCountName = "__mcount";
461 break;
462 case llvm::Triple::mips64:
463 case llvm::Triple::mips64el:
464 case llvm::Triple::ppc:
465 case llvm::Triple::sparcv9:
466 this->MCountName = "_mcount";
467 break;
468 }
469 }
470 };
471
472 // Bitrig Target
473 template<typename Target>
474 class BitrigTargetInfo : public OSTargetInfo<Target> {
475 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const476 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
477 MacroBuilder &Builder) const override {
478 // Bitrig defines; list based off of gcc output
479
480 Builder.defineMacro("__Bitrig__");
481 DefineStd(Builder, "unix", Opts);
482 Builder.defineMacro("__ELF__");
483 if (Opts.POSIXThreads)
484 Builder.defineMacro("_REENTRANT");
485 }
486 public:
BitrigTargetInfo(const llvm::Triple & Triple)487 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
488 this->UserLabelPrefix = "";
489 this->MCountName = "__mcount";
490 }
491 };
492
493 // PSP Target
494 template<typename Target>
495 class PSPTargetInfo : public OSTargetInfo<Target> {
496 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const497 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
498 MacroBuilder &Builder) const override {
499 // PSP defines; list based on the output of the pspdev gcc toolchain.
500 Builder.defineMacro("PSP");
501 Builder.defineMacro("_PSP");
502 Builder.defineMacro("__psp__");
503 Builder.defineMacro("__ELF__");
504 }
505 public:
PSPTargetInfo(const llvm::Triple & Triple)506 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
507 this->UserLabelPrefix = "";
508 }
509 };
510
511 // PS3 PPU Target
512 template<typename Target>
513 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
514 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const515 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516 MacroBuilder &Builder) const override {
517 // PS3 PPU defines.
518 Builder.defineMacro("__PPC__");
519 Builder.defineMacro("__PPU__");
520 Builder.defineMacro("__CELLOS_LV2__");
521 Builder.defineMacro("__ELF__");
522 Builder.defineMacro("__LP32__");
523 Builder.defineMacro("_ARCH_PPC64");
524 Builder.defineMacro("__powerpc64__");
525 }
526 public:
PS3PPUTargetInfo(const llvm::Triple & Triple)527 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
528 this->UserLabelPrefix = "";
529 this->LongWidth = this->LongAlign = 32;
530 this->PointerWidth = this->PointerAlign = 32;
531 this->IntMaxType = TargetInfo::SignedLongLong;
532 this->Int64Type = TargetInfo::SignedLongLong;
533 this->SizeType = TargetInfo::UnsignedInt;
534 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
535 }
536 };
537
538 // Solaris target
539 template<typename Target>
540 class SolarisTargetInfo : public OSTargetInfo<Target> {
541 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const542 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
543 MacroBuilder &Builder) const override {
544 DefineStd(Builder, "sun", Opts);
545 DefineStd(Builder, "unix", Opts);
546 Builder.defineMacro("__ELF__");
547 Builder.defineMacro("__svr4__");
548 Builder.defineMacro("__SVR4");
549 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
550 // newer, but to 500 for everything else. feature_test.h has a check to
551 // ensure that you are not using C99 with an old version of X/Open or C89
552 // with a new version.
553 if (Opts.C99)
554 Builder.defineMacro("_XOPEN_SOURCE", "600");
555 else
556 Builder.defineMacro("_XOPEN_SOURCE", "500");
557 if (Opts.CPlusPlus)
558 Builder.defineMacro("__C99FEATURES__");
559 Builder.defineMacro("_LARGEFILE_SOURCE");
560 Builder.defineMacro("_LARGEFILE64_SOURCE");
561 Builder.defineMacro("__EXTENSIONS__");
562 Builder.defineMacro("_REENTRANT");
563 }
564 public:
SolarisTargetInfo(const llvm::Triple & Triple)565 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
566 this->UserLabelPrefix = "";
567 this->WCharType = this->SignedInt;
568 // FIXME: WIntType should be SignedLong
569 }
570 };
571
572 // Windows target
573 template<typename Target>
574 class WindowsTargetInfo : public OSTargetInfo<Target> {
575 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
577 MacroBuilder &Builder) const override {
578 Builder.defineMacro("_WIN32");
579 }
getVisualStudioDefines(const LangOptions & Opts,MacroBuilder & Builder) const580 void getVisualStudioDefines(const LangOptions &Opts,
581 MacroBuilder &Builder) const {
582 if (Opts.CPlusPlus) {
583 if (Opts.RTTIData)
584 Builder.defineMacro("_CPPRTTI");
585
586 if (Opts.Exceptions)
587 Builder.defineMacro("_CPPUNWIND");
588 }
589
590 if (!Opts.CharIsSigned)
591 Builder.defineMacro("_CHAR_UNSIGNED");
592
593 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
594 // but it works for now.
595 if (Opts.POSIXThreads)
596 Builder.defineMacro("_MT");
597
598 if (Opts.MSCompatibilityVersion) {
599 Builder.defineMacro("_MSC_VER",
600 Twine(Opts.MSCompatibilityVersion / 100000));
601 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
602 // FIXME We cannot encode the revision information into 32-bits
603 Builder.defineMacro("_MSC_BUILD", Twine(1));
604 }
605
606 if (Opts.MicrosoftExt) {
607 Builder.defineMacro("_MSC_EXTENSIONS");
608
609 if (Opts.CPlusPlus11) {
610 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
611 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
612 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
613 }
614 }
615
616 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
617 }
618
619 public:
WindowsTargetInfo(const llvm::Triple & Triple)620 WindowsTargetInfo(const llvm::Triple &Triple)
621 : OSTargetInfo<Target>(Triple) {}
622 };
623
624 template <typename Target>
625 class NaClTargetInfo : public OSTargetInfo<Target> {
626 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
628 MacroBuilder &Builder) const override {
629 if (Opts.POSIXThreads)
630 Builder.defineMacro("_REENTRANT");
631 if (Opts.CPlusPlus)
632 Builder.defineMacro("_GNU_SOURCE");
633
634 DefineStd(Builder, "unix", Opts);
635 Builder.defineMacro("__ELF__");
636 Builder.defineMacro("__native_client__");
637 }
638
639 public:
NaClTargetInfo(const llvm::Triple & Triple)640 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
641 this->UserLabelPrefix = "";
642 this->LongAlign = 32;
643 this->LongWidth = 32;
644 this->PointerAlign = 32;
645 this->PointerWidth = 32;
646 this->IntMaxType = TargetInfo::SignedLongLong;
647 this->Int64Type = TargetInfo::SignedLongLong;
648 this->DoubleAlign = 64;
649 this->LongDoubleWidth = 64;
650 this->LongDoubleAlign = 64;
651 this->LongLongWidth = 64;
652 this->LongLongAlign = 64;
653 this->SizeType = TargetInfo::UnsignedInt;
654 this->PtrDiffType = TargetInfo::SignedInt;
655 this->IntPtrType = TargetInfo::SignedInt;
656 // RegParmMax is inherited from the underlying architecture
657 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
658 if (Triple.getArch() == llvm::Triple::arm) {
659 this->DescriptionString =
660 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
661 } else if (Triple.getArch() == llvm::Triple::x86) {
662 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
663 } else if (Triple.getArch() == llvm::Triple::x86_64) {
664 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
665 } else if (Triple.getArch() == llvm::Triple::mipsel) {
666 // Handled on mips' setDescriptionString.
667 } else {
668 assert(Triple.getArch() == llvm::Triple::le32);
669 this->DescriptionString = "e-p:32:32-i64:64";
670 }
671 }
checkCallingConvention(CallingConv CC) const672 typename Target::CallingConvCheckResult checkCallingConvention(
673 CallingConv CC) const override {
674 return CC == CC_PnaclCall ? Target::CCCR_OK :
675 Target::checkCallingConvention(CC);
676 }
677 };
678 } // end anonymous namespace.
679
680 //===----------------------------------------------------------------------===//
681 // Specific target implementations.
682 //===----------------------------------------------------------------------===//
683
684 namespace {
685 // PPC abstract base class
686 class PPCTargetInfo : public TargetInfo {
687 static const Builtin::Info BuiltinInfo[];
688 static const char * const GCCRegNames[];
689 static const TargetInfo::GCCRegAlias GCCRegAliases[];
690 std::string CPU;
691
692 // Target cpu features.
693 bool HasVSX;
694 bool HasP8Vector;
695
696 protected:
697 std::string ABI;
698
699 public:
PPCTargetInfo(const llvm::Triple & Triple)700 PPCTargetInfo(const llvm::Triple &Triple)
701 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
702 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
703 LongDoubleWidth = LongDoubleAlign = 128;
704 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
705 }
706
707 /// \brief Flags for architecture specific defines.
708 typedef enum {
709 ArchDefineNone = 0,
710 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
711 ArchDefinePpcgr = 1 << 1,
712 ArchDefinePpcsq = 1 << 2,
713 ArchDefine440 = 1 << 3,
714 ArchDefine603 = 1 << 4,
715 ArchDefine604 = 1 << 5,
716 ArchDefinePwr4 = 1 << 6,
717 ArchDefinePwr5 = 1 << 7,
718 ArchDefinePwr5x = 1 << 8,
719 ArchDefinePwr6 = 1 << 9,
720 ArchDefinePwr6x = 1 << 10,
721 ArchDefinePwr7 = 1 << 11,
722 ArchDefinePwr8 = 1 << 12,
723 ArchDefineA2 = 1 << 13,
724 ArchDefineA2q = 1 << 14
725 } ArchDefineTypes;
726
727 // Note: GCC recognizes the following additional cpus:
728 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
729 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
730 // titan, rs64.
setCPU(const std::string & Name)731 bool setCPU(const std::string &Name) override {
732 bool CPUKnown = llvm::StringSwitch<bool>(Name)
733 .Case("generic", true)
734 .Case("440", true)
735 .Case("450", true)
736 .Case("601", true)
737 .Case("602", true)
738 .Case("603", true)
739 .Case("603e", true)
740 .Case("603ev", true)
741 .Case("604", true)
742 .Case("604e", true)
743 .Case("620", true)
744 .Case("630", true)
745 .Case("g3", true)
746 .Case("7400", true)
747 .Case("g4", true)
748 .Case("7450", true)
749 .Case("g4+", true)
750 .Case("750", true)
751 .Case("970", true)
752 .Case("g5", true)
753 .Case("a2", true)
754 .Case("a2q", true)
755 .Case("e500mc", true)
756 .Case("e5500", true)
757 .Case("power3", true)
758 .Case("pwr3", true)
759 .Case("power4", true)
760 .Case("pwr4", true)
761 .Case("power5", true)
762 .Case("pwr5", true)
763 .Case("power5x", true)
764 .Case("pwr5x", true)
765 .Case("power6", true)
766 .Case("pwr6", true)
767 .Case("power6x", true)
768 .Case("pwr6x", true)
769 .Case("power7", true)
770 .Case("pwr7", true)
771 .Case("power8", true)
772 .Case("pwr8", true)
773 .Case("powerpc", true)
774 .Case("ppc", true)
775 .Case("powerpc64", true)
776 .Case("ppc64", true)
777 .Case("powerpc64le", true)
778 .Case("ppc64le", true)
779 .Default(false);
780
781 if (CPUKnown)
782 CPU = Name;
783
784 return CPUKnown;
785 }
786
787
getABI() const788 StringRef getABI() const override { return ABI; }
789
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const790 void getTargetBuiltins(const Builtin::Info *&Records,
791 unsigned &NumRecords) const override {
792 Records = BuiltinInfo;
793 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
794 }
795
isCLZForZeroUndef() const796 bool isCLZForZeroUndef() const override { return false; }
797
798 void getTargetDefines(const LangOptions &Opts,
799 MacroBuilder &Builder) const override;
800
801 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
802
803 bool handleTargetFeatures(std::vector<std::string> &Features,
804 DiagnosticsEngine &Diags) override;
805 bool hasFeature(StringRef Feature) const override;
806
807 void getGCCRegNames(const char * const *&Names,
808 unsigned &NumNames) const override;
809 void getGCCRegAliases(const GCCRegAlias *&Aliases,
810 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const811 bool validateAsmConstraint(const char *&Name,
812 TargetInfo::ConstraintInfo &Info) const override {
813 switch (*Name) {
814 default: return false;
815 case 'O': // Zero
816 break;
817 case 'b': // Base register
818 case 'f': // Floating point register
819 Info.setAllowsRegister();
820 break;
821 // FIXME: The following are added to allow parsing.
822 // I just took a guess at what the actions should be.
823 // Also, is more specific checking needed? I.e. specific registers?
824 case 'd': // Floating point register (containing 64-bit value)
825 case 'v': // Altivec vector register
826 Info.setAllowsRegister();
827 break;
828 case 'w':
829 switch (Name[1]) {
830 case 'd':// VSX vector register to hold vector double data
831 case 'f':// VSX vector register to hold vector float data
832 case 's':// VSX vector register to hold scalar float data
833 case 'a':// Any VSX register
834 case 'c':// An individual CR bit
835 break;
836 default:
837 return false;
838 }
839 Info.setAllowsRegister();
840 Name++; // Skip over 'w'.
841 break;
842 case 'h': // `MQ', `CTR', or `LINK' register
843 case 'q': // `MQ' register
844 case 'c': // `CTR' register
845 case 'l': // `LINK' register
846 case 'x': // `CR' register (condition register) number 0
847 case 'y': // `CR' register (condition register)
848 case 'z': // `XER[CA]' carry bit (part of the XER register)
849 Info.setAllowsRegister();
850 break;
851 case 'I': // Signed 16-bit constant
852 case 'J': // Unsigned 16-bit constant shifted left 16 bits
853 // (use `L' instead for SImode constants)
854 case 'K': // Unsigned 16-bit constant
855 case 'L': // Signed 16-bit constant shifted left 16 bits
856 case 'M': // Constant larger than 31
857 case 'N': // Exact power of 2
858 case 'P': // Constant whose negation is a signed 16-bit constant
859 case 'G': // Floating point constant that can be loaded into a
860 // register with one instruction per word
861 case 'H': // Integer/Floating point constant that can be loaded
862 // into a register using three instructions
863 break;
864 case 'm': // Memory operand. Note that on PowerPC targets, m can
865 // include addresses that update the base register. It
866 // is therefore only safe to use `m' in an asm statement
867 // if that asm statement accesses the operand exactly once.
868 // The asm statement must also use `%U<opno>' as a
869 // placeholder for the "update" flag in the corresponding
870 // load or store instruction. For example:
871 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
872 // is correct but:
873 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
874 // is not. Use es rather than m if you don't want the base
875 // register to be updated.
876 case 'e':
877 if (Name[1] != 's')
878 return false;
879 // es: A "stable" memory operand; that is, one which does not
880 // include any automodification of the base register. Unlike
881 // `m', this constraint can be used in asm statements that
882 // might access the operand several times, or that might not
883 // access it at all.
884 Info.setAllowsMemory();
885 Name++; // Skip over 'e'.
886 break;
887 case 'Q': // Memory operand that is an offset from a register (it is
888 // usually better to use `m' or `es' in asm statements)
889 case 'Z': // Memory operand that is an indexed or indirect from a
890 // register (it is usually better to use `m' or `es' in
891 // asm statements)
892 Info.setAllowsMemory();
893 Info.setAllowsRegister();
894 break;
895 case 'R': // AIX TOC entry
896 case 'a': // Address operand that is an indexed or indirect from a
897 // register (`p' is preferable for asm statements)
898 case 'S': // Constant suitable as a 64-bit mask operand
899 case 'T': // Constant suitable as a 32-bit mask operand
900 case 'U': // System V Release 4 small data area reference
901 case 't': // AND masks that can be performed by two rldic{l, r}
902 // instructions
903 case 'W': // Vector constant that does not require memory
904 case 'j': // Vector constant that is all zeros.
905 break;
906 // End FIXME.
907 }
908 return true;
909 }
convertConstraint(const char * & Constraint) const910 std::string convertConstraint(const char *&Constraint) const override {
911 std::string R;
912 switch (*Constraint) {
913 case 'e':
914 case 'w':
915 // Two-character constraint; add "^" hint for later parsing.
916 R = std::string("^") + std::string(Constraint, 2);
917 Constraint++;
918 break;
919 default:
920 return TargetInfo::convertConstraint(Constraint);
921 }
922 return R;
923 }
getClobbers() const924 const char *getClobbers() const override {
925 return "";
926 }
getEHDataRegisterNumber(unsigned RegNo) const927 int getEHDataRegisterNumber(unsigned RegNo) const override {
928 if (RegNo == 0) return 3;
929 if (RegNo == 1) return 4;
930 return -1;
931 }
932
hasSjLjLowering() const933 bool hasSjLjLowering() const override {
934 return true;
935 }
936 };
937
938 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
939 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
940 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
941 ALL_LANGUAGES },
942 #include "clang/Basic/BuiltinsPPC.def"
943 };
944
945 /// handleTargetFeatures - Perform initialization based on the user
946 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)947 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
948 DiagnosticsEngine &Diags) {
949 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
950 // Ignore disabled features.
951 if (Features[i][0] == '-')
952 continue;
953
954 StringRef Feature = StringRef(Features[i]).substr(1);
955
956 if (Feature == "vsx") {
957 HasVSX = true;
958 continue;
959 }
960
961 if (Feature == "power8-vector") {
962 HasP8Vector = true;
963 continue;
964 }
965
966 // TODO: Finish this list and add an assert that we've handled them
967 // all.
968 }
969
970 return true;
971 }
972
973 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
974 /// #defines that are not tied to a specific subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const975 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
976 MacroBuilder &Builder) const {
977 // Target identification.
978 Builder.defineMacro("__ppc__");
979 Builder.defineMacro("__PPC__");
980 Builder.defineMacro("_ARCH_PPC");
981 Builder.defineMacro("__powerpc__");
982 Builder.defineMacro("__POWERPC__");
983 if (PointerWidth == 64) {
984 Builder.defineMacro("_ARCH_PPC64");
985 Builder.defineMacro("__powerpc64__");
986 Builder.defineMacro("__ppc64__");
987 Builder.defineMacro("__PPC64__");
988 }
989
990 // Target properties.
991 if (getTriple().getArch() == llvm::Triple::ppc64le) {
992 Builder.defineMacro("_LITTLE_ENDIAN");
993 } else {
994 if (getTriple().getOS() != llvm::Triple::NetBSD &&
995 getTriple().getOS() != llvm::Triple::OpenBSD)
996 Builder.defineMacro("_BIG_ENDIAN");
997 }
998
999 // ABI options.
1000 if (ABI == "elfv1")
1001 Builder.defineMacro("_CALL_ELF", "1");
1002 if (ABI == "elfv2")
1003 Builder.defineMacro("_CALL_ELF", "2");
1004
1005 // Subtarget options.
1006 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1007 Builder.defineMacro("__REGISTER_PREFIX__", "");
1008
1009 // FIXME: Should be controlled by command line option.
1010 if (LongDoubleWidth == 128)
1011 Builder.defineMacro("__LONG_DOUBLE_128__");
1012
1013 if (Opts.AltiVec) {
1014 Builder.defineMacro("__VEC__", "10206");
1015 Builder.defineMacro("__ALTIVEC__");
1016 }
1017
1018 // CPU identification.
1019 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1020 .Case("440", ArchDefineName)
1021 .Case("450", ArchDefineName | ArchDefine440)
1022 .Case("601", ArchDefineName)
1023 .Case("602", ArchDefineName | ArchDefinePpcgr)
1024 .Case("603", ArchDefineName | ArchDefinePpcgr)
1025 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1026 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1027 .Case("604", ArchDefineName | ArchDefinePpcgr)
1028 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1029 .Case("620", ArchDefineName | ArchDefinePpcgr)
1030 .Case("630", ArchDefineName | ArchDefinePpcgr)
1031 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1032 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1033 .Case("750", ArchDefineName | ArchDefinePpcgr)
1034 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1035 | ArchDefinePpcsq)
1036 .Case("a2", ArchDefineA2)
1037 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1038 .Case("pwr3", ArchDefinePpcgr)
1039 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1040 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1041 | ArchDefinePpcsq)
1042 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1043 | ArchDefinePpcgr | ArchDefinePpcsq)
1044 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1045 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1046 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1047 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1048 | ArchDefinePpcsq)
1049 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1050 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1051 | ArchDefinePpcgr | ArchDefinePpcsq)
1052 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1053 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1054 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1055 .Case("power3", ArchDefinePpcgr)
1056 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1057 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1058 | ArchDefinePpcsq)
1059 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1060 | ArchDefinePpcgr | ArchDefinePpcsq)
1061 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1063 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1064 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1065 | ArchDefinePpcsq)
1066 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1067 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1068 | ArchDefinePpcgr | ArchDefinePpcsq)
1069 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1070 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1071 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1072 .Default(ArchDefineNone);
1073
1074 if (defs & ArchDefineName)
1075 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1076 if (defs & ArchDefinePpcgr)
1077 Builder.defineMacro("_ARCH_PPCGR");
1078 if (defs & ArchDefinePpcsq)
1079 Builder.defineMacro("_ARCH_PPCSQ");
1080 if (defs & ArchDefine440)
1081 Builder.defineMacro("_ARCH_440");
1082 if (defs & ArchDefine603)
1083 Builder.defineMacro("_ARCH_603");
1084 if (defs & ArchDefine604)
1085 Builder.defineMacro("_ARCH_604");
1086 if (defs & ArchDefinePwr4)
1087 Builder.defineMacro("_ARCH_PWR4");
1088 if (defs & ArchDefinePwr5)
1089 Builder.defineMacro("_ARCH_PWR5");
1090 if (defs & ArchDefinePwr5x)
1091 Builder.defineMacro("_ARCH_PWR5X");
1092 if (defs & ArchDefinePwr6)
1093 Builder.defineMacro("_ARCH_PWR6");
1094 if (defs & ArchDefinePwr6x)
1095 Builder.defineMacro("_ARCH_PWR6X");
1096 if (defs & ArchDefinePwr7)
1097 Builder.defineMacro("_ARCH_PWR7");
1098 if (defs & ArchDefinePwr8)
1099 Builder.defineMacro("_ARCH_PWR8");
1100 if (defs & ArchDefineA2)
1101 Builder.defineMacro("_ARCH_A2");
1102 if (defs & ArchDefineA2q) {
1103 Builder.defineMacro("_ARCH_A2Q");
1104 Builder.defineMacro("_ARCH_QP");
1105 }
1106
1107 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1108 Builder.defineMacro("__bg__");
1109 Builder.defineMacro("__THW_BLUEGENE__");
1110 Builder.defineMacro("__bgq__");
1111 Builder.defineMacro("__TOS_BGQ__");
1112 }
1113
1114 if (HasVSX)
1115 Builder.defineMacro("__VSX__");
1116 if (HasP8Vector)
1117 Builder.defineMacro("__POWER8_VECTOR__");
1118
1119 // FIXME: The following are not yet generated here by Clang, but are
1120 // generated by GCC:
1121 //
1122 // _SOFT_FLOAT_
1123 // __RECIP_PRECISION__
1124 // __APPLE_ALTIVEC__
1125 // __RECIP__
1126 // __RECIPF__
1127 // __RSQRTE__
1128 // __RSQRTEF__
1129 // _SOFT_DOUBLE_
1130 // __NO_LWSYNC__
1131 // __HAVE_BSWAP__
1132 // __LONGDOUBLE128
1133 // __CMODEL_MEDIUM__
1134 // __CMODEL_LARGE__
1135 // _CALL_SYSV
1136 // _CALL_DARWIN
1137 // __NO_FPRS__
1138 }
1139
getDefaultFeatures(llvm::StringMap<bool> & Features) const1140 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1141 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1142 .Case("7400", true)
1143 .Case("g4", true)
1144 .Case("7450", true)
1145 .Case("g4+", true)
1146 .Case("970", true)
1147 .Case("g5", true)
1148 .Case("pwr6", true)
1149 .Case("pwr7", true)
1150 .Case("pwr8", true)
1151 .Case("ppc64", true)
1152 .Case("ppc64le", true)
1153 .Default(false);
1154
1155 Features["qpx"] = (CPU == "a2q");
1156
1157 if (!ABI.empty())
1158 Features[ABI] = true;
1159 }
1160
hasFeature(StringRef Feature) const1161 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1162 return llvm::StringSwitch<bool>(Feature)
1163 .Case("powerpc", true)
1164 .Case("vsx", HasVSX)
1165 .Case("power8-vector", HasP8Vector)
1166 .Default(false);
1167 }
1168
1169 const char * const PPCTargetInfo::GCCRegNames[] = {
1170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1172 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1173 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1174 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1175 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1176 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1177 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1178 "mq", "lr", "ctr", "ap",
1179 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1180 "xer",
1181 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1182 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1183 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1184 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1185 "vrsave", "vscr",
1186 "spe_acc", "spefscr",
1187 "sfp"
1188 };
1189
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1190 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1191 unsigned &NumNames) const {
1192 Names = GCCRegNames;
1193 NumNames = llvm::array_lengthof(GCCRegNames);
1194 }
1195
1196 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1197 // While some of these aliases do map to different registers
1198 // they still share the same register name.
1199 { { "0" }, "r0" },
1200 { { "1"}, "r1" },
1201 { { "2" }, "r2" },
1202 { { "3" }, "r3" },
1203 { { "4" }, "r4" },
1204 { { "5" }, "r5" },
1205 { { "6" }, "r6" },
1206 { { "7" }, "r7" },
1207 { { "8" }, "r8" },
1208 { { "9" }, "r9" },
1209 { { "10" }, "r10" },
1210 { { "11" }, "r11" },
1211 { { "12" }, "r12" },
1212 { { "13" }, "r13" },
1213 { { "14" }, "r14" },
1214 { { "15" }, "r15" },
1215 { { "16" }, "r16" },
1216 { { "17" }, "r17" },
1217 { { "18" }, "r18" },
1218 { { "19" }, "r19" },
1219 { { "20" }, "r20" },
1220 { { "21" }, "r21" },
1221 { { "22" }, "r22" },
1222 { { "23" }, "r23" },
1223 { { "24" }, "r24" },
1224 { { "25" }, "r25" },
1225 { { "26" }, "r26" },
1226 { { "27" }, "r27" },
1227 { { "28" }, "r28" },
1228 { { "29" }, "r29" },
1229 { { "30" }, "r30" },
1230 { { "31" }, "r31" },
1231 { { "fr0" }, "f0" },
1232 { { "fr1" }, "f1" },
1233 { { "fr2" }, "f2" },
1234 { { "fr3" }, "f3" },
1235 { { "fr4" }, "f4" },
1236 { { "fr5" }, "f5" },
1237 { { "fr6" }, "f6" },
1238 { { "fr7" }, "f7" },
1239 { { "fr8" }, "f8" },
1240 { { "fr9" }, "f9" },
1241 { { "fr10" }, "f10" },
1242 { { "fr11" }, "f11" },
1243 { { "fr12" }, "f12" },
1244 { { "fr13" }, "f13" },
1245 { { "fr14" }, "f14" },
1246 { { "fr15" }, "f15" },
1247 { { "fr16" }, "f16" },
1248 { { "fr17" }, "f17" },
1249 { { "fr18" }, "f18" },
1250 { { "fr19" }, "f19" },
1251 { { "fr20" }, "f20" },
1252 { { "fr21" }, "f21" },
1253 { { "fr22" }, "f22" },
1254 { { "fr23" }, "f23" },
1255 { { "fr24" }, "f24" },
1256 { { "fr25" }, "f25" },
1257 { { "fr26" }, "f26" },
1258 { { "fr27" }, "f27" },
1259 { { "fr28" }, "f28" },
1260 { { "fr29" }, "f29" },
1261 { { "fr30" }, "f30" },
1262 { { "fr31" }, "f31" },
1263 { { "cc" }, "cr0" },
1264 };
1265
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1266 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1267 unsigned &NumAliases) const {
1268 Aliases = GCCRegAliases;
1269 NumAliases = llvm::array_lengthof(GCCRegAliases);
1270 }
1271 } // end anonymous namespace.
1272
1273 namespace {
1274 class PPC32TargetInfo : public PPCTargetInfo {
1275 public:
PPC32TargetInfo(const llvm::Triple & Triple)1276 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1277 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1278
1279 switch (getTriple().getOS()) {
1280 case llvm::Triple::Linux:
1281 case llvm::Triple::FreeBSD:
1282 case llvm::Triple::NetBSD:
1283 SizeType = UnsignedInt;
1284 PtrDiffType = SignedInt;
1285 IntPtrType = SignedInt;
1286 break;
1287 default:
1288 break;
1289 }
1290
1291 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1292 LongDoubleWidth = LongDoubleAlign = 64;
1293 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1294 }
1295
1296 // PPC32 supports atomics up to 4 bytes.
1297 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1298 }
1299
getBuiltinVaListKind() const1300 BuiltinVaListKind getBuiltinVaListKind() const override {
1301 // This is the ELF definition, and is overridden by the Darwin sub-target
1302 return TargetInfo::PowerABIBuiltinVaList;
1303 }
1304 };
1305 } // end anonymous namespace.
1306
1307 // Note: ABI differences may eventually require us to have a separate
1308 // TargetInfo for little endian.
1309 namespace {
1310 class PPC64TargetInfo : public PPCTargetInfo {
1311 public:
PPC64TargetInfo(const llvm::Triple & Triple)1312 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1313 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1314 IntMaxType = SignedLong;
1315 Int64Type = SignedLong;
1316
1317 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1318 DescriptionString = "e-m:e-i64:64-n32:64";
1319 ABI = "elfv2";
1320 } else {
1321 DescriptionString = "E-m:e-i64:64-n32:64";
1322 ABI = "elfv1";
1323 }
1324
1325 switch (getTriple().getOS()) {
1326 case llvm::Triple::FreeBSD:
1327 LongDoubleWidth = LongDoubleAlign = 64;
1328 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1329 break;
1330 case llvm::Triple::NetBSD:
1331 IntMaxType = SignedLongLong;
1332 Int64Type = SignedLongLong;
1333 break;
1334 default:
1335 break;
1336 }
1337
1338 // PPC64 supports atomics up to 8 bytes.
1339 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1340 }
getBuiltinVaListKind() const1341 BuiltinVaListKind getBuiltinVaListKind() const override {
1342 return TargetInfo::CharPtrBuiltinVaList;
1343 }
1344 // PPC64 Linux-specifc ABI options.
setABI(const std::string & Name)1345 bool setABI(const std::string &Name) override {
1346 if (Name == "elfv1" || Name == "elfv2") {
1347 ABI = Name;
1348 return true;
1349 }
1350 return false;
1351 }
1352 };
1353 } // end anonymous namespace.
1354
1355
1356 namespace {
1357 class DarwinPPC32TargetInfo :
1358 public DarwinTargetInfo<PPC32TargetInfo> {
1359 public:
DarwinPPC32TargetInfo(const llvm::Triple & Triple)1360 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1361 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1362 HasAlignMac68kSupport = true;
1363 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1364 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1365 LongLongAlign = 32;
1366 SuitableAlign = 128;
1367 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1368 }
getBuiltinVaListKind() const1369 BuiltinVaListKind getBuiltinVaListKind() const override {
1370 return TargetInfo::CharPtrBuiltinVaList;
1371 }
1372 };
1373
1374 class DarwinPPC64TargetInfo :
1375 public DarwinTargetInfo<PPC64TargetInfo> {
1376 public:
DarwinPPC64TargetInfo(const llvm::Triple & Triple)1377 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1378 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1379 HasAlignMac68kSupport = true;
1380 SuitableAlign = 128;
1381 DescriptionString = "E-m:o-i64:64-n32:64";
1382 }
1383 };
1384 } // end anonymous namespace.
1385
1386 namespace {
1387 static const unsigned NVPTXAddrSpaceMap[] = {
1388 1, // opencl_global
1389 3, // opencl_local
1390 4, // opencl_constant
1391 // FIXME: generic has to be added to the target
1392 0, // opencl_generic
1393 1, // cuda_device
1394 4, // cuda_constant
1395 3, // cuda_shared
1396 };
1397 class NVPTXTargetInfo : public TargetInfo {
1398 static const char * const GCCRegNames[];
1399 static const Builtin::Info BuiltinInfo[];
1400
1401 // The GPU profiles supported by the NVPTX backend
1402 enum GPUKind {
1403 GK_NONE,
1404 GK_SM20,
1405 GK_SM21,
1406 GK_SM30,
1407 GK_SM35,
1408 } GPU;
1409
1410 public:
NVPTXTargetInfo(const llvm::Triple & Triple)1411 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1412 BigEndian = false;
1413 TLSSupported = false;
1414 LongWidth = LongAlign = 64;
1415 AddrSpaceMap = &NVPTXAddrSpaceMap;
1416 UseAddrSpaceMapMangling = true;
1417 // Define available target features
1418 // These must be defined in sorted order!
1419 NoAsmVariants = true;
1420 // Set the default GPU to sm20
1421 GPU = GK_SM20;
1422 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const1423 void getTargetDefines(const LangOptions &Opts,
1424 MacroBuilder &Builder) const override {
1425 Builder.defineMacro("__PTX__");
1426 Builder.defineMacro("__NVPTX__");
1427 if (Opts.CUDAIsDevice) {
1428 // Set __CUDA_ARCH__ for the GPU specified.
1429 std::string CUDAArchCode;
1430 switch (GPU) {
1431 case GK_SM20:
1432 CUDAArchCode = "200";
1433 break;
1434 case GK_SM21:
1435 CUDAArchCode = "210";
1436 break;
1437 case GK_SM30:
1438 CUDAArchCode = "300";
1439 break;
1440 case GK_SM35:
1441 CUDAArchCode = "350";
1442 break;
1443 default:
1444 llvm_unreachable("Unhandled target CPU");
1445 }
1446 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1447 }
1448 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const1449 void getTargetBuiltins(const Builtin::Info *&Records,
1450 unsigned &NumRecords) const override {
1451 Records = BuiltinInfo;
1452 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1453 }
hasFeature(StringRef Feature) const1454 bool hasFeature(StringRef Feature) const override {
1455 return Feature == "ptx" || Feature == "nvptx";
1456 }
1457
1458 void getGCCRegNames(const char * const *&Names,
1459 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1460 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1461 unsigned &NumAliases) const override {
1462 // No aliases.
1463 Aliases = nullptr;
1464 NumAliases = 0;
1465 }
1466 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const1467 validateAsmConstraint(const char *&Name,
1468 TargetInfo::ConstraintInfo &Info) const override {
1469 switch (*Name) {
1470 default: return false;
1471 case 'c':
1472 case 'h':
1473 case 'r':
1474 case 'l':
1475 case 'f':
1476 case 'd':
1477 Info.setAllowsRegister();
1478 return true;
1479 }
1480 }
getClobbers() const1481 const char *getClobbers() const override {
1482 // FIXME: Is this really right?
1483 return "";
1484 }
getBuiltinVaListKind() const1485 BuiltinVaListKind getBuiltinVaListKind() const override {
1486 // FIXME: implement
1487 return TargetInfo::CharPtrBuiltinVaList;
1488 }
setCPU(const std::string & Name)1489 bool setCPU(const std::string &Name) override {
1490 GPU = llvm::StringSwitch<GPUKind>(Name)
1491 .Case("sm_20", GK_SM20)
1492 .Case("sm_21", GK_SM21)
1493 .Case("sm_30", GK_SM30)
1494 .Case("sm_35", GK_SM35)
1495 .Default(GK_NONE);
1496
1497 return GPU != GK_NONE;
1498 }
1499 };
1500
1501 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1502 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1503 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1504 ALL_LANGUAGES },
1505 #include "clang/Basic/BuiltinsNVPTX.def"
1506 };
1507
1508 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1509 "r0"
1510 };
1511
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1512 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1513 unsigned &NumNames) const {
1514 Names = GCCRegNames;
1515 NumNames = llvm::array_lengthof(GCCRegNames);
1516 }
1517
1518 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1519 public:
NVPTX32TargetInfo(const llvm::Triple & Triple)1520 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1521 PointerWidth = PointerAlign = 32;
1522 SizeType = PtrDiffType = TargetInfo::UnsignedInt;
1523 IntPtrType = TargetInfo::SignedInt;
1524 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1525 }
1526 };
1527
1528 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1529 public:
NVPTX64TargetInfo(const llvm::Triple & Triple)1530 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1531 PointerWidth = PointerAlign = 64;
1532 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
1533 IntPtrType = TargetInfo::SignedLongLong;
1534 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1535 }
1536 };
1537 }
1538
1539 namespace {
1540
1541 static const unsigned R600AddrSpaceMap[] = {
1542 1, // opencl_global
1543 3, // opencl_local
1544 2, // opencl_constant
1545 4, // opencl_generic
1546 1, // cuda_device
1547 2, // cuda_constant
1548 3 // cuda_shared
1549 };
1550
1551 // If you edit the description strings, make sure you update
1552 // getPointerWidthV().
1553
1554 static const char *DescriptionStringR600 =
1555 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1556 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1557
1558 static const char *DescriptionStringR600DoubleOps =
1559 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1560 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1561
1562 static const char *DescriptionStringSI =
1563 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1564 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1565 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1566
1567 class R600TargetInfo : public TargetInfo {
1568 static const Builtin::Info BuiltinInfo[];
1569
1570 /// \brief The GPU profiles supported by the R600 target.
1571 enum GPUKind {
1572 GK_NONE,
1573 GK_R600,
1574 GK_R600_DOUBLE_OPS,
1575 GK_R700,
1576 GK_R700_DOUBLE_OPS,
1577 GK_EVERGREEN,
1578 GK_EVERGREEN_DOUBLE_OPS,
1579 GK_NORTHERN_ISLANDS,
1580 GK_CAYMAN,
1581 GK_SOUTHERN_ISLANDS,
1582 GK_SEA_ISLANDS
1583 } GPU;
1584
1585 public:
R600TargetInfo(const llvm::Triple & Triple)1586 R600TargetInfo(const llvm::Triple &Triple)
1587 : TargetInfo(Triple), GPU(GK_R600) {
1588 DescriptionString = DescriptionStringR600;
1589 AddrSpaceMap = &R600AddrSpaceMap;
1590 UseAddrSpaceMapMangling = true;
1591 }
1592
getPointerWidthV(unsigned AddrSpace) const1593 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1594 if (GPU <= GK_CAYMAN)
1595 return 32;
1596
1597 switch(AddrSpace) {
1598 default:
1599 return 64;
1600 case 0:
1601 case 3:
1602 case 5:
1603 return 32;
1604 }
1605 }
1606
getClobbers() const1607 const char * getClobbers() const override {
1608 return "";
1609 }
1610
getGCCRegNames(const char * const * & Names,unsigned & numNames) const1611 void getGCCRegNames(const char * const *&Names,
1612 unsigned &numNames) const override {
1613 Names = nullptr;
1614 numNames = 0;
1615 }
1616
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1617 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1618 unsigned &NumAliases) const override {
1619 Aliases = nullptr;
1620 NumAliases = 0;
1621 }
1622
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const1623 bool validateAsmConstraint(const char *&Name,
1624 TargetInfo::ConstraintInfo &info) const override {
1625 return true;
1626 }
1627
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const1628 void getTargetBuiltins(const Builtin::Info *&Records,
1629 unsigned &NumRecords) const override {
1630 Records = BuiltinInfo;
1631 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1632 }
1633
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const1634 void getTargetDefines(const LangOptions &Opts,
1635 MacroBuilder &Builder) const override {
1636 Builder.defineMacro("__R600__");
1637 }
1638
getBuiltinVaListKind() const1639 BuiltinVaListKind getBuiltinVaListKind() const override {
1640 return TargetInfo::CharPtrBuiltinVaList;
1641 }
1642
setCPU(const std::string & Name)1643 bool setCPU(const std::string &Name) override {
1644 GPU = llvm::StringSwitch<GPUKind>(Name)
1645 .Case("r600" , GK_R600)
1646 .Case("rv610", GK_R600)
1647 .Case("rv620", GK_R600)
1648 .Case("rv630", GK_R600)
1649 .Case("rv635", GK_R600)
1650 .Case("rs780", GK_R600)
1651 .Case("rs880", GK_R600)
1652 .Case("rv670", GK_R600_DOUBLE_OPS)
1653 .Case("rv710", GK_R700)
1654 .Case("rv730", GK_R700)
1655 .Case("rv740", GK_R700_DOUBLE_OPS)
1656 .Case("rv770", GK_R700_DOUBLE_OPS)
1657 .Case("palm", GK_EVERGREEN)
1658 .Case("cedar", GK_EVERGREEN)
1659 .Case("sumo", GK_EVERGREEN)
1660 .Case("sumo2", GK_EVERGREEN)
1661 .Case("redwood", GK_EVERGREEN)
1662 .Case("juniper", GK_EVERGREEN)
1663 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1664 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1665 .Case("barts", GK_NORTHERN_ISLANDS)
1666 .Case("turks", GK_NORTHERN_ISLANDS)
1667 .Case("caicos", GK_NORTHERN_ISLANDS)
1668 .Case("cayman", GK_CAYMAN)
1669 .Case("aruba", GK_CAYMAN)
1670 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1671 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1672 .Case("verde", GK_SOUTHERN_ISLANDS)
1673 .Case("oland", GK_SOUTHERN_ISLANDS)
1674 .Case("hainan", GK_SOUTHERN_ISLANDS)
1675 .Case("bonaire", GK_SEA_ISLANDS)
1676 .Case("kabini", GK_SEA_ISLANDS)
1677 .Case("kaveri", GK_SEA_ISLANDS)
1678 .Case("hawaii", GK_SEA_ISLANDS)
1679 .Case("mullins", GK_SEA_ISLANDS)
1680 .Default(GK_NONE);
1681
1682 if (GPU == GK_NONE) {
1683 return false;
1684 }
1685
1686 // Set the correct data layout
1687 switch (GPU) {
1688 case GK_NONE:
1689 case GK_R600:
1690 case GK_R700:
1691 case GK_EVERGREEN:
1692 case GK_NORTHERN_ISLANDS:
1693 DescriptionString = DescriptionStringR600;
1694 break;
1695 case GK_R600_DOUBLE_OPS:
1696 case GK_R700_DOUBLE_OPS:
1697 case GK_EVERGREEN_DOUBLE_OPS:
1698 case GK_CAYMAN:
1699 DescriptionString = DescriptionStringR600DoubleOps;
1700 break;
1701 case GK_SOUTHERN_ISLANDS:
1702 case GK_SEA_ISLANDS:
1703 DescriptionString = DescriptionStringSI;
1704 break;
1705 }
1706
1707 return true;
1708 }
1709 };
1710
1711 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1712 #define BUILTIN(ID, TYPE, ATTRS) \
1713 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1714 #include "clang/Basic/BuiltinsR600.def"
1715 };
1716
1717 } // end anonymous namespace
1718
1719 namespace {
1720 // Namespace for x86 abstract base class
1721 const Builtin::Info BuiltinInfo[] = {
1722 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1723 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1724 ALL_LANGUAGES },
1725 #include "clang/Basic/BuiltinsX86.def"
1726 };
1727
1728 static const char* const GCCRegNames[] = {
1729 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1730 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1731 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1732 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1733 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1734 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1735 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1736 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1737 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1738 };
1739
1740 const TargetInfo::AddlRegName AddlRegNames[] = {
1741 { { "al", "ah", "eax", "rax" }, 0 },
1742 { { "bl", "bh", "ebx", "rbx" }, 3 },
1743 { { "cl", "ch", "ecx", "rcx" }, 2 },
1744 { { "dl", "dh", "edx", "rdx" }, 1 },
1745 { { "esi", "rsi" }, 4 },
1746 { { "edi", "rdi" }, 5 },
1747 { { "esp", "rsp" }, 7 },
1748 { { "ebp", "rbp" }, 6 },
1749 };
1750
1751 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1752 // most of the implementation can be shared.
1753 class X86TargetInfo : public TargetInfo {
1754 enum X86SSEEnum {
1755 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1756 } SSELevel;
1757 enum MMX3DNowEnum {
1758 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1759 } MMX3DNowLevel;
1760 enum XOPEnum {
1761 NoXOP,
1762 SSE4A,
1763 FMA4,
1764 XOP
1765 } XOPLevel;
1766
1767 bool HasAES;
1768 bool HasPCLMUL;
1769 bool HasLZCNT;
1770 bool HasRDRND;
1771 bool HasFSGSBASE;
1772 bool HasBMI;
1773 bool HasBMI2;
1774 bool HasPOPCNT;
1775 bool HasRTM;
1776 bool HasPRFCHW;
1777 bool HasRDSEED;
1778 bool HasADX;
1779 bool HasTBM;
1780 bool HasFMA;
1781 bool HasF16C;
1782 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1783 HasAVX512VL;
1784 bool HasSHA;
1785 bool HasCX16;
1786
1787 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1788 ///
1789 /// Each enumeration represents a particular CPU supported by Clang. These
1790 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1791 enum CPUKind {
1792 CK_Generic,
1793
1794 /// \name i386
1795 /// i386-generation processors.
1796 //@{
1797 CK_i386,
1798 //@}
1799
1800 /// \name i486
1801 /// i486-generation processors.
1802 //@{
1803 CK_i486,
1804 CK_WinChipC6,
1805 CK_WinChip2,
1806 CK_C3,
1807 //@}
1808
1809 /// \name i586
1810 /// i586-generation processors, P5 microarchitecture based.
1811 //@{
1812 CK_i586,
1813 CK_Pentium,
1814 CK_PentiumMMX,
1815 //@}
1816
1817 /// \name i686
1818 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1819 //@{
1820 CK_i686,
1821 CK_PentiumPro,
1822 CK_Pentium2,
1823 CK_Pentium3,
1824 CK_Pentium3M,
1825 CK_PentiumM,
1826 CK_C3_2,
1827
1828 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1829 /// Clang however has some logic to suport this.
1830 // FIXME: Warn, deprecate, and potentially remove this.
1831 CK_Yonah,
1832 //@}
1833
1834 /// \name Netburst
1835 /// Netburst microarchitecture based processors.
1836 //@{
1837 CK_Pentium4,
1838 CK_Pentium4M,
1839 CK_Prescott,
1840 CK_Nocona,
1841 //@}
1842
1843 /// \name Core
1844 /// Core microarchitecture based processors.
1845 //@{
1846 CK_Core2,
1847
1848 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1849 /// codename which GCC no longer accepts as an option to -march, but Clang
1850 /// has some logic for recognizing it.
1851 // FIXME: Warn, deprecate, and potentially remove this.
1852 CK_Penryn,
1853 //@}
1854
1855 /// \name Atom
1856 /// Atom processors
1857 //@{
1858 CK_Bonnell,
1859 CK_Silvermont,
1860 //@}
1861
1862 /// \name Nehalem
1863 /// Nehalem microarchitecture based processors.
1864 CK_Nehalem,
1865
1866 /// \name Westmere
1867 /// Westmere microarchitecture based processors.
1868 CK_Westmere,
1869
1870 /// \name Sandy Bridge
1871 /// Sandy Bridge microarchitecture based processors.
1872 CK_SandyBridge,
1873
1874 /// \name Ivy Bridge
1875 /// Ivy Bridge microarchitecture based processors.
1876 CK_IvyBridge,
1877
1878 /// \name Haswell
1879 /// Haswell microarchitecture based processors.
1880 CK_Haswell,
1881
1882 /// \name Broadwell
1883 /// Broadwell microarchitecture based processors.
1884 CK_Broadwell,
1885
1886 /// \name Skylake
1887 /// Skylake microarchitecture based processors.
1888 CK_Skylake,
1889
1890 /// \name Knights Landing
1891 /// Knights Landing processor.
1892 CK_KNL,
1893
1894 /// \name K6
1895 /// K6 architecture processors.
1896 //@{
1897 CK_K6,
1898 CK_K6_2,
1899 CK_K6_3,
1900 //@}
1901
1902 /// \name K7
1903 /// K7 architecture processors.
1904 //@{
1905 CK_Athlon,
1906 CK_AthlonThunderbird,
1907 CK_Athlon4,
1908 CK_AthlonXP,
1909 CK_AthlonMP,
1910 //@}
1911
1912 /// \name K8
1913 /// K8 architecture processors.
1914 //@{
1915 CK_Athlon64,
1916 CK_Athlon64SSE3,
1917 CK_AthlonFX,
1918 CK_K8,
1919 CK_K8SSE3,
1920 CK_Opteron,
1921 CK_OpteronSSE3,
1922 CK_AMDFAM10,
1923 //@}
1924
1925 /// \name Bobcat
1926 /// Bobcat architecture processors.
1927 //@{
1928 CK_BTVER1,
1929 CK_BTVER2,
1930 //@}
1931
1932 /// \name Bulldozer
1933 /// Bulldozer architecture processors.
1934 //@{
1935 CK_BDVER1,
1936 CK_BDVER2,
1937 CK_BDVER3,
1938 CK_BDVER4,
1939 //@}
1940
1941 /// This specification is deprecated and will be removed in the future.
1942 /// Users should prefer \see CK_K8.
1943 // FIXME: Warn on this when the CPU is set to it.
1944 //@{
1945 CK_x86_64,
1946 //@}
1947
1948 /// \name Geode
1949 /// Geode processors.
1950 //@{
1951 CK_Geode
1952 //@}
1953 } CPU;
1954
1955 enum FPMathKind {
1956 FP_Default,
1957 FP_SSE,
1958 FP_387
1959 } FPMath;
1960
1961 public:
X86TargetInfo(const llvm::Triple & Triple)1962 X86TargetInfo(const llvm::Triple &Triple)
1963 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1964 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1965 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1966 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1967 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1968 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1969 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1970 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1971 BigEndian = false;
1972 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1973 }
getFloatEvalMethod() const1974 unsigned getFloatEvalMethod() const override {
1975 // X87 evaluates with 80 bits "long double" precision.
1976 return SSELevel == NoSSE ? 2 : 0;
1977 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const1978 void getTargetBuiltins(const Builtin::Info *&Records,
1979 unsigned &NumRecords) const override {
1980 Records = BuiltinInfo;
1981 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1982 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1983 void getGCCRegNames(const char * const *&Names,
1984 unsigned &NumNames) const override {
1985 Names = GCCRegNames;
1986 NumNames = llvm::array_lengthof(GCCRegNames);
1987 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1988 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1989 unsigned &NumAliases) const override {
1990 Aliases = nullptr;
1991 NumAliases = 0;
1992 }
getGCCAddlRegNames(const AddlRegName * & Names,unsigned & NumNames) const1993 void getGCCAddlRegNames(const AddlRegName *&Names,
1994 unsigned &NumNames) const override {
1995 Names = AddlRegNames;
1996 NumNames = llvm::array_lengthof(AddlRegNames);
1997 }
1998 bool validateAsmConstraint(const char *&Name,
1999 TargetInfo::ConstraintInfo &info) const override;
2000
2001 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2002
2003 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2004
2005 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2006
2007 std::string convertConstraint(const char *&Constraint) const override;
getClobbers() const2008 const char *getClobbers() const override {
2009 return "~{dirflag},~{fpsr},~{flags}";
2010 }
2011 void getTargetDefines(const LangOptions &Opts,
2012 MacroBuilder &Builder) const override;
2013 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2014 bool Enabled);
2015 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2016 bool Enabled);
2017 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2018 bool Enabled);
setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const2019 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2020 StringRef Name, bool Enabled) const override {
2021 setFeatureEnabledImpl(Features, Name, Enabled);
2022 }
2023 // This exists purely to cut down on the number of virtual calls in
2024 // getDefaultFeatures which calls this repeatedly.
2025 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2026 StringRef Name, bool Enabled);
2027 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2028 bool hasFeature(StringRef Feature) const override;
2029 bool handleTargetFeatures(std::vector<std::string> &Features,
2030 DiagnosticsEngine &Diags) override;
getABI() const2031 StringRef getABI() const override {
2032 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2033 return "avx";
2034 else if (getTriple().getArch() == llvm::Triple::x86 &&
2035 MMX3DNowLevel == NoMMX3DNow)
2036 return "no-mmx";
2037 return "";
2038 }
setCPU(const std::string & Name)2039 bool setCPU(const std::string &Name) override {
2040 CPU = llvm::StringSwitch<CPUKind>(Name)
2041 .Case("i386", CK_i386)
2042 .Case("i486", CK_i486)
2043 .Case("winchip-c6", CK_WinChipC6)
2044 .Case("winchip2", CK_WinChip2)
2045 .Case("c3", CK_C3)
2046 .Case("i586", CK_i586)
2047 .Case("pentium", CK_Pentium)
2048 .Case("pentium-mmx", CK_PentiumMMX)
2049 .Case("i686", CK_i686)
2050 .Case("pentiumpro", CK_PentiumPro)
2051 .Case("pentium2", CK_Pentium2)
2052 .Case("pentium3", CK_Pentium3)
2053 .Case("pentium3m", CK_Pentium3M)
2054 .Case("pentium-m", CK_PentiumM)
2055 .Case("c3-2", CK_C3_2)
2056 .Case("yonah", CK_Yonah)
2057 .Case("pentium4", CK_Pentium4)
2058 .Case("pentium4m", CK_Pentium4M)
2059 .Case("prescott", CK_Prescott)
2060 .Case("nocona", CK_Nocona)
2061 .Case("core2", CK_Core2)
2062 .Case("penryn", CK_Penryn)
2063 .Case("bonnell", CK_Bonnell)
2064 .Case("atom", CK_Bonnell) // Legacy name.
2065 .Case("silvermont", CK_Silvermont)
2066 .Case("slm", CK_Silvermont) // Legacy name.
2067 .Case("nehalem", CK_Nehalem)
2068 .Case("corei7", CK_Nehalem) // Legacy name.
2069 .Case("westmere", CK_Westmere)
2070 .Case("sandybridge", CK_SandyBridge)
2071 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2072 .Case("ivybridge", CK_IvyBridge)
2073 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2074 .Case("haswell", CK_Haswell)
2075 .Case("core-avx2", CK_Haswell) // Legacy name.
2076 .Case("broadwell", CK_Broadwell)
2077 .Case("skylake", CK_Skylake)
2078 .Case("skx", CK_Skylake) // Legacy name.
2079 .Case("knl", CK_KNL)
2080 .Case("k6", CK_K6)
2081 .Case("k6-2", CK_K6_2)
2082 .Case("k6-3", CK_K6_3)
2083 .Case("athlon", CK_Athlon)
2084 .Case("athlon-tbird", CK_AthlonThunderbird)
2085 .Case("athlon-4", CK_Athlon4)
2086 .Case("athlon-xp", CK_AthlonXP)
2087 .Case("athlon-mp", CK_AthlonMP)
2088 .Case("athlon64", CK_Athlon64)
2089 .Case("athlon64-sse3", CK_Athlon64SSE3)
2090 .Case("athlon-fx", CK_AthlonFX)
2091 .Case("k8", CK_K8)
2092 .Case("k8-sse3", CK_K8SSE3)
2093 .Case("opteron", CK_Opteron)
2094 .Case("opteron-sse3", CK_OpteronSSE3)
2095 .Case("barcelona", CK_AMDFAM10)
2096 .Case("amdfam10", CK_AMDFAM10)
2097 .Case("btver1", CK_BTVER1)
2098 .Case("btver2", CK_BTVER2)
2099 .Case("bdver1", CK_BDVER1)
2100 .Case("bdver2", CK_BDVER2)
2101 .Case("bdver3", CK_BDVER3)
2102 .Case("bdver4", CK_BDVER4)
2103 .Case("x86-64", CK_x86_64)
2104 .Case("geode", CK_Geode)
2105 .Default(CK_Generic);
2106
2107 // Perform any per-CPU checks necessary to determine if this CPU is
2108 // acceptable.
2109 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2110 // invalid without explaining *why*.
2111 switch (CPU) {
2112 case CK_Generic:
2113 // No processor selected!
2114 return false;
2115
2116 case CK_i386:
2117 case CK_i486:
2118 case CK_WinChipC6:
2119 case CK_WinChip2:
2120 case CK_C3:
2121 case CK_i586:
2122 case CK_Pentium:
2123 case CK_PentiumMMX:
2124 case CK_i686:
2125 case CK_PentiumPro:
2126 case CK_Pentium2:
2127 case CK_Pentium3:
2128 case CK_Pentium3M:
2129 case CK_PentiumM:
2130 case CK_Yonah:
2131 case CK_C3_2:
2132 case CK_Pentium4:
2133 case CK_Pentium4M:
2134 case CK_Prescott:
2135 case CK_K6:
2136 case CK_K6_2:
2137 case CK_K6_3:
2138 case CK_Athlon:
2139 case CK_AthlonThunderbird:
2140 case CK_Athlon4:
2141 case CK_AthlonXP:
2142 case CK_AthlonMP:
2143 case CK_Geode:
2144 // Only accept certain architectures when compiling in 32-bit mode.
2145 if (getTriple().getArch() != llvm::Triple::x86)
2146 return false;
2147
2148 // Fallthrough
2149 case CK_Nocona:
2150 case CK_Core2:
2151 case CK_Penryn:
2152 case CK_Bonnell:
2153 case CK_Silvermont:
2154 case CK_Nehalem:
2155 case CK_Westmere:
2156 case CK_SandyBridge:
2157 case CK_IvyBridge:
2158 case CK_Haswell:
2159 case CK_Broadwell:
2160 case CK_Skylake:
2161 case CK_KNL:
2162 case CK_Athlon64:
2163 case CK_Athlon64SSE3:
2164 case CK_AthlonFX:
2165 case CK_K8:
2166 case CK_K8SSE3:
2167 case CK_Opteron:
2168 case CK_OpteronSSE3:
2169 case CK_AMDFAM10:
2170 case CK_BTVER1:
2171 case CK_BTVER2:
2172 case CK_BDVER1:
2173 case CK_BDVER2:
2174 case CK_BDVER3:
2175 case CK_BDVER4:
2176 case CK_x86_64:
2177 return true;
2178 }
2179 llvm_unreachable("Unhandled CPU kind");
2180 }
2181
2182 bool setFPMath(StringRef Name) override;
2183
checkCallingConvention(CallingConv CC) const2184 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2185 // We accept all non-ARM calling conventions
2186 return (CC == CC_X86ThisCall ||
2187 CC == CC_X86FastCall ||
2188 CC == CC_X86StdCall ||
2189 CC == CC_X86VectorCall ||
2190 CC == CC_C ||
2191 CC == CC_X86Pascal ||
2192 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2193 }
2194
getDefaultCallingConv(CallingConvMethodType MT) const2195 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2196 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2197 }
2198
hasSjLjLowering() const2199 bool hasSjLjLowering() const override {
2200 return true;
2201 }
2202 };
2203
setFPMath(StringRef Name)2204 bool X86TargetInfo::setFPMath(StringRef Name) {
2205 if (Name == "387") {
2206 FPMath = FP_387;
2207 return true;
2208 }
2209 if (Name == "sse") {
2210 FPMath = FP_SSE;
2211 return true;
2212 }
2213 return false;
2214 }
2215
getDefaultFeatures(llvm::StringMap<bool> & Features) const2216 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2217 // FIXME: This *really* should not be here.
2218
2219 // X86_64 always has SSE2.
2220 if (getTriple().getArch() == llvm::Triple::x86_64)
2221 setFeatureEnabledImpl(Features, "sse2", true);
2222
2223 switch (CPU) {
2224 case CK_Generic:
2225 case CK_i386:
2226 case CK_i486:
2227 case CK_i586:
2228 case CK_Pentium:
2229 case CK_i686:
2230 case CK_PentiumPro:
2231 break;
2232 case CK_PentiumMMX:
2233 case CK_Pentium2:
2234 case CK_K6:
2235 case CK_WinChipC6:
2236 setFeatureEnabledImpl(Features, "mmx", true);
2237 break;
2238 case CK_Pentium3:
2239 case CK_Pentium3M:
2240 case CK_C3_2:
2241 setFeatureEnabledImpl(Features, "sse", true);
2242 break;
2243 case CK_PentiumM:
2244 case CK_Pentium4:
2245 case CK_Pentium4M:
2246 case CK_x86_64:
2247 setFeatureEnabledImpl(Features, "sse2", true);
2248 break;
2249 case CK_Yonah:
2250 case CK_Prescott:
2251 case CK_Nocona:
2252 setFeatureEnabledImpl(Features, "sse3", true);
2253 setFeatureEnabledImpl(Features, "cx16", true);
2254 break;
2255 case CK_Core2:
2256 case CK_Bonnell:
2257 setFeatureEnabledImpl(Features, "ssse3", true);
2258 setFeatureEnabledImpl(Features, "cx16", true);
2259 break;
2260 case CK_Penryn:
2261 setFeatureEnabledImpl(Features, "sse4.1", true);
2262 setFeatureEnabledImpl(Features, "cx16", true);
2263 break;
2264 case CK_Skylake:
2265 setFeatureEnabledImpl(Features, "avx512f", true);
2266 setFeatureEnabledImpl(Features, "avx512cd", true);
2267 setFeatureEnabledImpl(Features, "avx512dq", true);
2268 setFeatureEnabledImpl(Features, "avx512bw", true);
2269 setFeatureEnabledImpl(Features, "avx512vl", true);
2270 // FALLTHROUGH
2271 case CK_Broadwell:
2272 setFeatureEnabledImpl(Features, "rdseed", true);
2273 setFeatureEnabledImpl(Features, "adx", true);
2274 // FALLTHROUGH
2275 case CK_Haswell:
2276 setFeatureEnabledImpl(Features, "avx2", true);
2277 setFeatureEnabledImpl(Features, "lzcnt", true);
2278 setFeatureEnabledImpl(Features, "bmi", true);
2279 setFeatureEnabledImpl(Features, "bmi2", true);
2280 setFeatureEnabledImpl(Features, "rtm", true);
2281 setFeatureEnabledImpl(Features, "fma", true);
2282 // FALLTHROUGH
2283 case CK_IvyBridge:
2284 setFeatureEnabledImpl(Features, "rdrnd", true);
2285 setFeatureEnabledImpl(Features, "f16c", true);
2286 setFeatureEnabledImpl(Features, "fsgsbase", true);
2287 // FALLTHROUGH
2288 case CK_SandyBridge:
2289 setFeatureEnabledImpl(Features, "avx", true);
2290 // FALLTHROUGH
2291 case CK_Westmere:
2292 case CK_Silvermont:
2293 setFeatureEnabledImpl(Features, "aes", true);
2294 setFeatureEnabledImpl(Features, "pclmul", true);
2295 // FALLTHROUGH
2296 case CK_Nehalem:
2297 setFeatureEnabledImpl(Features, "sse4.2", true);
2298 setFeatureEnabledImpl(Features, "cx16", true);
2299 break;
2300 case CK_KNL:
2301 setFeatureEnabledImpl(Features, "avx512f", true);
2302 setFeatureEnabledImpl(Features, "avx512cd", true);
2303 setFeatureEnabledImpl(Features, "avx512er", true);
2304 setFeatureEnabledImpl(Features, "avx512pf", true);
2305 setFeatureEnabledImpl(Features, "rdseed", true);
2306 setFeatureEnabledImpl(Features, "adx", true);
2307 setFeatureEnabledImpl(Features, "lzcnt", true);
2308 setFeatureEnabledImpl(Features, "bmi", true);
2309 setFeatureEnabledImpl(Features, "bmi2", true);
2310 setFeatureEnabledImpl(Features, "rtm", true);
2311 setFeatureEnabledImpl(Features, "fma", true);
2312 setFeatureEnabledImpl(Features, "rdrnd", true);
2313 setFeatureEnabledImpl(Features, "f16c", true);
2314 setFeatureEnabledImpl(Features, "fsgsbase", true);
2315 setFeatureEnabledImpl(Features, "aes", true);
2316 setFeatureEnabledImpl(Features, "pclmul", true);
2317 setFeatureEnabledImpl(Features, "cx16", true);
2318 break;
2319 case CK_K6_2:
2320 case CK_K6_3:
2321 case CK_WinChip2:
2322 case CK_C3:
2323 setFeatureEnabledImpl(Features, "3dnow", true);
2324 break;
2325 case CK_Athlon:
2326 case CK_AthlonThunderbird:
2327 case CK_Geode:
2328 setFeatureEnabledImpl(Features, "3dnowa", true);
2329 break;
2330 case CK_Athlon4:
2331 case CK_AthlonXP:
2332 case CK_AthlonMP:
2333 setFeatureEnabledImpl(Features, "sse", true);
2334 setFeatureEnabledImpl(Features, "3dnowa", true);
2335 break;
2336 case CK_K8:
2337 case CK_Opteron:
2338 case CK_Athlon64:
2339 case CK_AthlonFX:
2340 setFeatureEnabledImpl(Features, "sse2", true);
2341 setFeatureEnabledImpl(Features, "3dnowa", true);
2342 break;
2343 case CK_AMDFAM10:
2344 setFeatureEnabledImpl(Features, "sse4a", true);
2345 setFeatureEnabledImpl(Features, "lzcnt", true);
2346 setFeatureEnabledImpl(Features, "popcnt", true);
2347 // FALLTHROUGH
2348 case CK_K8SSE3:
2349 case CK_OpteronSSE3:
2350 case CK_Athlon64SSE3:
2351 setFeatureEnabledImpl(Features, "sse3", true);
2352 setFeatureEnabledImpl(Features, "3dnowa", true);
2353 break;
2354 case CK_BTVER2:
2355 setFeatureEnabledImpl(Features, "avx", true);
2356 setFeatureEnabledImpl(Features, "aes", true);
2357 setFeatureEnabledImpl(Features, "pclmul", true);
2358 setFeatureEnabledImpl(Features, "bmi", true);
2359 setFeatureEnabledImpl(Features, "f16c", true);
2360 // FALLTHROUGH
2361 case CK_BTVER1:
2362 setFeatureEnabledImpl(Features, "ssse3", true);
2363 setFeatureEnabledImpl(Features, "sse4a", true);
2364 setFeatureEnabledImpl(Features, "lzcnt", true);
2365 setFeatureEnabledImpl(Features, "popcnt", true);
2366 setFeatureEnabledImpl(Features, "prfchw", true);
2367 setFeatureEnabledImpl(Features, "cx16", true);
2368 break;
2369 case CK_BDVER4:
2370 setFeatureEnabledImpl(Features, "avx2", true);
2371 setFeatureEnabledImpl(Features, "bmi2", true);
2372 // FALLTHROUGH
2373 case CK_BDVER3:
2374 setFeatureEnabledImpl(Features, "fsgsbase", true);
2375 // FALLTHROUGH
2376 case CK_BDVER2:
2377 setFeatureEnabledImpl(Features, "bmi", true);
2378 setFeatureEnabledImpl(Features, "fma", true);
2379 setFeatureEnabledImpl(Features, "f16c", true);
2380 setFeatureEnabledImpl(Features, "tbm", true);
2381 // FALLTHROUGH
2382 case CK_BDVER1:
2383 // xop implies avx, sse4a and fma4.
2384 setFeatureEnabledImpl(Features, "xop", true);
2385 setFeatureEnabledImpl(Features, "lzcnt", true);
2386 setFeatureEnabledImpl(Features, "aes", true);
2387 setFeatureEnabledImpl(Features, "pclmul", true);
2388 setFeatureEnabledImpl(Features, "prfchw", true);
2389 setFeatureEnabledImpl(Features, "cx16", true);
2390 break;
2391 }
2392 }
2393
setSSELevel(llvm::StringMap<bool> & Features,X86SSEEnum Level,bool Enabled)2394 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2395 X86SSEEnum Level, bool Enabled) {
2396 if (Enabled) {
2397 switch (Level) {
2398 case AVX512F:
2399 Features["avx512f"] = true;
2400 case AVX2:
2401 Features["avx2"] = true;
2402 case AVX:
2403 Features["avx"] = true;
2404 case SSE42:
2405 Features["sse4.2"] = true;
2406 case SSE41:
2407 Features["sse4.1"] = true;
2408 case SSSE3:
2409 Features["ssse3"] = true;
2410 case SSE3:
2411 Features["sse3"] = true;
2412 case SSE2:
2413 Features["sse2"] = true;
2414 case SSE1:
2415 Features["sse"] = true;
2416 case NoSSE:
2417 break;
2418 }
2419 return;
2420 }
2421
2422 switch (Level) {
2423 case NoSSE:
2424 case SSE1:
2425 Features["sse"] = false;
2426 case SSE2:
2427 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2428 Features["sha"] = false;
2429 case SSE3:
2430 Features["sse3"] = false;
2431 setXOPLevel(Features, NoXOP, false);
2432 case SSSE3:
2433 Features["ssse3"] = false;
2434 case SSE41:
2435 Features["sse4.1"] = false;
2436 case SSE42:
2437 Features["sse4.2"] = false;
2438 case AVX:
2439 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2440 setXOPLevel(Features, FMA4, false);
2441 case AVX2:
2442 Features["avx2"] = false;
2443 case AVX512F:
2444 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2445 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2446 Features["avx512vl"] = false;
2447 }
2448 }
2449
setMMXLevel(llvm::StringMap<bool> & Features,MMX3DNowEnum Level,bool Enabled)2450 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2451 MMX3DNowEnum Level, bool Enabled) {
2452 if (Enabled) {
2453 switch (Level) {
2454 case AMD3DNowAthlon:
2455 Features["3dnowa"] = true;
2456 case AMD3DNow:
2457 Features["3dnow"] = true;
2458 case MMX:
2459 Features["mmx"] = true;
2460 case NoMMX3DNow:
2461 break;
2462 }
2463 return;
2464 }
2465
2466 switch (Level) {
2467 case NoMMX3DNow:
2468 case MMX:
2469 Features["mmx"] = false;
2470 case AMD3DNow:
2471 Features["3dnow"] = false;
2472 case AMD3DNowAthlon:
2473 Features["3dnowa"] = false;
2474 }
2475 }
2476
setXOPLevel(llvm::StringMap<bool> & Features,XOPEnum Level,bool Enabled)2477 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2478 bool Enabled) {
2479 if (Enabled) {
2480 switch (Level) {
2481 case XOP:
2482 Features["xop"] = true;
2483 case FMA4:
2484 Features["fma4"] = true;
2485 setSSELevel(Features, AVX, true);
2486 case SSE4A:
2487 Features["sse4a"] = true;
2488 setSSELevel(Features, SSE3, true);
2489 case NoXOP:
2490 break;
2491 }
2492 return;
2493 }
2494
2495 switch (Level) {
2496 case NoXOP:
2497 case SSE4A:
2498 Features["sse4a"] = false;
2499 case FMA4:
2500 Features["fma4"] = false;
2501 case XOP:
2502 Features["xop"] = false;
2503 }
2504 }
2505
setFeatureEnabledImpl(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled)2506 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2507 StringRef Name, bool Enabled) {
2508 // FIXME: This *really* should not be here. We need some way of translating
2509 // options into llvm subtarget features.
2510 if (Name == "sse4")
2511 Name = "sse4.2";
2512
2513 Features[Name] = Enabled;
2514
2515 if (Name == "mmx") {
2516 setMMXLevel(Features, MMX, Enabled);
2517 } else if (Name == "sse") {
2518 setSSELevel(Features, SSE1, Enabled);
2519 } else if (Name == "sse2") {
2520 setSSELevel(Features, SSE2, Enabled);
2521 } else if (Name == "sse3") {
2522 setSSELevel(Features, SSE3, Enabled);
2523 } else if (Name == "ssse3") {
2524 setSSELevel(Features, SSSE3, Enabled);
2525 } else if (Name == "sse4.2") {
2526 setSSELevel(Features, SSE42, Enabled);
2527 } else if (Name == "sse4.1") {
2528 setSSELevel(Features, SSE41, Enabled);
2529 } else if (Name == "3dnow") {
2530 setMMXLevel(Features, AMD3DNow, Enabled);
2531 } else if (Name == "3dnowa") {
2532 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2533 } else if (Name == "aes") {
2534 if (Enabled)
2535 setSSELevel(Features, SSE2, Enabled);
2536 } else if (Name == "pclmul") {
2537 if (Enabled)
2538 setSSELevel(Features, SSE2, Enabled);
2539 } else if (Name == "avx") {
2540 setSSELevel(Features, AVX, Enabled);
2541 } else if (Name == "avx2") {
2542 setSSELevel(Features, AVX2, Enabled);
2543 } else if (Name == "avx512f") {
2544 setSSELevel(Features, AVX512F, Enabled);
2545 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2546 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2547 if (Enabled)
2548 setSSELevel(Features, AVX512F, Enabled);
2549 } else if (Name == "fma") {
2550 if (Enabled)
2551 setSSELevel(Features, AVX, Enabled);
2552 } else if (Name == "fma4") {
2553 setXOPLevel(Features, FMA4, Enabled);
2554 } else if (Name == "xop") {
2555 setXOPLevel(Features, XOP, Enabled);
2556 } else if (Name == "sse4a") {
2557 setXOPLevel(Features, SSE4A, Enabled);
2558 } else if (Name == "f16c") {
2559 if (Enabled)
2560 setSSELevel(Features, AVX, Enabled);
2561 } else if (Name == "sha") {
2562 if (Enabled)
2563 setSSELevel(Features, SSE2, Enabled);
2564 }
2565 }
2566
2567 /// handleTargetFeatures - Perform initialization based on the user
2568 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)2569 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2570 DiagnosticsEngine &Diags) {
2571 // Remember the maximum enabled sselevel.
2572 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2573 // Ignore disabled features.
2574 if (Features[i][0] == '-')
2575 continue;
2576
2577 StringRef Feature = StringRef(Features[i]).substr(1);
2578
2579 if (Feature == "aes") {
2580 HasAES = true;
2581 continue;
2582 }
2583
2584 if (Feature == "pclmul") {
2585 HasPCLMUL = true;
2586 continue;
2587 }
2588
2589 if (Feature == "lzcnt") {
2590 HasLZCNT = true;
2591 continue;
2592 }
2593
2594 if (Feature == "rdrnd") {
2595 HasRDRND = true;
2596 continue;
2597 }
2598
2599 if (Feature == "fsgsbase") {
2600 HasFSGSBASE = true;
2601 continue;
2602 }
2603
2604 if (Feature == "bmi") {
2605 HasBMI = true;
2606 continue;
2607 }
2608
2609 if (Feature == "bmi2") {
2610 HasBMI2 = true;
2611 continue;
2612 }
2613
2614 if (Feature == "popcnt") {
2615 HasPOPCNT = true;
2616 continue;
2617 }
2618
2619 if (Feature == "rtm") {
2620 HasRTM = true;
2621 continue;
2622 }
2623
2624 if (Feature == "prfchw") {
2625 HasPRFCHW = true;
2626 continue;
2627 }
2628
2629 if (Feature == "rdseed") {
2630 HasRDSEED = true;
2631 continue;
2632 }
2633
2634 if (Feature == "adx") {
2635 HasADX = true;
2636 continue;
2637 }
2638
2639 if (Feature == "tbm") {
2640 HasTBM = true;
2641 continue;
2642 }
2643
2644 if (Feature == "fma") {
2645 HasFMA = true;
2646 continue;
2647 }
2648
2649 if (Feature == "f16c") {
2650 HasF16C = true;
2651 continue;
2652 }
2653
2654 if (Feature == "avx512cd") {
2655 HasAVX512CD = true;
2656 continue;
2657 }
2658
2659 if (Feature == "avx512er") {
2660 HasAVX512ER = true;
2661 continue;
2662 }
2663
2664 if (Feature == "avx512pf") {
2665 HasAVX512PF = true;
2666 continue;
2667 }
2668
2669 if (Feature == "avx512dq") {
2670 HasAVX512DQ = true;
2671 continue;
2672 }
2673
2674 if (Feature == "avx512bw") {
2675 HasAVX512BW = true;
2676 continue;
2677 }
2678
2679 if (Feature == "avx512vl") {
2680 HasAVX512VL = true;
2681 continue;
2682 }
2683
2684 if (Feature == "sha") {
2685 HasSHA = true;
2686 continue;
2687 }
2688
2689 if (Feature == "cx16") {
2690 HasCX16 = true;
2691 continue;
2692 }
2693
2694 assert(Features[i][0] == '+' && "Invalid target feature!");
2695 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2696 .Case("avx512f", AVX512F)
2697 .Case("avx2", AVX2)
2698 .Case("avx", AVX)
2699 .Case("sse4.2", SSE42)
2700 .Case("sse4.1", SSE41)
2701 .Case("ssse3", SSSE3)
2702 .Case("sse3", SSE3)
2703 .Case("sse2", SSE2)
2704 .Case("sse", SSE1)
2705 .Default(NoSSE);
2706 SSELevel = std::max(SSELevel, Level);
2707
2708 MMX3DNowEnum ThreeDNowLevel =
2709 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2710 .Case("3dnowa", AMD3DNowAthlon)
2711 .Case("3dnow", AMD3DNow)
2712 .Case("mmx", MMX)
2713 .Default(NoMMX3DNow);
2714 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2715
2716 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2717 .Case("xop", XOP)
2718 .Case("fma4", FMA4)
2719 .Case("sse4a", SSE4A)
2720 .Default(NoXOP);
2721 XOPLevel = std::max(XOPLevel, XLevel);
2722 }
2723
2724 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2725 // Can't do this earlier because we need to be able to explicitly enable
2726 // popcnt and still disable sse4.2.
2727 if (!HasPOPCNT && SSELevel >= SSE42 &&
2728 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2729 HasPOPCNT = true;
2730 Features.push_back("+popcnt");
2731 }
2732
2733 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2734 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2735 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2736 HasPRFCHW = true;
2737 Features.push_back("+prfchw");
2738 }
2739
2740 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2741 // matches the selected sse level.
2742 if (FPMath == FP_SSE && SSELevel < SSE1) {
2743 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2744 return false;
2745 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2746 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2747 return false;
2748 }
2749
2750 // Don't tell the backend if we're turning off mmx; it will end up disabling
2751 // SSE, which we don't want.
2752 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2753 // then enable MMX.
2754 std::vector<std::string>::iterator it;
2755 it = std::find(Features.begin(), Features.end(), "-mmx");
2756 if (it != Features.end())
2757 Features.erase(it);
2758 else if (SSELevel > NoSSE)
2759 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2760 return true;
2761 }
2762
2763 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2764 /// definitions for this particular subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const2765 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2766 MacroBuilder &Builder) const {
2767 // Target identification.
2768 if (getTriple().getArch() == llvm::Triple::x86_64) {
2769 Builder.defineMacro("__amd64__");
2770 Builder.defineMacro("__amd64");
2771 Builder.defineMacro("__x86_64");
2772 Builder.defineMacro("__x86_64__");
2773 if (getTriple().getArchName() == "x86_64h") {
2774 Builder.defineMacro("__x86_64h");
2775 Builder.defineMacro("__x86_64h__");
2776 }
2777 } else {
2778 DefineStd(Builder, "i386", Opts);
2779 }
2780
2781 // Subtarget options.
2782 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2783 // truly should be based on -mtune options.
2784 switch (CPU) {
2785 case CK_Generic:
2786 break;
2787 case CK_i386:
2788 // The rest are coming from the i386 define above.
2789 Builder.defineMacro("__tune_i386__");
2790 break;
2791 case CK_i486:
2792 case CK_WinChipC6:
2793 case CK_WinChip2:
2794 case CK_C3:
2795 defineCPUMacros(Builder, "i486");
2796 break;
2797 case CK_PentiumMMX:
2798 Builder.defineMacro("__pentium_mmx__");
2799 Builder.defineMacro("__tune_pentium_mmx__");
2800 // Fallthrough
2801 case CK_i586:
2802 case CK_Pentium:
2803 defineCPUMacros(Builder, "i586");
2804 defineCPUMacros(Builder, "pentium");
2805 break;
2806 case CK_Pentium3:
2807 case CK_Pentium3M:
2808 case CK_PentiumM:
2809 Builder.defineMacro("__tune_pentium3__");
2810 // Fallthrough
2811 case CK_Pentium2:
2812 case CK_C3_2:
2813 Builder.defineMacro("__tune_pentium2__");
2814 // Fallthrough
2815 case CK_PentiumPro:
2816 Builder.defineMacro("__tune_i686__");
2817 Builder.defineMacro("__tune_pentiumpro__");
2818 // Fallthrough
2819 case CK_i686:
2820 Builder.defineMacro("__i686");
2821 Builder.defineMacro("__i686__");
2822 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2823 Builder.defineMacro("__pentiumpro");
2824 Builder.defineMacro("__pentiumpro__");
2825 break;
2826 case CK_Pentium4:
2827 case CK_Pentium4M:
2828 defineCPUMacros(Builder, "pentium4");
2829 break;
2830 case CK_Yonah:
2831 case CK_Prescott:
2832 case CK_Nocona:
2833 defineCPUMacros(Builder, "nocona");
2834 break;
2835 case CK_Core2:
2836 case CK_Penryn:
2837 defineCPUMacros(Builder, "core2");
2838 break;
2839 case CK_Bonnell:
2840 defineCPUMacros(Builder, "atom");
2841 break;
2842 case CK_Silvermont:
2843 defineCPUMacros(Builder, "slm");
2844 break;
2845 case CK_Nehalem:
2846 case CK_Westmere:
2847 case CK_SandyBridge:
2848 case CK_IvyBridge:
2849 case CK_Haswell:
2850 case CK_Broadwell:
2851 // FIXME: Historically, we defined this legacy name, it would be nice to
2852 // remove it at some point. We've never exposed fine-grained names for
2853 // recent primary x86 CPUs, and we should keep it that way.
2854 defineCPUMacros(Builder, "corei7");
2855 break;
2856 case CK_Skylake:
2857 // FIXME: Historically, we defined this legacy name, it would be nice to
2858 // remove it at some point. This is the only fine-grained CPU macro in the
2859 // main intel CPU line, and it would be better to not have these and force
2860 // people to use ISA macros.
2861 defineCPUMacros(Builder, "skx");
2862 break;
2863 case CK_KNL:
2864 defineCPUMacros(Builder, "knl");
2865 break;
2866 case CK_K6_2:
2867 Builder.defineMacro("__k6_2__");
2868 Builder.defineMacro("__tune_k6_2__");
2869 // Fallthrough
2870 case CK_K6_3:
2871 if (CPU != CK_K6_2) { // In case of fallthrough
2872 // FIXME: GCC may be enabling these in cases where some other k6
2873 // architecture is specified but -m3dnow is explicitly provided. The
2874 // exact semantics need to be determined and emulated here.
2875 Builder.defineMacro("__k6_3__");
2876 Builder.defineMacro("__tune_k6_3__");
2877 }
2878 // Fallthrough
2879 case CK_K6:
2880 defineCPUMacros(Builder, "k6");
2881 break;
2882 case CK_Athlon:
2883 case CK_AthlonThunderbird:
2884 case CK_Athlon4:
2885 case CK_AthlonXP:
2886 case CK_AthlonMP:
2887 defineCPUMacros(Builder, "athlon");
2888 if (SSELevel != NoSSE) {
2889 Builder.defineMacro("__athlon_sse__");
2890 Builder.defineMacro("__tune_athlon_sse__");
2891 }
2892 break;
2893 case CK_K8:
2894 case CK_K8SSE3:
2895 case CK_x86_64:
2896 case CK_Opteron:
2897 case CK_OpteronSSE3:
2898 case CK_Athlon64:
2899 case CK_Athlon64SSE3:
2900 case CK_AthlonFX:
2901 defineCPUMacros(Builder, "k8");
2902 break;
2903 case CK_AMDFAM10:
2904 defineCPUMacros(Builder, "amdfam10");
2905 break;
2906 case CK_BTVER1:
2907 defineCPUMacros(Builder, "btver1");
2908 break;
2909 case CK_BTVER2:
2910 defineCPUMacros(Builder, "btver2");
2911 break;
2912 case CK_BDVER1:
2913 defineCPUMacros(Builder, "bdver1");
2914 break;
2915 case CK_BDVER2:
2916 defineCPUMacros(Builder, "bdver2");
2917 break;
2918 case CK_BDVER3:
2919 defineCPUMacros(Builder, "bdver3");
2920 break;
2921 case CK_BDVER4:
2922 defineCPUMacros(Builder, "bdver4");
2923 break;
2924 case CK_Geode:
2925 defineCPUMacros(Builder, "geode");
2926 break;
2927 }
2928
2929 // Target properties.
2930 Builder.defineMacro("__REGISTER_PREFIX__", "");
2931
2932 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2933 // functions in glibc header files that use FP Stack inline asm which the
2934 // backend can't deal with (PR879).
2935 Builder.defineMacro("__NO_MATH_INLINES");
2936
2937 if (HasAES)
2938 Builder.defineMacro("__AES__");
2939
2940 if (HasPCLMUL)
2941 Builder.defineMacro("__PCLMUL__");
2942
2943 if (HasLZCNT)
2944 Builder.defineMacro("__LZCNT__");
2945
2946 if (HasRDRND)
2947 Builder.defineMacro("__RDRND__");
2948
2949 if (HasFSGSBASE)
2950 Builder.defineMacro("__FSGSBASE__");
2951
2952 if (HasBMI)
2953 Builder.defineMacro("__BMI__");
2954
2955 if (HasBMI2)
2956 Builder.defineMacro("__BMI2__");
2957
2958 if (HasPOPCNT)
2959 Builder.defineMacro("__POPCNT__");
2960
2961 if (HasRTM)
2962 Builder.defineMacro("__RTM__");
2963
2964 if (HasPRFCHW)
2965 Builder.defineMacro("__PRFCHW__");
2966
2967 if (HasRDSEED)
2968 Builder.defineMacro("__RDSEED__");
2969
2970 if (HasADX)
2971 Builder.defineMacro("__ADX__");
2972
2973 if (HasTBM)
2974 Builder.defineMacro("__TBM__");
2975
2976 switch (XOPLevel) {
2977 case XOP:
2978 Builder.defineMacro("__XOP__");
2979 case FMA4:
2980 Builder.defineMacro("__FMA4__");
2981 case SSE4A:
2982 Builder.defineMacro("__SSE4A__");
2983 case NoXOP:
2984 break;
2985 }
2986
2987 if (HasFMA)
2988 Builder.defineMacro("__FMA__");
2989
2990 if (HasF16C)
2991 Builder.defineMacro("__F16C__");
2992
2993 if (HasAVX512CD)
2994 Builder.defineMacro("__AVX512CD__");
2995 if (HasAVX512ER)
2996 Builder.defineMacro("__AVX512ER__");
2997 if (HasAVX512PF)
2998 Builder.defineMacro("__AVX512PF__");
2999 if (HasAVX512DQ)
3000 Builder.defineMacro("__AVX512DQ__");
3001 if (HasAVX512BW)
3002 Builder.defineMacro("__AVX512BW__");
3003 if (HasAVX512VL)
3004 Builder.defineMacro("__AVX512VL__");
3005
3006 if (HasSHA)
3007 Builder.defineMacro("__SHA__");
3008
3009 if (HasCX16)
3010 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3011
3012 // Each case falls through to the previous one here.
3013 switch (SSELevel) {
3014 case AVX512F:
3015 Builder.defineMacro("__AVX512F__");
3016 case AVX2:
3017 Builder.defineMacro("__AVX2__");
3018 case AVX:
3019 Builder.defineMacro("__AVX__");
3020 case SSE42:
3021 Builder.defineMacro("__SSE4_2__");
3022 case SSE41:
3023 Builder.defineMacro("__SSE4_1__");
3024 case SSSE3:
3025 Builder.defineMacro("__SSSE3__");
3026 case SSE3:
3027 Builder.defineMacro("__SSE3__");
3028 case SSE2:
3029 Builder.defineMacro("__SSE2__");
3030 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3031 case SSE1:
3032 Builder.defineMacro("__SSE__");
3033 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3034 case NoSSE:
3035 break;
3036 }
3037
3038 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3039 switch (SSELevel) {
3040 case AVX512F:
3041 case AVX2:
3042 case AVX:
3043 case SSE42:
3044 case SSE41:
3045 case SSSE3:
3046 case SSE3:
3047 case SSE2:
3048 Builder.defineMacro("_M_IX86_FP", Twine(2));
3049 break;
3050 case SSE1:
3051 Builder.defineMacro("_M_IX86_FP", Twine(1));
3052 break;
3053 default:
3054 Builder.defineMacro("_M_IX86_FP", Twine(0));
3055 }
3056 }
3057
3058 // Each case falls through to the previous one here.
3059 switch (MMX3DNowLevel) {
3060 case AMD3DNowAthlon:
3061 Builder.defineMacro("__3dNOW_A__");
3062 case AMD3DNow:
3063 Builder.defineMacro("__3dNOW__");
3064 case MMX:
3065 Builder.defineMacro("__MMX__");
3066 case NoMMX3DNow:
3067 break;
3068 }
3069
3070 if (CPU >= CK_i486) {
3071 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3072 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3074 }
3075 if (CPU >= CK_i586)
3076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3077 }
3078
hasFeature(StringRef Feature) const3079 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3080 return llvm::StringSwitch<bool>(Feature)
3081 .Case("aes", HasAES)
3082 .Case("avx", SSELevel >= AVX)
3083 .Case("avx2", SSELevel >= AVX2)
3084 .Case("avx512f", SSELevel >= AVX512F)
3085 .Case("avx512cd", HasAVX512CD)
3086 .Case("avx512er", HasAVX512ER)
3087 .Case("avx512pf", HasAVX512PF)
3088 .Case("avx512dq", HasAVX512DQ)
3089 .Case("avx512bw", HasAVX512BW)
3090 .Case("avx512vl", HasAVX512VL)
3091 .Case("bmi", HasBMI)
3092 .Case("bmi2", HasBMI2)
3093 .Case("cx16", HasCX16)
3094 .Case("f16c", HasF16C)
3095 .Case("fma", HasFMA)
3096 .Case("fma4", XOPLevel >= FMA4)
3097 .Case("fsgsbase", HasFSGSBASE)
3098 .Case("lzcnt", HasLZCNT)
3099 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3100 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3101 .Case("mmx", MMX3DNowLevel >= MMX)
3102 .Case("pclmul", HasPCLMUL)
3103 .Case("popcnt", HasPOPCNT)
3104 .Case("prfchw", HasPRFCHW)
3105 .Case("rdrnd", HasRDRND)
3106 .Case("rdseed", HasRDSEED)
3107 .Case("rtm", HasRTM)
3108 .Case("sha", HasSHA)
3109 .Case("sse", SSELevel >= SSE1)
3110 .Case("sse2", SSELevel >= SSE2)
3111 .Case("sse3", SSELevel >= SSE3)
3112 .Case("ssse3", SSELevel >= SSSE3)
3113 .Case("sse4.1", SSELevel >= SSE41)
3114 .Case("sse4.2", SSELevel >= SSE42)
3115 .Case("sse4a", XOPLevel >= SSE4A)
3116 .Case("tbm", HasTBM)
3117 .Case("x86", true)
3118 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3119 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3120 .Case("xop", XOPLevel >= XOP)
3121 .Default(false);
3122 }
3123
3124 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const3125 X86TargetInfo::validateAsmConstraint(const char *&Name,
3126 TargetInfo::ConstraintInfo &Info) const {
3127 switch (*Name) {
3128 default: return false;
3129 case 'I':
3130 Info.setRequiresImmediate(0, 31);
3131 return true;
3132 case 'J':
3133 Info.setRequiresImmediate(0, 63);
3134 return true;
3135 case 'K':
3136 Info.setRequiresImmediate(-128, 127);
3137 return true;
3138 case 'L':
3139 // FIXME: properly analyze this constraint:
3140 // must be one of 0xff, 0xffff, or 0xffffffff
3141 return true;
3142 case 'M':
3143 Info.setRequiresImmediate(0, 3);
3144 return true;
3145 case 'N':
3146 Info.setRequiresImmediate(0, 255);
3147 return true;
3148 case 'O':
3149 Info.setRequiresImmediate(0, 127);
3150 return true;
3151 case 'Y': // first letter of a pair:
3152 switch (*(Name+1)) {
3153 default: return false;
3154 case '0': // First SSE register.
3155 case 't': // Any SSE register, when SSE2 is enabled.
3156 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3157 case 'm': // any MMX register, when inter-unit moves enabled.
3158 break; // falls through to setAllowsRegister.
3159 }
3160 case 'f': // any x87 floating point stack register.
3161 // Constraint 'f' cannot be used for output operands.
3162 if (Info.ConstraintStr[0] == '=')
3163 return false;
3164
3165 Info.setAllowsRegister();
3166 return true;
3167 case 'a': // eax.
3168 case 'b': // ebx.
3169 case 'c': // ecx.
3170 case 'd': // edx.
3171 case 'S': // esi.
3172 case 'D': // edi.
3173 case 'A': // edx:eax.
3174 case 't': // top of floating point stack.
3175 case 'u': // second from top of floating point stack.
3176 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3177 case 'y': // Any MMX register.
3178 case 'x': // Any SSE register.
3179 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3180 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3181 case 'l': // "Index" registers: any general register that can be used as an
3182 // index in a base+index memory access.
3183 Info.setAllowsRegister();
3184 return true;
3185 case 'C': // SSE floating point constant.
3186 case 'G': // x87 floating point constant.
3187 case 'e': // 32-bit signed integer constant for use with zero-extending
3188 // x86_64 instructions.
3189 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3190 // x86_64 instructions.
3191 return true;
3192 }
3193 }
3194
validateOutputSize(StringRef Constraint,unsigned Size) const3195 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3196 unsigned Size) const {
3197 // Strip off constraint modifiers.
3198 while (Constraint[0] == '=' ||
3199 Constraint[0] == '+' ||
3200 Constraint[0] == '&')
3201 Constraint = Constraint.substr(1);
3202
3203 return validateOperandSize(Constraint, Size);
3204 }
3205
validateInputSize(StringRef Constraint,unsigned Size) const3206 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3207 unsigned Size) const {
3208 return validateOperandSize(Constraint, Size);
3209 }
3210
validateOperandSize(StringRef Constraint,unsigned Size) const3211 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3212 unsigned Size) const {
3213 switch (Constraint[0]) {
3214 default: break;
3215 case 'y':
3216 return Size <= 64;
3217 case 'f':
3218 case 't':
3219 case 'u':
3220 return Size <= 128;
3221 case 'x':
3222 // 256-bit ymm registers can be used if target supports AVX.
3223 return Size <= (SSELevel >= AVX ? 256U : 128U);
3224 }
3225
3226 return true;
3227 }
3228
3229 std::string
convertConstraint(const char * & Constraint) const3230 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3231 switch (*Constraint) {
3232 case 'a': return std::string("{ax}");
3233 case 'b': return std::string("{bx}");
3234 case 'c': return std::string("{cx}");
3235 case 'd': return std::string("{dx}");
3236 case 'S': return std::string("{si}");
3237 case 'D': return std::string("{di}");
3238 case 'p': // address
3239 return std::string("im");
3240 case 't': // top of floating point stack.
3241 return std::string("{st}");
3242 case 'u': // second from top of floating point stack.
3243 return std::string("{st(1)}"); // second from top of floating point stack.
3244 default:
3245 return std::string(1, *Constraint);
3246 }
3247 }
3248 } // end anonymous namespace
3249
3250 namespace {
3251 // X86-32 generic target
3252 class X86_32TargetInfo : public X86TargetInfo {
3253 public:
X86_32TargetInfo(const llvm::Triple & Triple)3254 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3255 DoubleAlign = LongLongAlign = 32;
3256 LongDoubleWidth = 96;
3257 LongDoubleAlign = 32;
3258 SuitableAlign = 128;
3259 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3260 SizeType = UnsignedInt;
3261 PtrDiffType = SignedInt;
3262 IntPtrType = SignedInt;
3263 RegParmMax = 3;
3264
3265 // Use fpret for all types.
3266 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3267 (1 << TargetInfo::Double) |
3268 (1 << TargetInfo::LongDouble));
3269
3270 // x86-32 has atomics up to 8 bytes
3271 // FIXME: Check that we actually have cmpxchg8b before setting
3272 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3273 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3274 }
getBuiltinVaListKind() const3275 BuiltinVaListKind getBuiltinVaListKind() const override {
3276 return TargetInfo::CharPtrBuiltinVaList;
3277 }
3278
getEHDataRegisterNumber(unsigned RegNo) const3279 int getEHDataRegisterNumber(unsigned RegNo) const override {
3280 if (RegNo == 0) return 0;
3281 if (RegNo == 1) return 2;
3282 return -1;
3283 }
validateOperandSize(StringRef Constraint,unsigned Size) const3284 bool validateOperandSize(StringRef Constraint,
3285 unsigned Size) const override {
3286 switch (Constraint[0]) {
3287 default: break;
3288 case 'R':
3289 case 'q':
3290 case 'Q':
3291 case 'a':
3292 case 'b':
3293 case 'c':
3294 case 'd':
3295 case 'S':
3296 case 'D':
3297 return Size <= 32;
3298 case 'A':
3299 return Size <= 64;
3300 }
3301
3302 return X86TargetInfo::validateOperandSize(Constraint, Size);
3303 }
3304 };
3305 } // end anonymous namespace
3306
3307 namespace {
3308 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3309 public:
NetBSDI386TargetInfo(const llvm::Triple & Triple)3310 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3311 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3312
getFloatEvalMethod() const3313 unsigned getFloatEvalMethod() const override {
3314 unsigned Major, Minor, Micro;
3315 getTriple().getOSVersion(Major, Minor, Micro);
3316 // New NetBSD uses the default rounding mode.
3317 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3318 return X86_32TargetInfo::getFloatEvalMethod();
3319 // NetBSD before 6.99.26 defaults to "double" rounding.
3320 return 1;
3321 }
3322 };
3323 } // end anonymous namespace
3324
3325 namespace {
3326 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3327 public:
OpenBSDI386TargetInfo(const llvm::Triple & Triple)3328 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3329 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3330 SizeType = UnsignedLong;
3331 IntPtrType = SignedLong;
3332 PtrDiffType = SignedLong;
3333 }
3334 };
3335 } // end anonymous namespace
3336
3337 namespace {
3338 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3339 public:
BitrigI386TargetInfo(const llvm::Triple & Triple)3340 BitrigI386TargetInfo(const llvm::Triple &Triple)
3341 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3342 SizeType = UnsignedLong;
3343 IntPtrType = SignedLong;
3344 PtrDiffType = SignedLong;
3345 }
3346 };
3347 } // end anonymous namespace
3348
3349 namespace {
3350 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3351 public:
DarwinI386TargetInfo(const llvm::Triple & Triple)3352 DarwinI386TargetInfo(const llvm::Triple &Triple)
3353 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3354 LongDoubleWidth = 128;
3355 LongDoubleAlign = 128;
3356 SuitableAlign = 128;
3357 MaxVectorAlign = 256;
3358 SizeType = UnsignedLong;
3359 IntPtrType = SignedLong;
3360 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3361 HasAlignMac68kSupport = true;
3362 }
3363
3364 };
3365 } // end anonymous namespace
3366
3367 namespace {
3368 // x86-32 Windows target
3369 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3370 public:
WindowsX86_32TargetInfo(const llvm::Triple & Triple)3371 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3372 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3373 WCharType = UnsignedShort;
3374 DoubleAlign = LongLongAlign = 64;
3375 bool IsWinCOFF =
3376 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3377 DescriptionString = IsWinCOFF ? "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
3378 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-S32";
3379 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3380 void getTargetDefines(const LangOptions &Opts,
3381 MacroBuilder &Builder) const override {
3382 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3383 }
3384 };
3385
3386 // x86-32 Windows Visual Studio target
3387 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3388 public:
MicrosoftX86_32TargetInfo(const llvm::Triple & Triple)3389 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3390 : WindowsX86_32TargetInfo(Triple) {
3391 LongDoubleWidth = LongDoubleAlign = 64;
3392 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3393 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3394 void getTargetDefines(const LangOptions &Opts,
3395 MacroBuilder &Builder) const override {
3396 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3397 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3398 // The value of the following reflects processor type.
3399 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3400 // We lost the original triple, so we use the default.
3401 Builder.defineMacro("_M_IX86", "600");
3402 }
3403 };
3404 } // end anonymous namespace
3405
addMinGWDefines(const LangOptions & Opts,MacroBuilder & Builder)3406 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3407 Builder.defineMacro("__MSVCRT__");
3408 Builder.defineMacro("__MINGW32__");
3409
3410 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3411 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3412 // macro anyway for pre-processor compatibility.
3413 if (Opts.MicrosoftExt)
3414 Builder.defineMacro("__declspec", "__declspec");
3415 else
3416 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3417
3418 if (!Opts.MicrosoftExt) {
3419 // Provide macros for all the calling convention keywords. Provide both
3420 // single and double underscore prefixed variants. These are available on
3421 // x64 as well as x86, even though they have no effect.
3422 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3423 for (const char *CC : CCs) {
3424 std::string GCCSpelling = "__attribute__((__";
3425 GCCSpelling += CC;
3426 GCCSpelling += "__))";
3427 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3428 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3429 }
3430 }
3431 }
3432
3433 namespace {
3434 // x86-32 MinGW target
3435 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3436 public:
MinGWX86_32TargetInfo(const llvm::Triple & Triple)3437 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3438 : WindowsX86_32TargetInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3439 void getTargetDefines(const LangOptions &Opts,
3440 MacroBuilder &Builder) const override {
3441 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3442 DefineStd(Builder, "WIN32", Opts);
3443 DefineStd(Builder, "WINNT", Opts);
3444 Builder.defineMacro("_X86_");
3445 addMinGWDefines(Opts, Builder);
3446 }
3447 };
3448 } // end anonymous namespace
3449
3450 namespace {
3451 // x86-32 Cygwin target
3452 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3453 public:
CygwinX86_32TargetInfo(const llvm::Triple & Triple)3454 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3455 : X86_32TargetInfo(Triple) {
3456 TLSSupported = false;
3457 WCharType = UnsignedShort;
3458 DoubleAlign = LongLongAlign = 64;
3459 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3460 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3461 void getTargetDefines(const LangOptions &Opts,
3462 MacroBuilder &Builder) const override {
3463 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3464 Builder.defineMacro("_X86_");
3465 Builder.defineMacro("__CYGWIN__");
3466 Builder.defineMacro("__CYGWIN32__");
3467 DefineStd(Builder, "unix", Opts);
3468 if (Opts.CPlusPlus)
3469 Builder.defineMacro("_GNU_SOURCE");
3470 }
3471 };
3472 } // end anonymous namespace
3473
3474 namespace {
3475 // x86-32 Haiku target
3476 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3477 public:
HaikuX86_32TargetInfo(const llvm::Triple & Triple)3478 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3479 SizeType = UnsignedLong;
3480 IntPtrType = SignedLong;
3481 PtrDiffType = SignedLong;
3482 ProcessIDType = SignedLong;
3483 this->UserLabelPrefix = "";
3484 this->TLSSupported = false;
3485 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3486 void getTargetDefines(const LangOptions &Opts,
3487 MacroBuilder &Builder) const override {
3488 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3489 Builder.defineMacro("__INTEL__");
3490 Builder.defineMacro("__HAIKU__");
3491 }
3492 };
3493 } // end anonymous namespace
3494
3495 // RTEMS Target
3496 template<typename Target>
3497 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3498 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const3499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3500 MacroBuilder &Builder) const override {
3501 // RTEMS defines; list based off of gcc output
3502
3503 Builder.defineMacro("__rtems__");
3504 Builder.defineMacro("__ELF__");
3505 }
3506
3507 public:
RTEMSTargetInfo(const llvm::Triple & Triple)3508 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3509 this->UserLabelPrefix = "";
3510
3511 switch (Triple.getArch()) {
3512 default:
3513 case llvm::Triple::x86:
3514 // this->MCountName = ".mcount";
3515 break;
3516 case llvm::Triple::mips:
3517 case llvm::Triple::mipsel:
3518 case llvm::Triple::ppc:
3519 case llvm::Triple::ppc64:
3520 case llvm::Triple::ppc64le:
3521 // this->MCountName = "_mcount";
3522 break;
3523 case llvm::Triple::arm:
3524 // this->MCountName = "__mcount";
3525 break;
3526 }
3527 }
3528 };
3529
3530 namespace {
3531 // x86-32 RTEMS target
3532 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3533 public:
RTEMSX86_32TargetInfo(const llvm::Triple & Triple)3534 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3535 SizeType = UnsignedLong;
3536 IntPtrType = SignedLong;
3537 PtrDiffType = SignedLong;
3538 this->UserLabelPrefix = "";
3539 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3540 void getTargetDefines(const LangOptions &Opts,
3541 MacroBuilder &Builder) const override {
3542 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3543 Builder.defineMacro("__INTEL__");
3544 Builder.defineMacro("__rtems__");
3545 }
3546 };
3547 } // end anonymous namespace
3548
3549 namespace {
3550 // x86-64 generic target
3551 class X86_64TargetInfo : public X86TargetInfo {
3552 public:
X86_64TargetInfo(const llvm::Triple & Triple)3553 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3554 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3555 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3556 LongDoubleWidth = 128;
3557 LongDoubleAlign = 128;
3558 LargeArrayMinWidth = 128;
3559 LargeArrayAlign = 128;
3560 SuitableAlign = 128;
3561 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3562 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3563 IntPtrType = IsX32 ? SignedInt : SignedLong;
3564 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3565 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3566 RegParmMax = 6;
3567
3568 // Pointers are 32-bit in x32.
3569 DescriptionString = (IsX32)
3570 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3571 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3572
3573 // Use fpret only for long double.
3574 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3575
3576 // Use fp2ret for _Complex long double.
3577 ComplexLongDoubleUsesFP2Ret = true;
3578
3579 // x86-64 has atomics up to 16 bytes.
3580 MaxAtomicPromoteWidth = 128;
3581 MaxAtomicInlineWidth = 128;
3582 }
getBuiltinVaListKind() const3583 BuiltinVaListKind getBuiltinVaListKind() const override {
3584 return TargetInfo::X86_64ABIBuiltinVaList;
3585 }
3586
getEHDataRegisterNumber(unsigned RegNo) const3587 int getEHDataRegisterNumber(unsigned RegNo) const override {
3588 if (RegNo == 0) return 0;
3589 if (RegNo == 1) return 1;
3590 return -1;
3591 }
3592
checkCallingConvention(CallingConv CC) const3593 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3594 return (CC == CC_C ||
3595 CC == CC_X86VectorCall ||
3596 CC == CC_IntelOclBicc ||
3597 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3598 }
3599
getDefaultCallingConv(CallingConvMethodType MT) const3600 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3601 return CC_C;
3602 }
3603
3604 // for x32 we need it here explicitly
hasInt128Type() const3605 bool hasInt128Type() const override { return true; }
3606 };
3607 } // end anonymous namespace
3608
3609 namespace {
3610 // x86-64 Windows target
3611 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3612 public:
WindowsX86_64TargetInfo(const llvm::Triple & Triple)3613 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3614 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3615 WCharType = UnsignedShort;
3616 LongWidth = LongAlign = 32;
3617 DoubleAlign = LongLongAlign = 64;
3618 IntMaxType = SignedLongLong;
3619 Int64Type = SignedLongLong;
3620 SizeType = UnsignedLongLong;
3621 PtrDiffType = SignedLongLong;
3622 IntPtrType = SignedLongLong;
3623 this->UserLabelPrefix = "";
3624 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3625 void getTargetDefines(const LangOptions &Opts,
3626 MacroBuilder &Builder) const override {
3627 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3628 Builder.defineMacro("_WIN64");
3629 }
getBuiltinVaListKind() const3630 BuiltinVaListKind getBuiltinVaListKind() const override {
3631 return TargetInfo::CharPtrBuiltinVaList;
3632 }
checkCallingConvention(CallingConv CC) const3633 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3634 return (CC == CC_C ||
3635 CC == CC_X86VectorCall ||
3636 CC == CC_IntelOclBicc ||
3637 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3638 }
3639 };
3640 } // end anonymous namespace
3641
3642 namespace {
3643 // x86-64 Windows Visual Studio target
3644 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3645 public:
MicrosoftX86_64TargetInfo(const llvm::Triple & Triple)3646 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3647 : WindowsX86_64TargetInfo(Triple) {
3648 LongDoubleWidth = LongDoubleAlign = 64;
3649 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3650 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3651 void getTargetDefines(const LangOptions &Opts,
3652 MacroBuilder &Builder) const override {
3653 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3654 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3655 Builder.defineMacro("_M_X64");
3656 Builder.defineMacro("_M_AMD64");
3657 }
3658 };
3659 } // end anonymous namespace
3660
3661 namespace {
3662 // x86-64 MinGW target
3663 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3664 public:
MinGWX86_64TargetInfo(const llvm::Triple & Triple)3665 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3666 : WindowsX86_64TargetInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3667 void getTargetDefines(const LangOptions &Opts,
3668 MacroBuilder &Builder) const override {
3669 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3670 DefineStd(Builder, "WIN64", Opts);
3671 Builder.defineMacro("__MINGW64__");
3672 addMinGWDefines(Opts, Builder);
3673
3674 // GCC defines this macro when it is using __gxx_personality_seh0.
3675 if (!Opts.SjLjExceptions)
3676 Builder.defineMacro("__SEH__");
3677 }
3678 };
3679 } // end anonymous namespace
3680
3681 namespace {
3682 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3683 public:
DarwinX86_64TargetInfo(const llvm::Triple & Triple)3684 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3685 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3686 Int64Type = SignedLongLong;
3687 MaxVectorAlign = 256;
3688 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3689 llvm::Triple T = llvm::Triple(Triple);
3690 if (T.isiOS())
3691 UseSignedCharForObjCBool = false;
3692 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3693 }
3694 };
3695 } // end anonymous namespace
3696
3697 namespace {
3698 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3699 public:
OpenBSDX86_64TargetInfo(const llvm::Triple & Triple)3700 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3701 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3702 IntMaxType = SignedLongLong;
3703 Int64Type = SignedLongLong;
3704 }
3705 };
3706 } // end anonymous namespace
3707
3708 namespace {
3709 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3710 public:
BitrigX86_64TargetInfo(const llvm::Triple & Triple)3711 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3712 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3713 IntMaxType = SignedLongLong;
3714 Int64Type = SignedLongLong;
3715 }
3716 };
3717 }
3718
3719
3720 namespace {
3721 class ARMTargetInfo : public TargetInfo {
3722 // Possible FPU choices.
3723 enum FPUMode {
3724 VFP2FPU = (1 << 0),
3725 VFP3FPU = (1 << 1),
3726 VFP4FPU = (1 << 2),
3727 NeonFPU = (1 << 3),
3728 FPARMV8 = (1 << 4)
3729 };
3730
3731 // Possible HWDiv features.
3732 enum HWDivMode {
3733 HWDivThumb = (1 << 0),
3734 HWDivARM = (1 << 1)
3735 };
3736
FPUModeIsVFP(FPUMode Mode)3737 static bool FPUModeIsVFP(FPUMode Mode) {
3738 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3739 }
3740
3741 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3742 static const char * const GCCRegNames[];
3743
3744 std::string ABI, CPU;
3745
3746 enum {
3747 FP_Default,
3748 FP_VFP,
3749 FP_Neon
3750 } FPMath;
3751
3752 unsigned FPU : 5;
3753
3754 unsigned IsAAPCS : 1;
3755 unsigned IsThumb : 1;
3756 unsigned HWDiv : 2;
3757
3758 // Initialized via features.
3759 unsigned SoftFloat : 1;
3760 unsigned SoftFloatABI : 1;
3761
3762 unsigned CRC : 1;
3763 unsigned Crypto : 1;
3764
3765 // ACLE 6.5.1 Hardware floating point
3766 enum {
3767 HW_FP_HP = (1 << 1), /// half (16-bit)
3768 HW_FP_SP = (1 << 2), /// single (32-bit)
3769 HW_FP_DP = (1 << 3), /// double (64-bit)
3770 };
3771 uint32_t HW_FP;
3772
3773 static const Builtin::Info BuiltinInfo[];
3774
shouldUseInlineAtomic(const llvm::Triple & T)3775 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3776 StringRef ArchName = T.getArchName();
3777 if (T.getArch() == llvm::Triple::arm ||
3778 T.getArch() == llvm::Triple::armeb) {
3779 StringRef VersionStr;
3780 if (ArchName.startswith("armv"))
3781 VersionStr = ArchName.substr(4, 1);
3782 else if (ArchName.startswith("armebv"))
3783 VersionStr = ArchName.substr(6, 1);
3784 else
3785 return false;
3786 unsigned Version;
3787 if (VersionStr.getAsInteger(10, Version))
3788 return false;
3789 return Version >= 6;
3790 }
3791 assert(T.getArch() == llvm::Triple::thumb ||
3792 T.getArch() == llvm::Triple::thumbeb);
3793 StringRef VersionStr;
3794 if (ArchName.startswith("thumbv"))
3795 VersionStr = ArchName.substr(6, 1);
3796 else if (ArchName.startswith("thumbebv"))
3797 VersionStr = ArchName.substr(8, 1);
3798 else
3799 return false;
3800 unsigned Version;
3801 if (VersionStr.getAsInteger(10, Version))
3802 return false;
3803 return Version >= 7;
3804 }
3805
setABIAAPCS()3806 void setABIAAPCS() {
3807 IsAAPCS = true;
3808
3809 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3810 const llvm::Triple &T = getTriple();
3811
3812 // size_t is unsigned long on MachO-derived environments and NetBSD.
3813 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3814 SizeType = UnsignedLong;
3815 else
3816 SizeType = UnsignedInt;
3817
3818 switch (T.getOS()) {
3819 case llvm::Triple::NetBSD:
3820 WCharType = SignedInt;
3821 break;
3822 case llvm::Triple::Win32:
3823 WCharType = UnsignedShort;
3824 break;
3825 case llvm::Triple::Linux:
3826 default:
3827 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3828 WCharType = UnsignedInt;
3829 break;
3830 }
3831
3832 UseBitFieldTypeAlignment = true;
3833
3834 ZeroLengthBitfieldBoundary = 0;
3835
3836 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3837 // so set preferred for small types to 32.
3838 if (T.isOSBinFormatMachO()) {
3839 DescriptionString =
3840 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3841 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3842 } else if (T.isOSWindows()) {
3843 // FIXME: this is invalid for WindowsCE
3844 assert(!BigEndian && "Windows on ARM does not support big endian");
3845 DescriptionString = "e"
3846 "-m:e"
3847 "-p:32:32"
3848 "-i64:64"
3849 "-v128:64:128"
3850 "-a:0:32"
3851 "-n32"
3852 "-S64";
3853 } else {
3854 DescriptionString =
3855 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3856 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3857 }
3858
3859 // FIXME: Enumerated types are variable width in straight AAPCS.
3860 }
3861
setABIAPCS()3862 void setABIAPCS() {
3863 const llvm::Triple &T = getTriple();
3864
3865 IsAAPCS = false;
3866
3867 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3868
3869 // size_t is unsigned int on FreeBSD.
3870 if (T.getOS() == llvm::Triple::FreeBSD)
3871 SizeType = UnsignedInt;
3872 else
3873 SizeType = UnsignedLong;
3874
3875 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3876 WCharType = SignedInt;
3877
3878 // Do not respect the alignment of bit-field types when laying out
3879 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3880 UseBitFieldTypeAlignment = false;
3881
3882 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3883 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3884 /// gcc.
3885 ZeroLengthBitfieldBoundary = 32;
3886
3887 if (T.isOSBinFormatMachO())
3888 DescriptionString =
3889 BigEndian
3890 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3891 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3892 else
3893 DescriptionString =
3894 BigEndian
3895 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3896 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3897
3898 // FIXME: Override "preferred align" for double and long long.
3899 }
3900
3901 public:
ARMTargetInfo(const llvm::Triple & Triple,bool IsBigEndian)3902 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3903 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3904 IsAAPCS(true), HW_FP(0) {
3905 BigEndian = IsBigEndian;
3906
3907 switch (getTriple().getOS()) {
3908 case llvm::Triple::NetBSD:
3909 PtrDiffType = SignedLong;
3910 break;
3911 default:
3912 PtrDiffType = SignedInt;
3913 break;
3914 }
3915
3916 // {} in inline assembly are neon specifiers, not assembly variant
3917 // specifiers.
3918 NoAsmVariants = true;
3919
3920 // FIXME: Should we just treat this as a feature?
3921 IsThumb = getTriple().getArchName().startswith("thumb");
3922
3923 // FIXME: This duplicates code from the driver that sets the -target-abi
3924 // option - this code is used if -target-abi isn't passed and should
3925 // be unified in some way.
3926 if (Triple.isOSBinFormatMachO()) {
3927 // The backend is hardwired to assume AAPCS for M-class processors, ensure
3928 // the frontend matches that.
3929 if (Triple.getEnvironment() == llvm::Triple::EABI ||
3930 Triple.getOS() == llvm::Triple::UnknownOS ||
3931 StringRef(CPU).startswith("cortex-m")) {
3932 setABI("aapcs");
3933 } else {
3934 setABI("apcs-gnu");
3935 }
3936 } else if (Triple.isOSWindows()) {
3937 // FIXME: this is invalid for WindowsCE
3938 setABI("aapcs");
3939 } else {
3940 // Select the default based on the platform.
3941 switch (Triple.getEnvironment()) {
3942 case llvm::Triple::Android:
3943 case llvm::Triple::GNUEABI:
3944 case llvm::Triple::GNUEABIHF:
3945 setABI("aapcs-linux");
3946 break;
3947 case llvm::Triple::EABIHF:
3948 case llvm::Triple::EABI:
3949 setABI("aapcs");
3950 break;
3951 case llvm::Triple::GNU:
3952 setABI("apcs-gnu");
3953 break;
3954 default:
3955 if (Triple.getOS() == llvm::Triple::NetBSD)
3956 setABI("apcs-gnu");
3957 else
3958 setABI("aapcs");
3959 break;
3960 }
3961 }
3962
3963 // ARM targets default to using the ARM C++ ABI.
3964 TheCXXABI.set(TargetCXXABI::GenericARM);
3965
3966 // ARM has atomics up to 8 bytes
3967 MaxAtomicPromoteWidth = 64;
3968 if (shouldUseInlineAtomic(getTriple()))
3969 MaxAtomicInlineWidth = 64;
3970
3971 // Do force alignment of members that follow zero length bitfields. If
3972 // the alignment of the zero-length bitfield is greater than the member
3973 // that follows it, `bar', `bar' will be aligned as the type of the
3974 // zero length bitfield.
3975 UseZeroLengthBitfieldAlignment = true;
3976 }
getABI() const3977 StringRef getABI() const override { return ABI; }
setABI(const std::string & Name)3978 bool setABI(const std::string &Name) override {
3979 ABI = Name;
3980
3981 // The defaults (above) are for AAPCS, check if we need to change them.
3982 //
3983 // FIXME: We need support for -meabi... we could just mangle it into the
3984 // name.
3985 if (Name == "apcs-gnu") {
3986 setABIAPCS();
3987 return true;
3988 }
3989 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3990 setABIAAPCS();
3991 return true;
3992 }
3993 return false;
3994 }
3995
getDefaultFeatures(llvm::StringMap<bool> & Features) const3996 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3997 StringRef ArchName = getTriple().getArchName();
3998 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3999 Features["vfp2"] = true;
4000 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4001 Features["vfp3"] = true;
4002 Features["neon"] = true;
4003 }
4004 else if (CPU == "cortex-a5") {
4005 Features["vfp4"] = true;
4006 Features["neon"] = true;
4007 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4008 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4009 CPU == "cortex-a17" || CPU == "krait") {
4010 Features["vfp4"] = true;
4011 Features["neon"] = true;
4012 Features["hwdiv"] = true;
4013 Features["hwdiv-arm"] = true;
4014 } else if (CPU == "cyclone") {
4015 Features["v8fp"] = true;
4016 Features["neon"] = true;
4017 Features["hwdiv"] = true;
4018 Features["hwdiv-arm"] = true;
4019 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
4020 Features["fp-armv8"] = true;
4021 Features["neon"] = true;
4022 Features["hwdiv"] = true;
4023 Features["hwdiv-arm"] = true;
4024 Features["crc"] = true;
4025 Features["crypto"] = true;
4026 } else if (CPU == "cortex-r5" ||
4027 // Enable the hwdiv extension for all v8a AArch32 cores by
4028 // default.
4029 ArchName == "armv8a" || ArchName == "armv8" ||
4030 ArchName == "armebv8a" || ArchName == "armebv8" ||
4031 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4032 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4033 Features["hwdiv"] = true;
4034 Features["hwdiv-arm"] = true;
4035 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
4036 Features["hwdiv"] = true;
4037 }
4038 }
4039
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)4040 bool handleTargetFeatures(std::vector<std::string> &Features,
4041 DiagnosticsEngine &Diags) override {
4042 FPU = 0;
4043 CRC = 0;
4044 Crypto = 0;
4045 SoftFloat = SoftFloatABI = false;
4046 HWDiv = 0;
4047
4048 for (const auto &Feature : Features) {
4049 if (Feature == "+soft-float") {
4050 SoftFloat = true;
4051 } else if (Feature == "+soft-float-abi") {
4052 SoftFloatABI = true;
4053 } else if (Feature == "+vfp2") {
4054 FPU |= VFP2FPU;
4055 HW_FP = HW_FP_SP | HW_FP_DP;
4056 } else if (Feature == "+vfp3") {
4057 FPU |= VFP3FPU;
4058 HW_FP = HW_FP_SP | HW_FP_DP;
4059 } else if (Feature == "+vfp4") {
4060 FPU |= VFP4FPU;
4061 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4062 } else if (Feature == "+fp-armv8") {
4063 FPU |= FPARMV8;
4064 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4065 } else if (Feature == "+neon") {
4066 FPU |= NeonFPU;
4067 HW_FP = HW_FP_SP | HW_FP_DP;
4068 } else if (Feature == "+hwdiv") {
4069 HWDiv |= HWDivThumb;
4070 } else if (Feature == "+hwdiv-arm") {
4071 HWDiv |= HWDivARM;
4072 } else if (Feature == "+crc") {
4073 CRC = 1;
4074 } else if (Feature == "+crypto") {
4075 Crypto = 1;
4076 } else if (Feature == "+fp-only-sp") {
4077 HW_FP &= ~HW_FP_DP;
4078 }
4079 }
4080
4081 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4082 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4083 return false;
4084 }
4085
4086 if (FPMath == FP_Neon)
4087 Features.push_back("+neonfp");
4088 else if (FPMath == FP_VFP)
4089 Features.push_back("-neonfp");
4090
4091 // Remove front-end specific options which the backend handles differently.
4092 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4093 for (const auto &FEFeature : FrontEndFeatures) {
4094 auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4095 if (Feature != Features.end())
4096 Features.erase(Feature);
4097 }
4098
4099 return true;
4100 }
4101
hasFeature(StringRef Feature) const4102 bool hasFeature(StringRef Feature) const override {
4103 return llvm::StringSwitch<bool>(Feature)
4104 .Case("arm", true)
4105 .Case("softfloat", SoftFloat)
4106 .Case("thumb", IsThumb)
4107 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4108 .Case("hwdiv", HWDiv & HWDivThumb)
4109 .Case("hwdiv-arm", HWDiv & HWDivARM)
4110 .Default(false);
4111 }
4112 // FIXME: Should we actually have some table instead of these switches?
getCPUDefineSuffix(StringRef Name)4113 static const char *getCPUDefineSuffix(StringRef Name) {
4114 return llvm::StringSwitch<const char *>(Name)
4115 .Cases("arm8", "arm810", "4")
4116 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4117 "4")
4118 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4119 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4120 .Case("ep9312", "4T")
4121 .Cases("arm10tdmi", "arm1020t", "5T")
4122 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4123 .Case("arm926ej-s", "5TEJ")
4124 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4125 .Cases("xscale", "iwmmxt", "5TE")
4126 .Case("arm1136j-s", "6J")
4127 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4128 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4129 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4130 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4131 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4132 "7A")
4133 .Cases("cortex-r4", "cortex-r5", "7R")
4134 .Case("swift", "7S")
4135 .Case("cyclone", "8A")
4136 .Case("cortex-m3", "7M")
4137 .Cases("cortex-m4", "cortex-m7", "7EM")
4138 .Case("cortex-m0", "6M")
4139 .Cases("cortex-a53", "cortex-a57", "8A")
4140 .Default(nullptr);
4141 }
getCPUProfile(StringRef Name)4142 static const char *getCPUProfile(StringRef Name) {
4143 return llvm::StringSwitch<const char *>(Name)
4144 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4145 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4146 "A")
4147 .Cases("cortex-a53", "cortex-a57", "A")
4148 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4149 .Cases("cortex-r4", "cortex-r5", "R")
4150 .Default("");
4151 }
setCPU(const std::string & Name)4152 bool setCPU(const std::string &Name) override {
4153 if (!getCPUDefineSuffix(Name))
4154 return false;
4155
4156 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4157 StringRef Profile = getCPUProfile(Name);
4158 if (Profile == "M" && MaxAtomicInlineWidth) {
4159 MaxAtomicPromoteWidth = 32;
4160 MaxAtomicInlineWidth = 32;
4161 }
4162
4163 CPU = Name;
4164 return true;
4165 }
4166 bool setFPMath(StringRef Name) override;
supportsThumb(StringRef ArchName,StringRef CPUArch,unsigned CPUArchVer) const4167 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4168 unsigned CPUArchVer) const {
4169 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4170 (CPUArch.find('M') != StringRef::npos);
4171 }
supportsThumb2(StringRef ArchName,StringRef CPUArch,unsigned CPUArchVer) const4172 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4173 unsigned CPUArchVer) const {
4174 // We check both CPUArchVer and ArchName because when only triple is
4175 // specified, the default CPU is arm1136j-s.
4176 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4177 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4178 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4179 void getTargetDefines(const LangOptions &Opts,
4180 MacroBuilder &Builder) const override {
4181 // Target identification.
4182 Builder.defineMacro("__arm");
4183 Builder.defineMacro("__arm__");
4184
4185 // Target properties.
4186 Builder.defineMacro("__REGISTER_PREFIX__", "");
4187
4188 StringRef CPUArch = getCPUDefineSuffix(CPU);
4189 unsigned int CPUArchVer;
4190 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4191 llvm_unreachable("Invalid char for architecture version number");
4192 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4193
4194 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4195 StringRef CPUProfile = getCPUProfile(CPU);
4196 StringRef ArchName = getTriple().getArchName();
4197
4198 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4199 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4200 if (CPUArch[0] >= '8') {
4201 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4202 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4203 }
4204
4205 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4206 // is not defined for the M-profile.
4207 // NOTE that the deffault profile is assumed to be 'A'
4208 if (CPUProfile.empty() || CPUProfile != "M")
4209 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4210
4211 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4212 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4213 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4214 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4215 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4216 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4217 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4218
4219 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4220 // instruction set such as ARM or Thumb.
4221 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4222
4223 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4224
4225 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4226 if (!CPUProfile.empty())
4227 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4228
4229 // ACLE 6.5.1 Hardware Floating Point
4230 if (HW_FP)
4231 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4232
4233 // ACLE predefines.
4234 Builder.defineMacro("__ARM_ACLE", "200");
4235
4236 // Subtarget options.
4237
4238 // FIXME: It's more complicated than this and we don't really support
4239 // interworking.
4240 // Windows on ARM does not "support" interworking
4241 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4242 Builder.defineMacro("__THUMB_INTERWORK__");
4243
4244 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4245 // Embedded targets on Darwin follow AAPCS, but not EABI.
4246 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4247 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4248 Builder.defineMacro("__ARM_EABI__");
4249 Builder.defineMacro("__ARM_PCS", "1");
4250
4251 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4252 Builder.defineMacro("__ARM_PCS_VFP", "1");
4253 }
4254
4255 if (SoftFloat)
4256 Builder.defineMacro("__SOFTFP__");
4257
4258 if (CPU == "xscale")
4259 Builder.defineMacro("__XSCALE__");
4260
4261 if (IsThumb) {
4262 Builder.defineMacro("__THUMBEL__");
4263 Builder.defineMacro("__thumb__");
4264 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4265 Builder.defineMacro("__thumb2__");
4266 }
4267 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4268 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4269
4270 // Note, this is always on in gcc, even though it doesn't make sense.
4271 Builder.defineMacro("__APCS_32__");
4272
4273 if (FPUModeIsVFP((FPUMode) FPU)) {
4274 Builder.defineMacro("__VFP_FP__");
4275 if (FPU & VFP2FPU)
4276 Builder.defineMacro("__ARM_VFPV2__");
4277 if (FPU & VFP3FPU)
4278 Builder.defineMacro("__ARM_VFPV3__");
4279 if (FPU & VFP4FPU)
4280 Builder.defineMacro("__ARM_VFPV4__");
4281 }
4282
4283 // This only gets set when Neon instructions are actually available, unlike
4284 // the VFP define, hence the soft float and arch check. This is subtly
4285 // different from gcc, we follow the intent which was that it should be set
4286 // when Neon instructions are actually available.
4287 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4288 Builder.defineMacro("__ARM_NEON");
4289 Builder.defineMacro("__ARM_NEON__");
4290 }
4291
4292 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4293 Opts.ShortWChar ? "2" : "4");
4294
4295 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4296 Opts.ShortEnums ? "1" : "4");
4297
4298 if (CRC)
4299 Builder.defineMacro("__ARM_FEATURE_CRC32");
4300
4301 if (Crypto)
4302 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4303
4304 if (CPUArchVer >= 6 && CPUArch != "6M") {
4305 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4306 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4307 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4309 }
4310
4311 bool is5EOrAbove = (CPUArchVer >= 6 ||
4312 (CPUArchVer == 5 &&
4313 CPUArch.find('E') != StringRef::npos));
4314 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4315 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4316 Builder.defineMacro("__ARM_FEATURE_DSP");
4317 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const4318 void getTargetBuiltins(const Builtin::Info *&Records,
4319 unsigned &NumRecords) const override {
4320 Records = BuiltinInfo;
4321 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4322 }
isCLZForZeroUndef() const4323 bool isCLZForZeroUndef() const override { return false; }
getBuiltinVaListKind() const4324 BuiltinVaListKind getBuiltinVaListKind() const override {
4325 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4326 }
4327 void getGCCRegNames(const char * const *&Names,
4328 unsigned &NumNames) const override;
4329 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4330 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const4331 bool validateAsmConstraint(const char *&Name,
4332 TargetInfo::ConstraintInfo &Info) const override {
4333 switch (*Name) {
4334 default: break;
4335 case 'l': // r0-r7
4336 case 'h': // r8-r15
4337 case 'w': // VFP Floating point register single precision
4338 case 'P': // VFP Floating point register double precision
4339 Info.setAllowsRegister();
4340 return true;
4341 case 'I':
4342 case 'J':
4343 case 'K':
4344 case 'L':
4345 case 'M':
4346 // FIXME
4347 return true;
4348 case 'Q': // A memory address that is a single base register.
4349 Info.setAllowsMemory();
4350 return true;
4351 case 'U': // a memory reference...
4352 switch (Name[1]) {
4353 case 'q': // ...ARMV4 ldrsb
4354 case 'v': // ...VFP load/store (reg+constant offset)
4355 case 'y': // ...iWMMXt load/store
4356 case 't': // address valid for load/store opaque types wider
4357 // than 128-bits
4358 case 'n': // valid address for Neon doubleword vector load/store
4359 case 'm': // valid address for Neon element and structure load/store
4360 case 's': // valid address for non-offset loads/stores of quad-word
4361 // values in four ARM registers
4362 Info.setAllowsMemory();
4363 Name++;
4364 return true;
4365 }
4366 }
4367 return false;
4368 }
convertConstraint(const char * & Constraint) const4369 std::string convertConstraint(const char *&Constraint) const override {
4370 std::string R;
4371 switch (*Constraint) {
4372 case 'U': // Two-character constraint; add "^" hint for later parsing.
4373 R = std::string("^") + std::string(Constraint, 2);
4374 Constraint++;
4375 break;
4376 case 'p': // 'p' should be translated to 'r' by default.
4377 R = std::string("r");
4378 break;
4379 default:
4380 return std::string(1, *Constraint);
4381 }
4382 return R;
4383 }
4384 bool
validateConstraintModifier(StringRef Constraint,char Modifier,unsigned Size,std::string & SuggestedModifier) const4385 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4386 std::string &SuggestedModifier) const override {
4387 bool isOutput = (Constraint[0] == '=');
4388 bool isInOut = (Constraint[0] == '+');
4389
4390 // Strip off constraint modifiers.
4391 while (Constraint[0] == '=' ||
4392 Constraint[0] == '+' ||
4393 Constraint[0] == '&')
4394 Constraint = Constraint.substr(1);
4395
4396 switch (Constraint[0]) {
4397 default: break;
4398 case 'r': {
4399 switch (Modifier) {
4400 default:
4401 return (isInOut || isOutput || Size <= 64);
4402 case 'q':
4403 // A register of size 32 cannot fit a vector type.
4404 return false;
4405 }
4406 }
4407 }
4408
4409 return true;
4410 }
getClobbers() const4411 const char *getClobbers() const override {
4412 // FIXME: Is this really right?
4413 return "";
4414 }
4415
checkCallingConvention(CallingConv CC) const4416 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4417 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4418 }
4419
getEHDataRegisterNumber(unsigned RegNo) const4420 int getEHDataRegisterNumber(unsigned RegNo) const override {
4421 if (RegNo == 0) return 0;
4422 if (RegNo == 1) return 1;
4423 return -1;
4424 }
4425 };
4426
setFPMath(StringRef Name)4427 bool ARMTargetInfo::setFPMath(StringRef Name) {
4428 if (Name == "neon") {
4429 FPMath = FP_Neon;
4430 return true;
4431 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4432 Name == "vfp4") {
4433 FPMath = FP_VFP;
4434 return true;
4435 }
4436 return false;
4437 }
4438
4439 const char * const ARMTargetInfo::GCCRegNames[] = {
4440 // Integer registers
4441 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4442 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4443
4444 // Float registers
4445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4446 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4447 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4448 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4449
4450 // Double registers
4451 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4452 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4453 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4454 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4455
4456 // Quad registers
4457 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4458 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4459 };
4460
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const4461 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4462 unsigned &NumNames) const {
4463 Names = GCCRegNames;
4464 NumNames = llvm::array_lengthof(GCCRegNames);
4465 }
4466
4467 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4468 { { "a1" }, "r0" },
4469 { { "a2" }, "r1" },
4470 { { "a3" }, "r2" },
4471 { { "a4" }, "r3" },
4472 { { "v1" }, "r4" },
4473 { { "v2" }, "r5" },
4474 { { "v3" }, "r6" },
4475 { { "v4" }, "r7" },
4476 { { "v5" }, "r8" },
4477 { { "v6", "rfp" }, "r9" },
4478 { { "sl" }, "r10" },
4479 { { "fp" }, "r11" },
4480 { { "ip" }, "r12" },
4481 { { "r13" }, "sp" },
4482 { { "r14" }, "lr" },
4483 { { "r15" }, "pc" },
4484 // The S, D and Q registers overlap, but aren't really aliases; we
4485 // don't want to substitute one of these for a different-sized one.
4486 };
4487
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const4488 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4489 unsigned &NumAliases) const {
4490 Aliases = GCCRegAliases;
4491 NumAliases = llvm::array_lengthof(GCCRegAliases);
4492 }
4493
4494 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4495 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4496 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4497 ALL_LANGUAGES },
4498 #include "clang/Basic/BuiltinsNEON.def"
4499
4500 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4501 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4502 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4503 ALL_LANGUAGES },
4504 #include "clang/Basic/BuiltinsARM.def"
4505 };
4506
4507 class ARMleTargetInfo : public ARMTargetInfo {
4508 public:
ARMleTargetInfo(const llvm::Triple & Triple)4509 ARMleTargetInfo(const llvm::Triple &Triple)
4510 : ARMTargetInfo(Triple, false) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4511 virtual void getTargetDefines(const LangOptions &Opts,
4512 MacroBuilder &Builder) const {
4513 Builder.defineMacro("__ARMEL__");
4514 ARMTargetInfo::getTargetDefines(Opts, Builder);
4515 }
4516 };
4517
4518 class ARMbeTargetInfo : public ARMTargetInfo {
4519 public:
ARMbeTargetInfo(const llvm::Triple & Triple)4520 ARMbeTargetInfo(const llvm::Triple &Triple)
4521 : ARMTargetInfo(Triple, true) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4522 virtual void getTargetDefines(const LangOptions &Opts,
4523 MacroBuilder &Builder) const {
4524 Builder.defineMacro("__ARMEB__");
4525 Builder.defineMacro("__ARM_BIG_ENDIAN");
4526 ARMTargetInfo::getTargetDefines(Opts, Builder);
4527 }
4528 };
4529 } // end anonymous namespace.
4530
4531 namespace {
4532 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4533 const llvm::Triple Triple;
4534 public:
WindowsARMTargetInfo(const llvm::Triple & Triple)4535 WindowsARMTargetInfo(const llvm::Triple &Triple)
4536 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4537 TLSSupported = false;
4538 WCharType = UnsignedShort;
4539 SizeType = UnsignedInt;
4540 UserLabelPrefix = "";
4541 }
getVisualStudioDefines(const LangOptions & Opts,MacroBuilder & Builder) const4542 void getVisualStudioDefines(const LangOptions &Opts,
4543 MacroBuilder &Builder) const {
4544 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4545
4546 // FIXME: this is invalid for WindowsCE
4547 Builder.defineMacro("_M_ARM_NT", "1");
4548 Builder.defineMacro("_M_ARMT", "_M_ARM");
4549 Builder.defineMacro("_M_THUMB", "_M_ARM");
4550
4551 assert((Triple.getArch() == llvm::Triple::arm ||
4552 Triple.getArch() == llvm::Triple::thumb) &&
4553 "invalid architecture for Windows ARM target info");
4554 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4555 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4556
4557 // TODO map the complete set of values
4558 // 31: VFPv3 40: VFPv4
4559 Builder.defineMacro("_M_ARM_FP", "31");
4560 }
getBuiltinVaListKind() const4561 BuiltinVaListKind getBuiltinVaListKind() const override {
4562 return TargetInfo::CharPtrBuiltinVaList;
4563 }
4564 };
4565
4566 // Windows ARM + Itanium C++ ABI Target
4567 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4568 public:
ItaniumWindowsARMleTargetInfo(const llvm::Triple & Triple)4569 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4570 : WindowsARMTargetInfo(Triple) {
4571 TheCXXABI.set(TargetCXXABI::GenericARM);
4572 }
4573
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4574 void getTargetDefines(const LangOptions &Opts,
4575 MacroBuilder &Builder) const override {
4576 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4577
4578 if (Opts.MSVCCompat)
4579 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4580 }
4581 };
4582
4583 // Windows ARM, MS (C++) ABI
4584 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4585 public:
MicrosoftARMleTargetInfo(const llvm::Triple & Triple)4586 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4587 : WindowsARMTargetInfo(Triple) {
4588 TheCXXABI.set(TargetCXXABI::Microsoft);
4589 }
4590
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4591 void getTargetDefines(const LangOptions &Opts,
4592 MacroBuilder &Builder) const override {
4593 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4594 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4595 }
4596 };
4597 }
4598
4599
4600 namespace {
4601 class DarwinARMTargetInfo :
4602 public DarwinTargetInfo<ARMleTargetInfo> {
4603 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const4604 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4605 MacroBuilder &Builder) const override {
4606 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4607 }
4608
4609 public:
DarwinARMTargetInfo(const llvm::Triple & Triple)4610 DarwinARMTargetInfo(const llvm::Triple &Triple)
4611 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4612 HasAlignMac68kSupport = true;
4613 // iOS always has 64-bit atomic instructions.
4614 // FIXME: This should be based off of the target features in
4615 // ARMleTargetInfo.
4616 MaxAtomicInlineWidth = 64;
4617
4618 // Darwin on iOS uses a variant of the ARM C++ ABI.
4619 TheCXXABI.set(TargetCXXABI::iOS);
4620 }
4621 };
4622 } // end anonymous namespace.
4623
4624
4625 namespace {
4626 class AArch64TargetInfo : public TargetInfo {
4627 virtual void setDescriptionString() = 0;
4628 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4629 static const char *const GCCRegNames[];
4630
4631 enum FPUModeEnum {
4632 FPUMode,
4633 NeonMode
4634 };
4635
4636 unsigned FPU;
4637 unsigned CRC;
4638 unsigned Crypto;
4639
4640 static const Builtin::Info BuiltinInfo[];
4641
4642 std::string ABI;
4643
4644 public:
AArch64TargetInfo(const llvm::Triple & Triple)4645 AArch64TargetInfo(const llvm::Triple &Triple)
4646 : TargetInfo(Triple), ABI("aapcs") {
4647
4648 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4649 WCharType = SignedInt;
4650
4651 // NetBSD apparently prefers consistency across ARM targets to consistency
4652 // across 64-bit targets.
4653 Int64Type = SignedLongLong;
4654 IntMaxType = SignedLongLong;
4655 } else {
4656 WCharType = UnsignedInt;
4657 Int64Type = SignedLong;
4658 IntMaxType = SignedLong;
4659 }
4660
4661 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4662 MaxVectorAlign = 128;
4663 RegParmMax = 8;
4664 MaxAtomicInlineWidth = 128;
4665 MaxAtomicPromoteWidth = 128;
4666
4667 LongDoubleWidth = LongDoubleAlign = 128;
4668 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4669
4670 // {} in inline assembly are neon specifiers, not assembly variant
4671 // specifiers.
4672 NoAsmVariants = true;
4673
4674 // AArch64 targets default to using the ARM C++ ABI.
4675 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4676 }
4677
getABI() const4678 StringRef getABI() const override { return ABI; }
setABI(const std::string & Name)4679 bool setABI(const std::string &Name) override {
4680 if (Name != "aapcs" && Name != "darwinpcs")
4681 return false;
4682
4683 ABI = Name;
4684 return true;
4685 }
4686
setCPU(const std::string & Name)4687 bool setCPU(const std::string &Name) override {
4688 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4689 .Case("generic", true)
4690 .Cases("cortex-a53", "cortex-a57", true)
4691 .Case("cyclone", true)
4692 .Default(false);
4693 return CPUKnown;
4694 }
4695
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4696 virtual void getTargetDefines(const LangOptions &Opts,
4697 MacroBuilder &Builder) const override {
4698 // Target identification.
4699 Builder.defineMacro("__aarch64__");
4700
4701 // Target properties.
4702 Builder.defineMacro("_LP64");
4703 Builder.defineMacro("__LP64__");
4704
4705 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4706 Builder.defineMacro("__ARM_ACLE", "200");
4707 Builder.defineMacro("__ARM_ARCH", "8");
4708 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4709
4710 Builder.defineMacro("__ARM_64BIT_STATE");
4711 Builder.defineMacro("__ARM_PCS_AAPCS64");
4712 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4713
4714 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4715 Builder.defineMacro("__ARM_FEATURE_CLZ");
4716 Builder.defineMacro("__ARM_FEATURE_FMA");
4717 Builder.defineMacro("__ARM_FEATURE_DIV");
4718 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4719 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4720 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4721 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4722
4723 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4724
4725 // 0xe implies support for half, single and double precision operations.
4726 Builder.defineMacro("__ARM_FP", "0xe");
4727
4728 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4729 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4730 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4731
4732 if (Opts.FastMath || Opts.FiniteMathOnly)
4733 Builder.defineMacro("__ARM_FP_FAST");
4734
4735 if (Opts.C99 && !Opts.Freestanding)
4736 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4737
4738 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4739
4740 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4741 Opts.ShortEnums ? "1" : "4");
4742
4743 if (FPU == NeonMode) {
4744 Builder.defineMacro("__ARM_NEON");
4745 // 64-bit NEON supports half, single and double precision operations.
4746 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4747 }
4748
4749 if (CRC)
4750 Builder.defineMacro("__ARM_FEATURE_CRC32");
4751
4752 if (Crypto)
4753 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4754 }
4755
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const4756 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4757 unsigned &NumRecords) const override {
4758 Records = BuiltinInfo;
4759 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4760 }
4761
hasFeature(StringRef Feature) const4762 bool hasFeature(StringRef Feature) const override {
4763 return Feature == "aarch64" ||
4764 Feature == "arm64" ||
4765 (Feature == "neon" && FPU == NeonMode);
4766 }
4767
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)4768 bool handleTargetFeatures(std::vector<std::string> &Features,
4769 DiagnosticsEngine &Diags) override {
4770 FPU = FPUMode;
4771 CRC = 0;
4772 Crypto = 0;
4773 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4774 if (Features[i] == "+neon")
4775 FPU = NeonMode;
4776 if (Features[i] == "+crc")
4777 CRC = 1;
4778 if (Features[i] == "+crypto")
4779 Crypto = 1;
4780 }
4781
4782 setDescriptionString();
4783
4784 return true;
4785 }
4786
isCLZForZeroUndef() const4787 bool isCLZForZeroUndef() const override { return false; }
4788
getBuiltinVaListKind() const4789 BuiltinVaListKind getBuiltinVaListKind() const override {
4790 return TargetInfo::AArch64ABIBuiltinVaList;
4791 }
4792
4793 virtual void getGCCRegNames(const char *const *&Names,
4794 unsigned &NumNames) const override;
4795 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4796 unsigned &NumAliases) const override;
4797
4798 virtual bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const4799 validateAsmConstraint(const char *&Name,
4800 TargetInfo::ConstraintInfo &Info) const override {
4801 switch (*Name) {
4802 default:
4803 return false;
4804 case 'w': // Floating point and SIMD registers (V0-V31)
4805 Info.setAllowsRegister();
4806 return true;
4807 case 'I': // Constant that can be used with an ADD instruction
4808 case 'J': // Constant that can be used with a SUB instruction
4809 case 'K': // Constant that can be used with a 32-bit logical instruction
4810 case 'L': // Constant that can be used with a 64-bit logical instruction
4811 case 'M': // Constant that can be used as a 32-bit MOV immediate
4812 case 'N': // Constant that can be used as a 64-bit MOV immediate
4813 case 'Y': // Floating point constant zero
4814 case 'Z': // Integer constant zero
4815 return true;
4816 case 'Q': // A memory reference with base register and no offset
4817 Info.setAllowsMemory();
4818 return true;
4819 case 'S': // A symbolic address
4820 Info.setAllowsRegister();
4821 return true;
4822 case 'U':
4823 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4824 // Utf: A memory address suitable for ldp/stp in TF mode.
4825 // Usa: An absolute symbolic address.
4826 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4827 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4828 case 'z': // Zero register, wzr or xzr
4829 Info.setAllowsRegister();
4830 return true;
4831 case 'x': // Floating point and SIMD registers (V0-V15)
4832 Info.setAllowsRegister();
4833 return true;
4834 }
4835 return false;
4836 }
4837
4838 bool
validateConstraintModifier(StringRef Constraint,char Modifier,unsigned Size,std::string & SuggestedModifier) const4839 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4840 std::string &SuggestedModifier) const override {
4841 // Strip off constraint modifiers.
4842 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4843 Constraint = Constraint.substr(1);
4844
4845 switch (Constraint[0]) {
4846 default:
4847 return true;
4848 case 'z':
4849 case 'r': {
4850 switch (Modifier) {
4851 case 'x':
4852 case 'w':
4853 // For now assume that the person knows what they're
4854 // doing with the modifier.
4855 return true;
4856 default:
4857 // By default an 'r' constraint will be in the 'x'
4858 // registers.
4859 if (Size == 64)
4860 return true;
4861
4862 SuggestedModifier = "w";
4863 return false;
4864 }
4865 }
4866 }
4867 }
4868
getClobbers() const4869 const char *getClobbers() const override { return ""; }
4870
getEHDataRegisterNumber(unsigned RegNo) const4871 int getEHDataRegisterNumber(unsigned RegNo) const override {
4872 if (RegNo == 0)
4873 return 0;
4874 if (RegNo == 1)
4875 return 1;
4876 return -1;
4877 }
4878 };
4879
4880 const char *const AArch64TargetInfo::GCCRegNames[] = {
4881 // 32-bit Integer registers
4882 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
4883 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4884 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4885
4886 // 64-bit Integer registers
4887 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
4888 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4889 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
4890
4891 // 32-bit floating point regsisters
4892 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
4893 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4894 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4895
4896 // 64-bit floating point regsisters
4897 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
4898 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4899 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4900
4901 // Vector registers
4902 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
4903 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4904 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4905 };
4906
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const4907 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4908 unsigned &NumNames) const {
4909 Names = GCCRegNames;
4910 NumNames = llvm::array_lengthof(GCCRegNames);
4911 }
4912
4913 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4914 { { "w31" }, "wsp" },
4915 { { "x29" }, "fp" },
4916 { { "x30" }, "lr" },
4917 { { "x31" }, "sp" },
4918 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4919 // don't want to substitute one of these for a different-sized one.
4920 };
4921
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const4922 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4923 unsigned &NumAliases) const {
4924 Aliases = GCCRegAliases;
4925 NumAliases = llvm::array_lengthof(GCCRegAliases);
4926 }
4927
4928 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4929 #define BUILTIN(ID, TYPE, ATTRS) \
4930 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4931 #include "clang/Basic/BuiltinsNEON.def"
4932
4933 #define BUILTIN(ID, TYPE, ATTRS) \
4934 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4935 #include "clang/Basic/BuiltinsAArch64.def"
4936 };
4937
4938 class AArch64leTargetInfo : public AArch64TargetInfo {
setDescriptionString()4939 void setDescriptionString() override {
4940 if (getTriple().isOSBinFormatMachO())
4941 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4942 else
4943 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4944 }
4945
4946 public:
AArch64leTargetInfo(const llvm::Triple & Triple)4947 AArch64leTargetInfo(const llvm::Triple &Triple)
4948 : AArch64TargetInfo(Triple) {
4949 BigEndian = false;
4950 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4951 void getTargetDefines(const LangOptions &Opts,
4952 MacroBuilder &Builder) const override {
4953 Builder.defineMacro("__AARCH64EL__");
4954 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4955 }
4956 };
4957
4958 class AArch64beTargetInfo : public AArch64TargetInfo {
setDescriptionString()4959 void setDescriptionString() override {
4960 assert(!getTriple().isOSBinFormatMachO());
4961 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4962 }
4963
4964 public:
AArch64beTargetInfo(const llvm::Triple & Triple)4965 AArch64beTargetInfo(const llvm::Triple &Triple)
4966 : AArch64TargetInfo(Triple) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4967 void getTargetDefines(const LangOptions &Opts,
4968 MacroBuilder &Builder) const override {
4969 Builder.defineMacro("__AARCH64EB__");
4970 Builder.defineMacro("__AARCH_BIG_ENDIAN");
4971 Builder.defineMacro("__ARM_BIG_ENDIAN");
4972 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4973 }
4974 };
4975 } // end anonymous namespace.
4976
4977 namespace {
4978 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4979 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const4980 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4981 MacroBuilder &Builder) const override {
4982 Builder.defineMacro("__AARCH64_SIMD__");
4983 Builder.defineMacro("__ARM64_ARCH_8__");
4984 Builder.defineMacro("__ARM_NEON__");
4985 Builder.defineMacro("__LITTLE_ENDIAN__");
4986 Builder.defineMacro("__REGISTER_PREFIX__", "");
4987 Builder.defineMacro("__arm64", "1");
4988 Builder.defineMacro("__arm64__", "1");
4989
4990 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4991 }
4992
4993 public:
DarwinAArch64TargetInfo(const llvm::Triple & Triple)4994 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4995 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4996 Int64Type = SignedLongLong;
4997 WCharType = SignedInt;
4998 UseSignedCharForObjCBool = false;
4999
5000 LongDoubleWidth = LongDoubleAlign = 64;
5001 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5002
5003 TheCXXABI.set(TargetCXXABI::iOS64);
5004 }
5005
getBuiltinVaListKind() const5006 BuiltinVaListKind getBuiltinVaListKind() const override {
5007 return TargetInfo::CharPtrBuiltinVaList;
5008 }
5009 };
5010 } // end anonymous namespace
5011
5012 namespace {
5013 // Hexagon abstract base class
5014 class HexagonTargetInfo : public TargetInfo {
5015 static const Builtin::Info BuiltinInfo[];
5016 static const char * const GCCRegNames[];
5017 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5018 std::string CPU;
5019 public:
HexagonTargetInfo(const llvm::Triple & Triple)5020 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5021 BigEndian = false;
5022 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5023
5024 // {} in inline assembly are packet specifiers, not assembly variant
5025 // specifiers.
5026 NoAsmVariants = true;
5027 }
5028
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5029 void getTargetBuiltins(const Builtin::Info *&Records,
5030 unsigned &NumRecords) const override {
5031 Records = BuiltinInfo;
5032 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5033 }
5034
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5035 bool validateAsmConstraint(const char *&Name,
5036 TargetInfo::ConstraintInfo &Info) const override {
5037 return true;
5038 }
5039
5040 void getTargetDefines(const LangOptions &Opts,
5041 MacroBuilder &Builder) const override;
5042
hasFeature(StringRef Feature) const5043 bool hasFeature(StringRef Feature) const override {
5044 return Feature == "hexagon";
5045 }
5046
getBuiltinVaListKind() const5047 BuiltinVaListKind getBuiltinVaListKind() const override {
5048 return TargetInfo::CharPtrBuiltinVaList;
5049 }
5050 void getGCCRegNames(const char * const *&Names,
5051 unsigned &NumNames) const override;
5052 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5053 unsigned &NumAliases) const override;
getClobbers() const5054 const char *getClobbers() const override {
5055 return "";
5056 }
5057
getHexagonCPUSuffix(StringRef Name)5058 static const char *getHexagonCPUSuffix(StringRef Name) {
5059 return llvm::StringSwitch<const char*>(Name)
5060 .Case("hexagonv4", "4")
5061 .Case("hexagonv5", "5")
5062 .Default(nullptr);
5063 }
5064
setCPU(const std::string & Name)5065 bool setCPU(const std::string &Name) override {
5066 if (!getHexagonCPUSuffix(Name))
5067 return false;
5068
5069 CPU = Name;
5070 return true;
5071 }
5072 };
5073
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5074 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5075 MacroBuilder &Builder) const {
5076 Builder.defineMacro("qdsp6");
5077 Builder.defineMacro("__qdsp6", "1");
5078 Builder.defineMacro("__qdsp6__", "1");
5079
5080 Builder.defineMacro("hexagon");
5081 Builder.defineMacro("__hexagon", "1");
5082 Builder.defineMacro("__hexagon__", "1");
5083
5084 if(CPU == "hexagonv1") {
5085 Builder.defineMacro("__HEXAGON_V1__");
5086 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5087 if(Opts.HexagonQdsp6Compat) {
5088 Builder.defineMacro("__QDSP6_V1__");
5089 Builder.defineMacro("__QDSP6_ARCH__", "1");
5090 }
5091 }
5092 else if(CPU == "hexagonv2") {
5093 Builder.defineMacro("__HEXAGON_V2__");
5094 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5095 if(Opts.HexagonQdsp6Compat) {
5096 Builder.defineMacro("__QDSP6_V2__");
5097 Builder.defineMacro("__QDSP6_ARCH__", "2");
5098 }
5099 }
5100 else if(CPU == "hexagonv3") {
5101 Builder.defineMacro("__HEXAGON_V3__");
5102 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5103 if(Opts.HexagonQdsp6Compat) {
5104 Builder.defineMacro("__QDSP6_V3__");
5105 Builder.defineMacro("__QDSP6_ARCH__", "3");
5106 }
5107 }
5108 else if(CPU == "hexagonv4") {
5109 Builder.defineMacro("__HEXAGON_V4__");
5110 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5111 if(Opts.HexagonQdsp6Compat) {
5112 Builder.defineMacro("__QDSP6_V4__");
5113 Builder.defineMacro("__QDSP6_ARCH__", "4");
5114 }
5115 }
5116 else if(CPU == "hexagonv5") {
5117 Builder.defineMacro("__HEXAGON_V5__");
5118 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5119 if(Opts.HexagonQdsp6Compat) {
5120 Builder.defineMacro("__QDSP6_V5__");
5121 Builder.defineMacro("__QDSP6_ARCH__", "5");
5122 }
5123 }
5124 }
5125
5126 const char * const HexagonTargetInfo::GCCRegNames[] = {
5127 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5128 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5129 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5130 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5131 "p0", "p1", "p2", "p3",
5132 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5133 };
5134
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5135 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5136 unsigned &NumNames) const {
5137 Names = GCCRegNames;
5138 NumNames = llvm::array_lengthof(GCCRegNames);
5139 }
5140
5141
5142 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5143 { { "sp" }, "r29" },
5144 { { "fp" }, "r30" },
5145 { { "lr" }, "r31" },
5146 };
5147
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5148 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5149 unsigned &NumAliases) const {
5150 Aliases = GCCRegAliases;
5151 NumAliases = llvm::array_lengthof(GCCRegAliases);
5152 }
5153
5154
5155 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5156 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5158 ALL_LANGUAGES },
5159 #include "clang/Basic/BuiltinsHexagon.def"
5160 };
5161 }
5162
5163
5164 namespace {
5165 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5166 class SparcTargetInfo : public TargetInfo {
5167 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5168 static const char * const GCCRegNames[];
5169 bool SoftFloat;
5170 public:
SparcTargetInfo(const llvm::Triple & Triple)5171 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5172
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)5173 bool handleTargetFeatures(std::vector<std::string> &Features,
5174 DiagnosticsEngine &Diags) override {
5175 SoftFloat = false;
5176 for (unsigned i = 0, e = Features.size(); i != e; ++i)
5177 if (Features[i] == "+soft-float")
5178 SoftFloat = true;
5179 return true;
5180 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5181 void getTargetDefines(const LangOptions &Opts,
5182 MacroBuilder &Builder) const override {
5183 DefineStd(Builder, "sparc", Opts);
5184 Builder.defineMacro("__REGISTER_PREFIX__", "");
5185
5186 if (SoftFloat)
5187 Builder.defineMacro("SOFT_FLOAT", "1");
5188 }
5189
hasFeature(StringRef Feature) const5190 bool hasFeature(StringRef Feature) const override {
5191 return llvm::StringSwitch<bool>(Feature)
5192 .Case("softfloat", SoftFloat)
5193 .Case("sparc", true)
5194 .Default(false);
5195 }
5196
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5197 void getTargetBuiltins(const Builtin::Info *&Records,
5198 unsigned &NumRecords) const override {
5199 // FIXME: Implement!
5200 }
getBuiltinVaListKind() const5201 BuiltinVaListKind getBuiltinVaListKind() const override {
5202 return TargetInfo::VoidPtrBuiltinVaList;
5203 }
5204 void getGCCRegNames(const char * const *&Names,
5205 unsigned &NumNames) const override;
5206 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5207 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5208 bool validateAsmConstraint(const char *&Name,
5209 TargetInfo::ConstraintInfo &info) const override {
5210 // FIXME: Implement!
5211 switch (*Name) {
5212 case 'I': // Signed 13-bit constant
5213 case 'J': // Zero
5214 case 'K': // 32-bit constant with the low 12 bits clear
5215 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5216 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5217 case 'N': // Same as 'K' but zext (required for SIMode)
5218 case 'O': // The constant 4096
5219 return true;
5220 }
5221 return false;
5222 }
getClobbers() const5223 const char *getClobbers() const override {
5224 // FIXME: Implement!
5225 return "";
5226 }
5227 };
5228
5229 const char * const SparcTargetInfo::GCCRegNames[] = {
5230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5232 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5233 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5234 };
5235
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5236 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5237 unsigned &NumNames) const {
5238 Names = GCCRegNames;
5239 NumNames = llvm::array_lengthof(GCCRegNames);
5240 }
5241
5242 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5243 { { "g0" }, "r0" },
5244 { { "g1" }, "r1" },
5245 { { "g2" }, "r2" },
5246 { { "g3" }, "r3" },
5247 { { "g4" }, "r4" },
5248 { { "g5" }, "r5" },
5249 { { "g6" }, "r6" },
5250 { { "g7" }, "r7" },
5251 { { "o0" }, "r8" },
5252 { { "o1" }, "r9" },
5253 { { "o2" }, "r10" },
5254 { { "o3" }, "r11" },
5255 { { "o4" }, "r12" },
5256 { { "o5" }, "r13" },
5257 { { "o6", "sp" }, "r14" },
5258 { { "o7" }, "r15" },
5259 { { "l0" }, "r16" },
5260 { { "l1" }, "r17" },
5261 { { "l2" }, "r18" },
5262 { { "l3" }, "r19" },
5263 { { "l4" }, "r20" },
5264 { { "l5" }, "r21" },
5265 { { "l6" }, "r22" },
5266 { { "l7" }, "r23" },
5267 { { "i0" }, "r24" },
5268 { { "i1" }, "r25" },
5269 { { "i2" }, "r26" },
5270 { { "i3" }, "r27" },
5271 { { "i4" }, "r28" },
5272 { { "i5" }, "r29" },
5273 { { "i6", "fp" }, "r30" },
5274 { { "i7" }, "r31" },
5275 };
5276
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5277 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5278 unsigned &NumAliases) const {
5279 Aliases = GCCRegAliases;
5280 NumAliases = llvm::array_lengthof(GCCRegAliases);
5281 }
5282
5283 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5284 class SparcV8TargetInfo : public SparcTargetInfo {
5285 public:
SparcV8TargetInfo(const llvm::Triple & Triple)5286 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5287 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5288 }
5289
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5290 void getTargetDefines(const LangOptions &Opts,
5291 MacroBuilder &Builder) const override {
5292 SparcTargetInfo::getTargetDefines(Opts, Builder);
5293 Builder.defineMacro("__sparcv8");
5294 }
5295 };
5296
5297 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5298 class SparcV9TargetInfo : public SparcTargetInfo {
5299 public:
SparcV9TargetInfo(const llvm::Triple & Triple)5300 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5301 // FIXME: Support Sparc quad-precision long double?
5302 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5303 // This is an LP64 platform.
5304 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5305
5306 // OpenBSD uses long long for int64_t and intmax_t.
5307 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5308 IntMaxType = SignedLongLong;
5309 else
5310 IntMaxType = SignedLong;
5311 Int64Type = IntMaxType;
5312
5313 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5314 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5315 LongDoubleWidth = 128;
5316 LongDoubleAlign = 128;
5317 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5318 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5319 }
5320
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5321 void getTargetDefines(const LangOptions &Opts,
5322 MacroBuilder &Builder) const override {
5323 SparcTargetInfo::getTargetDefines(Opts, Builder);
5324 Builder.defineMacro("__sparcv9");
5325 Builder.defineMacro("__arch64__");
5326 // Solaris doesn't need these variants, but the BSDs do.
5327 if (getTriple().getOS() != llvm::Triple::Solaris) {
5328 Builder.defineMacro("__sparc64__");
5329 Builder.defineMacro("__sparc_v9__");
5330 Builder.defineMacro("__sparcv9__");
5331 }
5332 }
5333
setCPU(const std::string & Name)5334 bool setCPU(const std::string &Name) override {
5335 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5336 .Case("v9", true)
5337 .Case("ultrasparc", true)
5338 .Case("ultrasparc3", true)
5339 .Case("niagara", true)
5340 .Case("niagara2", true)
5341 .Case("niagara3", true)
5342 .Case("niagara4", true)
5343 .Default(false);
5344
5345 // No need to store the CPU yet. There aren't any CPU-specific
5346 // macros to define.
5347 return CPUKnown;
5348 }
5349 };
5350
5351 } // end anonymous namespace.
5352
5353 namespace {
5354 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5355 public:
SolarisSparcV8TargetInfo(const llvm::Triple & Triple)5356 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5357 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5358 SizeType = UnsignedInt;
5359 PtrDiffType = SignedInt;
5360 }
5361 };
5362 } // end anonymous namespace.
5363
5364 namespace {
5365 class SystemZTargetInfo : public TargetInfo {
5366 static const char *const GCCRegNames[];
5367
5368 public:
SystemZTargetInfo(const llvm::Triple & Triple)5369 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5370 TLSSupported = true;
5371 IntWidth = IntAlign = 32;
5372 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5373 PointerWidth = PointerAlign = 64;
5374 LongDoubleWidth = 128;
5375 LongDoubleAlign = 64;
5376 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5377 MinGlobalAlign = 16;
5378 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5379 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5380 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5381 void getTargetDefines(const LangOptions &Opts,
5382 MacroBuilder &Builder) const override {
5383 Builder.defineMacro("__s390__");
5384 Builder.defineMacro("__s390x__");
5385 Builder.defineMacro("__zarch__");
5386 Builder.defineMacro("__LONG_DOUBLE_128__");
5387 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5388 void getTargetBuiltins(const Builtin::Info *&Records,
5389 unsigned &NumRecords) const override {
5390 // FIXME: Implement.
5391 Records = nullptr;
5392 NumRecords = 0;
5393 }
5394
5395 void getGCCRegNames(const char *const *&Names,
5396 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5397 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5398 unsigned &NumAliases) const override {
5399 // No aliases.
5400 Aliases = nullptr;
5401 NumAliases = 0;
5402 }
5403 bool validateAsmConstraint(const char *&Name,
5404 TargetInfo::ConstraintInfo &info) const override;
getClobbers() const5405 const char *getClobbers() const override {
5406 // FIXME: Is this really right?
5407 return "";
5408 }
getBuiltinVaListKind() const5409 BuiltinVaListKind getBuiltinVaListKind() const override {
5410 return TargetInfo::SystemZBuiltinVaList;
5411 }
setCPU(const std::string & Name)5412 bool setCPU(const std::string &Name) override {
5413 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5414 .Case("z10", true)
5415 .Case("z196", true)
5416 .Case("zEC12", true)
5417 .Default(false);
5418
5419 // No need to store the CPU yet. There aren't any CPU-specific
5420 // macros to define.
5421 return CPUKnown;
5422 }
5423 };
5424
5425 const char *const SystemZTargetInfo::GCCRegNames[] = {
5426 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5427 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5428 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5429 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5430 };
5431
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5432 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5433 unsigned &NumNames) const {
5434 Names = GCCRegNames;
5435 NumNames = llvm::array_lengthof(GCCRegNames);
5436 }
5437
5438 bool SystemZTargetInfo::
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5439 validateAsmConstraint(const char *&Name,
5440 TargetInfo::ConstraintInfo &Info) const {
5441 switch (*Name) {
5442 default:
5443 return false;
5444
5445 case 'a': // Address register
5446 case 'd': // Data register (equivalent to 'r')
5447 case 'f': // Floating-point register
5448 Info.setAllowsRegister();
5449 return true;
5450
5451 case 'I': // Unsigned 8-bit constant
5452 case 'J': // Unsigned 12-bit constant
5453 case 'K': // Signed 16-bit constant
5454 case 'L': // Signed 20-bit displacement (on all targets we support)
5455 case 'M': // 0x7fffffff
5456 return true;
5457
5458 case 'Q': // Memory with base and unsigned 12-bit displacement
5459 case 'R': // Likewise, plus an index
5460 case 'S': // Memory with base and signed 20-bit displacement
5461 case 'T': // Likewise, plus an index
5462 Info.setAllowsMemory();
5463 return true;
5464 }
5465 }
5466 }
5467
5468 namespace {
5469 class MSP430TargetInfo : public TargetInfo {
5470 static const char * const GCCRegNames[];
5471 public:
MSP430TargetInfo(const llvm::Triple & Triple)5472 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5473 BigEndian = false;
5474 TLSSupported = false;
5475 IntWidth = 16; IntAlign = 16;
5476 LongWidth = 32; LongLongWidth = 64;
5477 LongAlign = LongLongAlign = 16;
5478 PointerWidth = 16; PointerAlign = 16;
5479 SuitableAlign = 16;
5480 SizeType = UnsignedInt;
5481 IntMaxType = SignedLongLong;
5482 IntPtrType = SignedInt;
5483 PtrDiffType = SignedInt;
5484 SigAtomicType = SignedLong;
5485 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5486 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5487 void getTargetDefines(const LangOptions &Opts,
5488 MacroBuilder &Builder) const override {
5489 Builder.defineMacro("MSP430");
5490 Builder.defineMacro("__MSP430__");
5491 // FIXME: defines for different 'flavours' of MCU
5492 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5493 void getTargetBuiltins(const Builtin::Info *&Records,
5494 unsigned &NumRecords) const override {
5495 // FIXME: Implement.
5496 Records = nullptr;
5497 NumRecords = 0;
5498 }
hasFeature(StringRef Feature) const5499 bool hasFeature(StringRef Feature) const override {
5500 return Feature == "msp430";
5501 }
5502 void getGCCRegNames(const char * const *&Names,
5503 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5504 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5505 unsigned &NumAliases) const override {
5506 // No aliases.
5507 Aliases = nullptr;
5508 NumAliases = 0;
5509 }
5510 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5511 validateAsmConstraint(const char *&Name,
5512 TargetInfo::ConstraintInfo &info) const override {
5513 // FIXME: implement
5514 switch (*Name) {
5515 case 'K': // the constant 1
5516 case 'L': // constant -1^20 .. 1^19
5517 case 'M': // constant 1-4:
5518 return true;
5519 }
5520 // No target constraints for now.
5521 return false;
5522 }
getClobbers() const5523 const char *getClobbers() const override {
5524 // FIXME: Is this really right?
5525 return "";
5526 }
getBuiltinVaListKind() const5527 BuiltinVaListKind getBuiltinVaListKind() const override {
5528 // FIXME: implement
5529 return TargetInfo::CharPtrBuiltinVaList;
5530 }
5531 };
5532
5533 const char * const MSP430TargetInfo::GCCRegNames[] = {
5534 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5535 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5536 };
5537
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5538 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5539 unsigned &NumNames) const {
5540 Names = GCCRegNames;
5541 NumNames = llvm::array_lengthof(GCCRegNames);
5542 }
5543 }
5544
5545 namespace {
5546
5547 // LLVM and Clang cannot be used directly to output native binaries for
5548 // target, but is used to compile C code to llvm bitcode with correct
5549 // type and alignment information.
5550 //
5551 // TCE uses the llvm bitcode as input and uses it for generating customized
5552 // target processor and program binary. TCE co-design environment is
5553 // publicly available in http://tce.cs.tut.fi
5554
5555 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5556 3, // opencl_global
5557 4, // opencl_local
5558 5, // opencl_constant
5559 // FIXME: generic has to be added to the target
5560 0, // opencl_generic
5561 0, // cuda_device
5562 0, // cuda_constant
5563 0 // cuda_shared
5564 };
5565
5566 class TCETargetInfo : public TargetInfo{
5567 public:
TCETargetInfo(const llvm::Triple & Triple)5568 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5569 TLSSupported = false;
5570 IntWidth = 32;
5571 LongWidth = LongLongWidth = 32;
5572 PointerWidth = 32;
5573 IntAlign = 32;
5574 LongAlign = LongLongAlign = 32;
5575 PointerAlign = 32;
5576 SuitableAlign = 32;
5577 SizeType = UnsignedInt;
5578 IntMaxType = SignedLong;
5579 IntPtrType = SignedInt;
5580 PtrDiffType = SignedInt;
5581 FloatWidth = 32;
5582 FloatAlign = 32;
5583 DoubleWidth = 32;
5584 DoubleAlign = 32;
5585 LongDoubleWidth = 32;
5586 LongDoubleAlign = 32;
5587 FloatFormat = &llvm::APFloat::IEEEsingle;
5588 DoubleFormat = &llvm::APFloat::IEEEsingle;
5589 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5590 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5591 "-f64:32-v64:32-v128:32-a:0:32-n32";
5592 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5593 UseAddrSpaceMapMangling = true;
5594 }
5595
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5596 void getTargetDefines(const LangOptions &Opts,
5597 MacroBuilder &Builder) const override {
5598 DefineStd(Builder, "tce", Opts);
5599 Builder.defineMacro("__TCE__");
5600 Builder.defineMacro("__TCE_V1__");
5601 }
hasFeature(StringRef Feature) const5602 bool hasFeature(StringRef Feature) const override {
5603 return Feature == "tce";
5604 }
5605
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5606 void getTargetBuiltins(const Builtin::Info *&Records,
5607 unsigned &NumRecords) const override {}
getClobbers() const5608 const char *getClobbers() const override {
5609 return "";
5610 }
getBuiltinVaListKind() const5611 BuiltinVaListKind getBuiltinVaListKind() const override {
5612 return TargetInfo::VoidPtrBuiltinVaList;
5613 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5614 void getGCCRegNames(const char * const *&Names,
5615 unsigned &NumNames) const override {}
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5616 bool validateAsmConstraint(const char *&Name,
5617 TargetInfo::ConstraintInfo &info) const override{
5618 return true;
5619 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5620 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5621 unsigned &NumAliases) const override {}
5622 };
5623 }
5624
5625 namespace {
5626 class MipsTargetInfoBase : public TargetInfo {
5627 virtual void setDescriptionString() = 0;
5628
5629 static const Builtin::Info BuiltinInfo[];
5630 std::string CPU;
5631 bool IsMips16;
5632 bool IsMicromips;
5633 bool IsNan2008;
5634 bool IsSingleFloat;
5635 enum MipsFloatABI {
5636 HardFloat, SoftFloat
5637 } FloatABI;
5638 enum DspRevEnum {
5639 NoDSP, DSP1, DSP2
5640 } DspRev;
5641 bool HasMSA;
5642
5643 protected:
5644 bool HasFP64;
5645 std::string ABI;
5646
5647 public:
MipsTargetInfoBase(const llvm::Triple & Triple,const std::string & ABIStr,const std::string & CPUStr)5648 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5649 const std::string &CPUStr)
5650 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5651 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5652 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5653 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5654 }
5655
isNaN2008Default() const5656 bool isNaN2008Default() const {
5657 return CPU == "mips32r6" || CPU == "mips64r6";
5658 }
5659
isFP64Default() const5660 bool isFP64Default() const {
5661 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5662 }
5663
getABI() const5664 StringRef getABI() const override { return ABI; }
setCPU(const std::string & Name)5665 bool setCPU(const std::string &Name) override {
5666 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5667 getTriple().getArch() == llvm::Triple::mipsel;
5668 CPU = Name;
5669 return llvm::StringSwitch<bool>(Name)
5670 .Case("mips1", IsMips32)
5671 .Case("mips2", IsMips32)
5672 .Case("mips3", true)
5673 .Case("mips4", true)
5674 .Case("mips5", true)
5675 .Case("mips32", IsMips32)
5676 .Case("mips32r2", IsMips32)
5677 .Case("mips32r6", IsMips32)
5678 .Case("mips64", true)
5679 .Case("mips64r2", true)
5680 .Case("mips64r6", true)
5681 .Case("octeon", true)
5682 .Default(false);
5683 }
getCPU() const5684 const std::string& getCPU() const { return CPU; }
getDefaultFeatures(llvm::StringMap<bool> & Features) const5685 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5686 // The backend enables certain ABI's by default according to the
5687 // architecture.
5688 // Disable both possible defaults so that we don't end up with multiple
5689 // ABI's selected and trigger an assertion.
5690 Features["o32"] = false;
5691 Features["n64"] = false;
5692
5693 Features[ABI] = true;
5694 if (CPU == "octeon")
5695 Features["mips64r2"] = Features["cnmips"] = true;
5696 else
5697 Features[CPU] = true;
5698 }
5699
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5700 void getTargetDefines(const LangOptions &Opts,
5701 MacroBuilder &Builder) const override {
5702 Builder.defineMacro("__mips__");
5703 Builder.defineMacro("_mips");
5704 if (Opts.GNUMode)
5705 Builder.defineMacro("mips");
5706
5707 Builder.defineMacro("__REGISTER_PREFIX__", "");
5708
5709 switch (FloatABI) {
5710 case HardFloat:
5711 Builder.defineMacro("__mips_hard_float", Twine(1));
5712 break;
5713 case SoftFloat:
5714 Builder.defineMacro("__mips_soft_float", Twine(1));
5715 break;
5716 }
5717
5718 if (IsSingleFloat)
5719 Builder.defineMacro("__mips_single_float", Twine(1));
5720
5721 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5722 Builder.defineMacro("_MIPS_FPSET",
5723 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5724
5725 if (IsMips16)
5726 Builder.defineMacro("__mips16", Twine(1));
5727
5728 if (IsMicromips)
5729 Builder.defineMacro("__mips_micromips", Twine(1));
5730
5731 if (IsNan2008)
5732 Builder.defineMacro("__mips_nan2008", Twine(1));
5733
5734 switch (DspRev) {
5735 default:
5736 break;
5737 case DSP1:
5738 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5739 Builder.defineMacro("__mips_dsp", Twine(1));
5740 break;
5741 case DSP2:
5742 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5743 Builder.defineMacro("__mips_dspr2", Twine(1));
5744 Builder.defineMacro("__mips_dsp", Twine(1));
5745 break;
5746 }
5747
5748 if (HasMSA)
5749 Builder.defineMacro("__mips_msa", Twine(1));
5750
5751 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5752 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5753 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5754
5755 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5756 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5757 }
5758
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5759 void getTargetBuiltins(const Builtin::Info *&Records,
5760 unsigned &NumRecords) const override {
5761 Records = BuiltinInfo;
5762 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5763 }
hasFeature(StringRef Feature) const5764 bool hasFeature(StringRef Feature) const override {
5765 return llvm::StringSwitch<bool>(Feature)
5766 .Case("mips", true)
5767 .Case("fp64", HasFP64)
5768 .Default(false);
5769 }
getBuiltinVaListKind() const5770 BuiltinVaListKind getBuiltinVaListKind() const override {
5771 return TargetInfo::VoidPtrBuiltinVaList;
5772 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5773 void getGCCRegNames(const char * const *&Names,
5774 unsigned &NumNames) const override {
5775 static const char *const GCCRegNames[] = {
5776 // CPU register names
5777 // Must match second column of GCCRegAliases
5778 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5779 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5780 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5781 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5782 // Floating point register names
5783 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5784 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5785 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5786 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5787 // Hi/lo and condition register names
5788 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5789 "$fcc5","$fcc6","$fcc7",
5790 // MSA register names
5791 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5792 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5793 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5794 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5795 // MSA control register names
5796 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5797 "$msarequest", "$msamap", "$msaunmap"
5798 };
5799 Names = GCCRegNames;
5800 NumNames = llvm::array_lengthof(GCCRegNames);
5801 }
5802 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5803 unsigned &NumAliases) const override = 0;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5804 bool validateAsmConstraint(const char *&Name,
5805 TargetInfo::ConstraintInfo &Info) const override {
5806 switch (*Name) {
5807 default:
5808 return false;
5809 case 'r': // CPU registers.
5810 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5811 case 'y': // Equivalent to "r", backward compatibility only.
5812 case 'f': // floating-point registers.
5813 case 'c': // $25 for indirect jumps
5814 case 'l': // lo register
5815 case 'x': // hilo register pair
5816 Info.setAllowsRegister();
5817 return true;
5818 case 'I': // Signed 16-bit constant
5819 case 'J': // Integer 0
5820 case 'K': // Unsigned 16-bit constant
5821 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5822 case 'M': // Constants not loadable via lui, addiu, or ori
5823 case 'N': // Constant -1 to -65535
5824 case 'O': // A signed 15-bit constant
5825 case 'P': // A constant between 1 go 65535
5826 return true;
5827 case 'R': // An address that can be used in a non-macro load or store
5828 Info.setAllowsMemory();
5829 return true;
5830 }
5831 }
5832
getClobbers() const5833 const char *getClobbers() const override {
5834 // In GCC, $1 is not widely used in generated code (it's used only in a few
5835 // specific situations), so there is no real need for users to add it to
5836 // the clobbers list if they want to use it in their inline assembly code.
5837 //
5838 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5839 // code generation, so using it in inline assembly without adding it to the
5840 // clobbers list can cause conflicts between the inline assembly code and
5841 // the surrounding generated code.
5842 //
5843 // Another problem is that LLVM is allowed to choose $1 for inline assembly
5844 // operands, which will conflict with the ".set at" assembler option (which
5845 // we use only for inline assembly, in order to maintain compatibility with
5846 // GCC) and will also conflict with the user's usage of $1.
5847 //
5848 // The easiest way to avoid these conflicts and keep $1 as an allocatable
5849 // register for generated code is to automatically clobber $1 for all inline
5850 // assembly code.
5851 //
5852 // FIXME: We should automatically clobber $1 only for inline assembly code
5853 // which actually uses it. This would allow LLVM to use $1 for inline
5854 // assembly operands if the user's assembly code doesn't use it.
5855 return "~{$1}";
5856 }
5857
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)5858 bool handleTargetFeatures(std::vector<std::string> &Features,
5859 DiagnosticsEngine &Diags) override {
5860 IsMips16 = false;
5861 IsMicromips = false;
5862 IsNan2008 = isNaN2008Default();
5863 IsSingleFloat = false;
5864 FloatABI = HardFloat;
5865 DspRev = NoDSP;
5866 HasFP64 = isFP64Default();
5867
5868 for (std::vector<std::string>::iterator it = Features.begin(),
5869 ie = Features.end(); it != ie; ++it) {
5870 if (*it == "+single-float")
5871 IsSingleFloat = true;
5872 else if (*it == "+soft-float")
5873 FloatABI = SoftFloat;
5874 else if (*it == "+mips16")
5875 IsMips16 = true;
5876 else if (*it == "+micromips")
5877 IsMicromips = true;
5878 else if (*it == "+dsp")
5879 DspRev = std::max(DspRev, DSP1);
5880 else if (*it == "+dspr2")
5881 DspRev = std::max(DspRev, DSP2);
5882 else if (*it == "+msa")
5883 HasMSA = true;
5884 else if (*it == "+fp64")
5885 HasFP64 = true;
5886 else if (*it == "-fp64")
5887 HasFP64 = false;
5888 else if (*it == "+nan2008")
5889 IsNan2008 = true;
5890 else if (*it == "-nan2008")
5891 IsNan2008 = false;
5892 }
5893
5894 // Remove front-end specific options.
5895 std::vector<std::string>::iterator it =
5896 std::find(Features.begin(), Features.end(), "+soft-float");
5897 if (it != Features.end())
5898 Features.erase(it);
5899
5900 setDescriptionString();
5901
5902 return true;
5903 }
5904
getEHDataRegisterNumber(unsigned RegNo) const5905 int getEHDataRegisterNumber(unsigned RegNo) const override {
5906 if (RegNo == 0) return 4;
5907 if (RegNo == 1) return 5;
5908 return -1;
5909 }
5910
isCLZForZeroUndef() const5911 bool isCLZForZeroUndef() const override { return false; }
5912 };
5913
5914 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5915 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5916 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5917 ALL_LANGUAGES },
5918 #include "clang/Basic/BuiltinsMips.def"
5919 };
5920
5921 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5922 public:
Mips32TargetInfoBase(const llvm::Triple & Triple)5923 Mips32TargetInfoBase(const llvm::Triple &Triple)
5924 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5925 SizeType = UnsignedInt;
5926 PtrDiffType = SignedInt;
5927 Int64Type = SignedLongLong;
5928 IntMaxType = Int64Type;
5929 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5930 }
setABI(const std::string & Name)5931 bool setABI(const std::string &Name) override {
5932 if (Name == "o32" || Name == "eabi") {
5933 ABI = Name;
5934 return true;
5935 }
5936 return false;
5937 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5938 void getTargetDefines(const LangOptions &Opts,
5939 MacroBuilder &Builder) const override {
5940 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5941
5942 Builder.defineMacro("__mips", "32");
5943 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5944
5945 const std::string& CPUStr = getCPU();
5946 if (CPUStr == "mips32")
5947 Builder.defineMacro("__mips_isa_rev", "1");
5948 else if (CPUStr == "mips32r2")
5949 Builder.defineMacro("__mips_isa_rev", "2");
5950 else if (CPUStr == "mips32r6")
5951 Builder.defineMacro("__mips_isa_rev", "6");
5952
5953 if (ABI == "o32") {
5954 Builder.defineMacro("__mips_o32");
5955 Builder.defineMacro("_ABIO32", "1");
5956 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5957 }
5958 else if (ABI == "eabi")
5959 Builder.defineMacro("__mips_eabi");
5960 else
5961 llvm_unreachable("Invalid ABI for Mips32.");
5962 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5963 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5964 unsigned &NumAliases) const override {
5965 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5966 { { "at" }, "$1" },
5967 { { "v0" }, "$2" },
5968 { { "v1" }, "$3" },
5969 { { "a0" }, "$4" },
5970 { { "a1" }, "$5" },
5971 { { "a2" }, "$6" },
5972 { { "a3" }, "$7" },
5973 { { "t0" }, "$8" },
5974 { { "t1" }, "$9" },
5975 { { "t2" }, "$10" },
5976 { { "t3" }, "$11" },
5977 { { "t4" }, "$12" },
5978 { { "t5" }, "$13" },
5979 { { "t6" }, "$14" },
5980 { { "t7" }, "$15" },
5981 { { "s0" }, "$16" },
5982 { { "s1" }, "$17" },
5983 { { "s2" }, "$18" },
5984 { { "s3" }, "$19" },
5985 { { "s4" }, "$20" },
5986 { { "s5" }, "$21" },
5987 { { "s6" }, "$22" },
5988 { { "s7" }, "$23" },
5989 { { "t8" }, "$24" },
5990 { { "t9" }, "$25" },
5991 { { "k0" }, "$26" },
5992 { { "k1" }, "$27" },
5993 { { "gp" }, "$28" },
5994 { { "sp","$sp" }, "$29" },
5995 { { "fp","$fp" }, "$30" },
5996 { { "ra" }, "$31" }
5997 };
5998 Aliases = GCCRegAliases;
5999 NumAliases = llvm::array_lengthof(GCCRegAliases);
6000 }
6001 };
6002
6003 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
setDescriptionString()6004 void setDescriptionString() override {
6005 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6006 }
6007
6008 public:
Mips32EBTargetInfo(const llvm::Triple & Triple)6009 Mips32EBTargetInfo(const llvm::Triple &Triple)
6010 : Mips32TargetInfoBase(Triple) {
6011 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6012 void getTargetDefines(const LangOptions &Opts,
6013 MacroBuilder &Builder) const override {
6014 DefineStd(Builder, "MIPSEB", Opts);
6015 Builder.defineMacro("_MIPSEB");
6016 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6017 }
6018 };
6019
6020 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
setDescriptionString()6021 void setDescriptionString() override {
6022 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6023 }
6024
6025 public:
Mips32ELTargetInfo(const llvm::Triple & Triple)6026 Mips32ELTargetInfo(const llvm::Triple &Triple)
6027 : Mips32TargetInfoBase(Triple) {
6028 BigEndian = false;
6029 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6030 void getTargetDefines(const LangOptions &Opts,
6031 MacroBuilder &Builder) const override {
6032 DefineStd(Builder, "MIPSEL", Opts);
6033 Builder.defineMacro("_MIPSEL");
6034 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6035 }
6036 };
6037
6038 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6039 public:
Mips64TargetInfoBase(const llvm::Triple & Triple)6040 Mips64TargetInfoBase(const llvm::Triple &Triple)
6041 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6042 LongDoubleWidth = LongDoubleAlign = 128;
6043 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6044 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6045 LongDoubleWidth = LongDoubleAlign = 64;
6046 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6047 }
6048 setN64ABITypes();
6049 SuitableAlign = 128;
6050 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6051 }
6052
setN64ABITypes()6053 void setN64ABITypes() {
6054 LongWidth = LongAlign = 64;
6055 PointerWidth = PointerAlign = 64;
6056 SizeType = UnsignedLong;
6057 PtrDiffType = SignedLong;
6058 Int64Type = SignedLong;
6059 IntMaxType = Int64Type;
6060 }
6061
setN32ABITypes()6062 void setN32ABITypes() {
6063 LongWidth = LongAlign = 32;
6064 PointerWidth = PointerAlign = 32;
6065 SizeType = UnsignedInt;
6066 PtrDiffType = SignedInt;
6067 Int64Type = SignedLongLong;
6068 IntMaxType = Int64Type;
6069 }
6070
setABI(const std::string & Name)6071 bool setABI(const std::string &Name) override {
6072 if (Name == "n32") {
6073 setN32ABITypes();
6074 ABI = Name;
6075 return true;
6076 }
6077 if (Name == "n64") {
6078 setN64ABITypes();
6079 ABI = Name;
6080 return true;
6081 }
6082 return false;
6083 }
6084
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6085 void getTargetDefines(const LangOptions &Opts,
6086 MacroBuilder &Builder) const override {
6087 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6088
6089 Builder.defineMacro("__mips", "64");
6090 Builder.defineMacro("__mips64");
6091 Builder.defineMacro("__mips64__");
6092 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6093
6094 const std::string& CPUStr = getCPU();
6095 if (CPUStr == "mips64")
6096 Builder.defineMacro("__mips_isa_rev", "1");
6097 else if (CPUStr == "mips64r2")
6098 Builder.defineMacro("__mips_isa_rev", "2");
6099 else if (CPUStr == "mips64r6")
6100 Builder.defineMacro("__mips_isa_rev", "6");
6101
6102 if (ABI == "n32") {
6103 Builder.defineMacro("__mips_n32");
6104 Builder.defineMacro("_ABIN32", "2");
6105 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6106 }
6107 else if (ABI == "n64") {
6108 Builder.defineMacro("__mips_n64");
6109 Builder.defineMacro("_ABI64", "3");
6110 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6111 }
6112 else
6113 llvm_unreachable("Invalid ABI for Mips64.");
6114 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6115 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6116 unsigned &NumAliases) const override {
6117 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6118 { { "at" }, "$1" },
6119 { { "v0" }, "$2" },
6120 { { "v1" }, "$3" },
6121 { { "a0" }, "$4" },
6122 { { "a1" }, "$5" },
6123 { { "a2" }, "$6" },
6124 { { "a3" }, "$7" },
6125 { { "a4" }, "$8" },
6126 { { "a5" }, "$9" },
6127 { { "a6" }, "$10" },
6128 { { "a7" }, "$11" },
6129 { { "t0" }, "$12" },
6130 { { "t1" }, "$13" },
6131 { { "t2" }, "$14" },
6132 { { "t3" }, "$15" },
6133 { { "s0" }, "$16" },
6134 { { "s1" }, "$17" },
6135 { { "s2" }, "$18" },
6136 { { "s3" }, "$19" },
6137 { { "s4" }, "$20" },
6138 { { "s5" }, "$21" },
6139 { { "s6" }, "$22" },
6140 { { "s7" }, "$23" },
6141 { { "t8" }, "$24" },
6142 { { "t9" }, "$25" },
6143 { { "k0" }, "$26" },
6144 { { "k1" }, "$27" },
6145 { { "gp" }, "$28" },
6146 { { "sp","$sp" }, "$29" },
6147 { { "fp","$fp" }, "$30" },
6148 { { "ra" }, "$31" }
6149 };
6150 Aliases = GCCRegAliases;
6151 NumAliases = llvm::array_lengthof(GCCRegAliases);
6152 }
6153
hasInt128Type() const6154 bool hasInt128Type() const override { return true; }
6155 };
6156
6157 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
setDescriptionString()6158 void setDescriptionString() override {
6159 if (ABI == "n32")
6160 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6161 else
6162 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6163
6164 }
6165
6166 public:
Mips64EBTargetInfo(const llvm::Triple & Triple)6167 Mips64EBTargetInfo(const llvm::Triple &Triple)
6168 : Mips64TargetInfoBase(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6169 void getTargetDefines(const LangOptions &Opts,
6170 MacroBuilder &Builder) const override {
6171 DefineStd(Builder, "MIPSEB", Opts);
6172 Builder.defineMacro("_MIPSEB");
6173 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6174 }
6175 };
6176
6177 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
setDescriptionString()6178 void setDescriptionString() override {
6179 if (ABI == "n32")
6180 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6181 else
6182 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6183 }
6184 public:
Mips64ELTargetInfo(const llvm::Triple & Triple)6185 Mips64ELTargetInfo(const llvm::Triple &Triple)
6186 : Mips64TargetInfoBase(Triple) {
6187 // Default ABI is n64.
6188 BigEndian = false;
6189 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6190 void getTargetDefines(const LangOptions &Opts,
6191 MacroBuilder &Builder) const override {
6192 DefineStd(Builder, "MIPSEL", Opts);
6193 Builder.defineMacro("_MIPSEL");
6194 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6195 }
6196 };
6197 } // end anonymous namespace.
6198
6199 namespace {
6200 class PNaClTargetInfo : public TargetInfo {
6201 public:
PNaClTargetInfo(const llvm::Triple & Triple)6202 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6203 BigEndian = false;
6204 this->UserLabelPrefix = "";
6205 this->LongAlign = 32;
6206 this->LongWidth = 32;
6207 this->PointerAlign = 32;
6208 this->PointerWidth = 32;
6209 this->IntMaxType = TargetInfo::SignedLongLong;
6210 this->Int64Type = TargetInfo::SignedLongLong;
6211 this->DoubleAlign = 64;
6212 this->LongDoubleWidth = 64;
6213 this->LongDoubleAlign = 64;
6214 this->SizeType = TargetInfo::UnsignedInt;
6215 this->PtrDiffType = TargetInfo::SignedInt;
6216 this->IntPtrType = TargetInfo::SignedInt;
6217 this->RegParmMax = 0; // Disallow regparm
6218 }
6219
getDefaultFeatures(llvm::StringMap<bool> & Features) const6220 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6221 }
getArchDefines(const LangOptions & Opts,MacroBuilder & Builder) const6222 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6223 Builder.defineMacro("__le32__");
6224 Builder.defineMacro("__pnacl__");
6225 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6226 void getTargetDefines(const LangOptions &Opts,
6227 MacroBuilder &Builder) const override {
6228 getArchDefines(Opts, Builder);
6229 }
hasFeature(StringRef Feature) const6230 bool hasFeature(StringRef Feature) const override {
6231 return Feature == "pnacl";
6232 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6233 void getTargetBuiltins(const Builtin::Info *&Records,
6234 unsigned &NumRecords) const override {
6235 }
getBuiltinVaListKind() const6236 BuiltinVaListKind getBuiltinVaListKind() const override {
6237 return TargetInfo::PNaClABIBuiltinVaList;
6238 }
6239 void getGCCRegNames(const char * const *&Names,
6240 unsigned &NumNames) const override;
6241 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6242 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6243 bool validateAsmConstraint(const char *&Name,
6244 TargetInfo::ConstraintInfo &Info) const override {
6245 return false;
6246 }
6247
getClobbers() const6248 const char *getClobbers() const override {
6249 return "";
6250 }
6251 };
6252
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6253 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6254 unsigned &NumNames) const {
6255 Names = nullptr;
6256 NumNames = 0;
6257 }
6258
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6259 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6260 unsigned &NumAliases) const {
6261 Aliases = nullptr;
6262 NumAliases = 0;
6263 }
6264 } // end anonymous namespace.
6265
6266 namespace {
6267 class Le64TargetInfo : public TargetInfo {
6268 static const Builtin::Info BuiltinInfo[];
6269
6270 public:
Le64TargetInfo(const llvm::Triple & Triple)6271 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6272 BigEndian = false;
6273 NoAsmVariants = true;
6274 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6275 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6276 DescriptionString =
6277 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6278 }
6279
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6280 void getTargetDefines(const LangOptions &Opts,
6281 MacroBuilder &Builder) const override {
6282 DefineStd(Builder, "unix", Opts);
6283 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6284 Builder.defineMacro("__ELF__");
6285 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6286 void getTargetBuiltins(const Builtin::Info *&Records,
6287 unsigned &NumRecords) const override {
6288 Records = BuiltinInfo;
6289 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6290 }
getBuiltinVaListKind() const6291 BuiltinVaListKind getBuiltinVaListKind() const override {
6292 return TargetInfo::PNaClABIBuiltinVaList;
6293 }
getClobbers() const6294 const char *getClobbers() const override { return ""; }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6295 void getGCCRegNames(const char *const *&Names,
6296 unsigned &NumNames) const override {
6297 Names = nullptr;
6298 NumNames = 0;
6299 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6300 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6301 unsigned &NumAliases) const override {
6302 Aliases = nullptr;
6303 NumAliases = 0;
6304 }
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6305 bool validateAsmConstraint(const char *&Name,
6306 TargetInfo::ConstraintInfo &Info) const override {
6307 return false;
6308 }
6309
hasProtectedVisibility() const6310 bool hasProtectedVisibility() const override { return false; }
6311 };
6312 } // end anonymous namespace.
6313
6314 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6315 #define BUILTIN(ID, TYPE, ATTRS) \
6316 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6317 #include "clang/Basic/BuiltinsLe64.def"
6318 };
6319
6320 namespace {
6321 static const unsigned SPIRAddrSpaceMap[] = {
6322 1, // opencl_global
6323 3, // opencl_local
6324 2, // opencl_constant
6325 4, // opencl_generic
6326 0, // cuda_device
6327 0, // cuda_constant
6328 0 // cuda_shared
6329 };
6330 class SPIRTargetInfo : public TargetInfo {
6331 public:
SPIRTargetInfo(const llvm::Triple & Triple)6332 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6333 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6334 "SPIR target must use unknown OS");
6335 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6336 "SPIR target must use unknown environment type");
6337 BigEndian = false;
6338 TLSSupported = false;
6339 LongWidth = LongAlign = 64;
6340 AddrSpaceMap = &SPIRAddrSpaceMap;
6341 UseAddrSpaceMapMangling = true;
6342 // Define available target features
6343 // These must be defined in sorted order!
6344 NoAsmVariants = true;
6345 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6346 void getTargetDefines(const LangOptions &Opts,
6347 MacroBuilder &Builder) const override {
6348 DefineStd(Builder, "SPIR", Opts);
6349 }
hasFeature(StringRef Feature) const6350 bool hasFeature(StringRef Feature) const override {
6351 return Feature == "spir";
6352 }
6353
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6354 void getTargetBuiltins(const Builtin::Info *&Records,
6355 unsigned &NumRecords) const override {}
getClobbers() const6356 const char *getClobbers() const override {
6357 return "";
6358 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6359 void getGCCRegNames(const char * const *&Names,
6360 unsigned &NumNames) const override {}
6361 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const6362 validateAsmConstraint(const char *&Name,
6363 TargetInfo::ConstraintInfo &info) const override {
6364 return true;
6365 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6366 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6367 unsigned &NumAliases) const override {}
getBuiltinVaListKind() const6368 BuiltinVaListKind getBuiltinVaListKind() const override {
6369 return TargetInfo::VoidPtrBuiltinVaList;
6370 }
6371 };
6372
6373
6374 class SPIR32TargetInfo : public SPIRTargetInfo {
6375 public:
SPIR32TargetInfo(const llvm::Triple & Triple)6376 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6377 PointerWidth = PointerAlign = 32;
6378 SizeType = TargetInfo::UnsignedInt;
6379 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6380 DescriptionString
6381 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6382 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6383 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6384 void getTargetDefines(const LangOptions &Opts,
6385 MacroBuilder &Builder) const override {
6386 DefineStd(Builder, "SPIR32", Opts);
6387 }
6388 };
6389
6390 class SPIR64TargetInfo : public SPIRTargetInfo {
6391 public:
SPIR64TargetInfo(const llvm::Triple & Triple)6392 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6393 PointerWidth = PointerAlign = 64;
6394 SizeType = TargetInfo::UnsignedLong;
6395 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6396 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6397 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6398 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6399 void getTargetDefines(const LangOptions &Opts,
6400 MacroBuilder &Builder) const override {
6401 DefineStd(Builder, "SPIR64", Opts);
6402 }
6403 };
6404 }
6405
6406 namespace {
6407 class XCoreTargetInfo : public TargetInfo {
6408 static const Builtin::Info BuiltinInfo[];
6409 public:
XCoreTargetInfo(const llvm::Triple & Triple)6410 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6411 BigEndian = false;
6412 NoAsmVariants = true;
6413 LongLongAlign = 32;
6414 SuitableAlign = 32;
6415 DoubleAlign = LongDoubleAlign = 32;
6416 SizeType = UnsignedInt;
6417 PtrDiffType = SignedInt;
6418 IntPtrType = SignedInt;
6419 WCharType = UnsignedChar;
6420 WIntType = UnsignedInt;
6421 UseZeroLengthBitfieldAlignment = true;
6422 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6423 "-f64:32-a:0:32-n32";
6424 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6425 void getTargetDefines(const LangOptions &Opts,
6426 MacroBuilder &Builder) const override {
6427 Builder.defineMacro("__XS1B__");
6428 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6429 void getTargetBuiltins(const Builtin::Info *&Records,
6430 unsigned &NumRecords) const override {
6431 Records = BuiltinInfo;
6432 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6433 }
getBuiltinVaListKind() const6434 BuiltinVaListKind getBuiltinVaListKind() const override {
6435 return TargetInfo::VoidPtrBuiltinVaList;
6436 }
getClobbers() const6437 const char *getClobbers() const override {
6438 return "";
6439 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6440 void getGCCRegNames(const char * const *&Names,
6441 unsigned &NumNames) const override {
6442 static const char * const GCCRegNames[] = {
6443 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6444 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6445 };
6446 Names = GCCRegNames;
6447 NumNames = llvm::array_lengthof(GCCRegNames);
6448 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6449 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6450 unsigned &NumAliases) const override {
6451 Aliases = nullptr;
6452 NumAliases = 0;
6453 }
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6454 bool validateAsmConstraint(const char *&Name,
6455 TargetInfo::ConstraintInfo &Info) const override {
6456 return false;
6457 }
getEHDataRegisterNumber(unsigned RegNo) const6458 int getEHDataRegisterNumber(unsigned RegNo) const override {
6459 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6460 return (RegNo < 2)? RegNo : -1;
6461 }
6462 };
6463
6464 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6465 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6466 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6467 ALL_LANGUAGES },
6468 #include "clang/Basic/BuiltinsXCore.def"
6469 };
6470 } // end anonymous namespace.
6471
6472
6473 //===----------------------------------------------------------------------===//
6474 // Driver code
6475 //===----------------------------------------------------------------------===//
6476
AllocateTarget(const llvm::Triple & Triple)6477 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6478 llvm::Triple::OSType os = Triple.getOS();
6479
6480 switch (Triple.getArch()) {
6481 default:
6482 return nullptr;
6483
6484 case llvm::Triple::xcore:
6485 return new XCoreTargetInfo(Triple);
6486
6487 case llvm::Triple::hexagon:
6488 return new HexagonTargetInfo(Triple);
6489
6490 case llvm::Triple::aarch64:
6491 if (Triple.isOSDarwin())
6492 return new DarwinAArch64TargetInfo(Triple);
6493
6494 switch (os) {
6495 case llvm::Triple::FreeBSD:
6496 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6497 case llvm::Triple::Linux:
6498 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6499 case llvm::Triple::NetBSD:
6500 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6501 default:
6502 return new AArch64leTargetInfo(Triple);
6503 }
6504
6505 case llvm::Triple::aarch64_be:
6506 switch (os) {
6507 case llvm::Triple::FreeBSD:
6508 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6509 case llvm::Triple::Linux:
6510 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6511 case llvm::Triple::NetBSD:
6512 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6513 default:
6514 return new AArch64beTargetInfo(Triple);
6515 }
6516
6517 case llvm::Triple::arm:
6518 case llvm::Triple::thumb:
6519 if (Triple.isOSBinFormatMachO())
6520 return new DarwinARMTargetInfo(Triple);
6521
6522 switch (os) {
6523 case llvm::Triple::Linux:
6524 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6525 case llvm::Triple::FreeBSD:
6526 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6527 case llvm::Triple::Minix:
6528 return new MinixTargetInfo<ARMleTargetInfo>(Triple);
6529 case llvm::Triple::NetBSD:
6530 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6531 case llvm::Triple::OpenBSD:
6532 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6533 case llvm::Triple::Bitrig:
6534 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6535 case llvm::Triple::RTEMS:
6536 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6537 case llvm::Triple::NaCl:
6538 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6539 case llvm::Triple::Win32:
6540 switch (Triple.getEnvironment()) {
6541 default:
6542 return new ARMleTargetInfo(Triple);
6543 case llvm::Triple::Itanium:
6544 return new ItaniumWindowsARMleTargetInfo(Triple);
6545 case llvm::Triple::MSVC:
6546 return new MicrosoftARMleTargetInfo(Triple);
6547 }
6548 default:
6549 return new ARMleTargetInfo(Triple);
6550 }
6551
6552 case llvm::Triple::armeb:
6553 case llvm::Triple::thumbeb:
6554 if (Triple.isOSDarwin())
6555 return new DarwinARMTargetInfo(Triple);
6556
6557 switch (os) {
6558 case llvm::Triple::Linux:
6559 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6560 case llvm::Triple::FreeBSD:
6561 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6562 case llvm::Triple::NetBSD:
6563 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6564 case llvm::Triple::OpenBSD:
6565 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6566 case llvm::Triple::Bitrig:
6567 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6568 case llvm::Triple::RTEMS:
6569 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6570 case llvm::Triple::NaCl:
6571 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6572 default:
6573 return new ARMbeTargetInfo(Triple);
6574 }
6575
6576 case llvm::Triple::msp430:
6577 return new MSP430TargetInfo(Triple);
6578
6579 case llvm::Triple::mips:
6580 switch (os) {
6581 case llvm::Triple::Linux:
6582 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6583 case llvm::Triple::RTEMS:
6584 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6585 case llvm::Triple::FreeBSD:
6586 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6587 case llvm::Triple::NetBSD:
6588 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6589 default:
6590 return new Mips32EBTargetInfo(Triple);
6591 }
6592
6593 case llvm::Triple::mipsel:
6594 switch (os) {
6595 case llvm::Triple::Linux:
6596 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6597 case llvm::Triple::RTEMS:
6598 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6599 case llvm::Triple::FreeBSD:
6600 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6601 case llvm::Triple::NetBSD:
6602 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6603 case llvm::Triple::NaCl:
6604 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6605 default:
6606 return new Mips32ELTargetInfo(Triple);
6607 }
6608
6609 case llvm::Triple::mips64:
6610 switch (os) {
6611 case llvm::Triple::Linux:
6612 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6613 case llvm::Triple::RTEMS:
6614 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6615 case llvm::Triple::FreeBSD:
6616 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6617 case llvm::Triple::NetBSD:
6618 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6619 case llvm::Triple::OpenBSD:
6620 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6621 default:
6622 return new Mips64EBTargetInfo(Triple);
6623 }
6624
6625 case llvm::Triple::mips64el:
6626 switch (os) {
6627 case llvm::Triple::Linux:
6628 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6629 case llvm::Triple::RTEMS:
6630 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6631 case llvm::Triple::FreeBSD:
6632 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6633 case llvm::Triple::NetBSD:
6634 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6635 case llvm::Triple::OpenBSD:
6636 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6637 default:
6638 return new Mips64ELTargetInfo(Triple);
6639 }
6640
6641 case llvm::Triple::le32:
6642 switch (os) {
6643 case llvm::Triple::NaCl:
6644 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6645 default:
6646 return nullptr;
6647 }
6648
6649 case llvm::Triple::le64:
6650 return new Le64TargetInfo(Triple);
6651
6652 case llvm::Triple::ppc:
6653 if (Triple.isOSDarwin())
6654 return new DarwinPPC32TargetInfo(Triple);
6655 switch (os) {
6656 case llvm::Triple::Linux:
6657 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6658 case llvm::Triple::FreeBSD:
6659 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6660 case llvm::Triple::NetBSD:
6661 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6662 case llvm::Triple::OpenBSD:
6663 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6664 case llvm::Triple::RTEMS:
6665 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6666 default:
6667 return new PPC32TargetInfo(Triple);
6668 }
6669
6670 case llvm::Triple::ppc64:
6671 if (Triple.isOSDarwin())
6672 return new DarwinPPC64TargetInfo(Triple);
6673 switch (os) {
6674 case llvm::Triple::Linux:
6675 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6676 case llvm::Triple::Lv2:
6677 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6678 case llvm::Triple::FreeBSD:
6679 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6680 case llvm::Triple::NetBSD:
6681 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6682 default:
6683 return new PPC64TargetInfo(Triple);
6684 }
6685
6686 case llvm::Triple::ppc64le:
6687 switch (os) {
6688 case llvm::Triple::Linux:
6689 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6690 case llvm::Triple::NetBSD:
6691 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6692 default:
6693 return new PPC64TargetInfo(Triple);
6694 }
6695
6696 case llvm::Triple::nvptx:
6697 return new NVPTX32TargetInfo(Triple);
6698 case llvm::Triple::nvptx64:
6699 return new NVPTX64TargetInfo(Triple);
6700
6701 case llvm::Triple::amdgcn:
6702 case llvm::Triple::r600:
6703 return new R600TargetInfo(Triple);
6704
6705 case llvm::Triple::sparc:
6706 switch (os) {
6707 case llvm::Triple::Linux:
6708 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6709 case llvm::Triple::Solaris:
6710 return new SolarisSparcV8TargetInfo(Triple);
6711 case llvm::Triple::NetBSD:
6712 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6713 case llvm::Triple::OpenBSD:
6714 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6715 case llvm::Triple::RTEMS:
6716 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6717 default:
6718 return new SparcV8TargetInfo(Triple);
6719 }
6720
6721 case llvm::Triple::sparcv9:
6722 switch (os) {
6723 case llvm::Triple::Linux:
6724 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6725 case llvm::Triple::Solaris:
6726 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6727 case llvm::Triple::NetBSD:
6728 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6729 case llvm::Triple::OpenBSD:
6730 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6731 case llvm::Triple::FreeBSD:
6732 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6733 default:
6734 return new SparcV9TargetInfo(Triple);
6735 }
6736
6737 case llvm::Triple::systemz:
6738 switch (os) {
6739 case llvm::Triple::Linux:
6740 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6741 default:
6742 return new SystemZTargetInfo(Triple);
6743 }
6744
6745 case llvm::Triple::tce:
6746 return new TCETargetInfo(Triple);
6747
6748 case llvm::Triple::x86:
6749 if (Triple.isOSDarwin())
6750 return new DarwinI386TargetInfo(Triple);
6751
6752 switch (os) {
6753 case llvm::Triple::Linux:
6754 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6755 case llvm::Triple::DragonFly:
6756 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6757 case llvm::Triple::NetBSD:
6758 return new NetBSDI386TargetInfo(Triple);
6759 case llvm::Triple::OpenBSD:
6760 return new OpenBSDI386TargetInfo(Triple);
6761 case llvm::Triple::Bitrig:
6762 return new BitrigI386TargetInfo(Triple);
6763 case llvm::Triple::FreeBSD:
6764 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6765 case llvm::Triple::KFreeBSD:
6766 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6767 case llvm::Triple::Minix:
6768 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6769 case llvm::Triple::Solaris:
6770 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6771 case llvm::Triple::Win32: {
6772 switch (Triple.getEnvironment()) {
6773 default:
6774 return new X86_32TargetInfo(Triple);
6775 case llvm::Triple::Cygnus:
6776 return new CygwinX86_32TargetInfo(Triple);
6777 case llvm::Triple::GNU:
6778 return new MinGWX86_32TargetInfo(Triple);
6779 case llvm::Triple::Itanium:
6780 case llvm::Triple::MSVC:
6781 return new MicrosoftX86_32TargetInfo(Triple);
6782 }
6783 }
6784 case llvm::Triple::Haiku:
6785 return new HaikuX86_32TargetInfo(Triple);
6786 case llvm::Triple::RTEMS:
6787 return new RTEMSX86_32TargetInfo(Triple);
6788 case llvm::Triple::NaCl:
6789 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6790 default:
6791 return new X86_32TargetInfo(Triple);
6792 }
6793
6794 case llvm::Triple::x86_64:
6795 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6796 return new DarwinX86_64TargetInfo(Triple);
6797
6798 switch (os) {
6799 case llvm::Triple::Linux:
6800 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6801 case llvm::Triple::DragonFly:
6802 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6803 case llvm::Triple::NetBSD:
6804 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6805 case llvm::Triple::OpenBSD:
6806 return new OpenBSDX86_64TargetInfo(Triple);
6807 case llvm::Triple::Bitrig:
6808 return new BitrigX86_64TargetInfo(Triple);
6809 case llvm::Triple::FreeBSD:
6810 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6811 case llvm::Triple::KFreeBSD:
6812 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6813 case llvm::Triple::Solaris:
6814 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6815 case llvm::Triple::Win32: {
6816 switch (Triple.getEnvironment()) {
6817 default:
6818 return new X86_64TargetInfo(Triple);
6819 case llvm::Triple::GNU:
6820 return new MinGWX86_64TargetInfo(Triple);
6821 case llvm::Triple::MSVC:
6822 return new MicrosoftX86_64TargetInfo(Triple);
6823 }
6824 }
6825 case llvm::Triple::NaCl:
6826 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6827 default:
6828 return new X86_64TargetInfo(Triple);
6829 }
6830
6831 case llvm::Triple::spir: {
6832 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6833 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6834 return nullptr;
6835 return new SPIR32TargetInfo(Triple);
6836 }
6837 case llvm::Triple::spir64: {
6838 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6839 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6840 return nullptr;
6841 return new SPIR64TargetInfo(Triple);
6842 }
6843 }
6844 }
6845
6846 /// CreateTargetInfo - Return the target info object for the specified target
6847 /// triple.
6848 TargetInfo *
CreateTargetInfo(DiagnosticsEngine & Diags,const std::shared_ptr<TargetOptions> & Opts)6849 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6850 const std::shared_ptr<TargetOptions> &Opts) {
6851 llvm::Triple Triple(Opts->Triple);
6852
6853 // Construct the target
6854 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6855 if (!Target) {
6856 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6857 return nullptr;
6858 }
6859 Target->TargetOpts = Opts;
6860
6861 // Set the target CPU if specified.
6862 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6863 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6864 return nullptr;
6865 }
6866
6867 // Set the target ABI if specified.
6868 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6869 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6870 return nullptr;
6871 }
6872
6873 // Set the fp math unit.
6874 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6875 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6876 return nullptr;
6877 }
6878
6879 // Compute the default target features, we need the target to handle this
6880 // because features may have dependencies on one another.
6881 llvm::StringMap<bool> Features;
6882 Target->getDefaultFeatures(Features);
6883
6884 // Apply the user specified deltas.
6885 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6886 I < N; ++I) {
6887 const char *Name = Opts->FeaturesAsWritten[I].c_str();
6888 // Apply the feature via the target.
6889 bool Enabled = Name[0] == '+';
6890 Target->setFeatureEnabled(Features, Name + 1, Enabled);
6891 }
6892
6893 // Add the features to the compile options.
6894 //
6895 // FIXME: If we are completely confident that we have the right set, we only
6896 // need to pass the minuses.
6897 Opts->Features.clear();
6898 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6899 ie = Features.end(); it != ie; ++it)
6900 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6901 if (!Target->handleTargetFeatures(Opts->Features, Diags))
6902 return nullptr;
6903
6904 return Target.release();
6905 }
6906