1f4a2713aSLionel Sambuc // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \ 2f4a2713aSLionel Sambuc // RUN: | FileCheck %s 3f4a2713aSLionel Sambuc 4f4a2713aSLionel Sambuc // This checks that the frontend will accept inline asm memory constraints. 5f4a2713aSLionel Sambuc foo()6f4a2713aSLionel Sambucint foo() 7f4a2713aSLionel Sambuc { 8f4a2713aSLionel Sambuc 9f4a2713aSLionel Sambuc // 'R': An address that can be used in a non-macro load or stor' 10f4a2713aSLionel Sambuc // This test will result in the higher and lower nibbles being 11f4a2713aSLionel Sambuc // switched due to the lwl/lwr instruction pairs. 12*0a6a1f1dSLionel Sambuc // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R,~{$1}"(i32* %{{[0-9,a-f]+}}) #1, 13f4a2713aSLionel Sambuc 14f4a2713aSLionel Sambuc int c = 0xffbbccdd; 15f4a2713aSLionel Sambuc 16f4a2713aSLionel Sambuc int *p = &c; 17f4a2713aSLionel Sambuc int out = 0; 18f4a2713aSLionel Sambuc 19f4a2713aSLionel Sambuc __asm volatile ( 20f4a2713aSLionel Sambuc "lwl %0, 1 + %1\n\t" 21f4a2713aSLionel Sambuc "lwr %0, 2 + %1\n\t" 22f4a2713aSLionel Sambuc : "=r"(out) 23f4a2713aSLionel Sambuc : "R"(*p) 24f4a2713aSLionel Sambuc ); 25f4a2713aSLionel Sambuc return 0; 26f4a2713aSLionel Sambuc } 27