1//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred_asmoperand : AsmOperandClass { 16 let Name = "ITCondCode"; 17 let ParserMethod = "parseITCondCode"; 18} 19def it_pred : Operand<i32> { 20 let PrintMethod = "printMandatoryPredicateOperand"; 21 let ParserMatchClass = it_pred_asmoperand; 22} 23 24// IT block condition mask 25def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 26def it_mask : Operand<i32> { 27 let PrintMethod = "printThumbITMask"; 28 let ParserMatchClass = it_mask_asmoperand; 29} 30 31// t2_shift_imm: An integer that encodes a shift amount and the type of shift 32// (asr or lsl). The 6-bit immediate encodes as: 33// {5} 0 ==> lsl 34// 1 asr 35// {4-0} imm5 shift amount. 36// asr #32 not allowed 37def t2_shift_imm : Operand<i32> { 38 let PrintMethod = "printShiftImmOperand"; 39 let ParserMatchClass = ShifterImmAsmOperand; 40 let DecoderMethod = "DecodeT2ShifterImmOperand"; 41} 42 43// Shifted operands. No register controlled shifts for Thumb2. 44// Note: We do not support rrx shifted operands yet. 45def t2_so_reg : Operand<i32>, // reg imm 46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 47 [shl,srl,sra,rotr]> { 48 let EncoderMethod = "getT2SORegOpValue"; 49 let PrintMethod = "printT2SOOperand"; 50 let DecoderMethod = "DecodeSORegImmOperand"; 51 let ParserMatchClass = ShiftedImmAsmOperand; 52 let MIOperandInfo = (ops rGPR, i32imm); 53} 54 55// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 56def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 58}]>; 59 60// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 61def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 63}]>; 64 65// so_imm_notSext_XFORM - Return a so_imm value packed into the format 66// described for so_imm_notSext def below, with sign extension from 16 67// bits. 68def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{ 69 APInt apIntN = N->getAPIntValue(); 70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32); 72}]>; 73 74// t2_so_imm - Match a 32-bit immediate operand, which is an 75// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 76// immediate splatted into multiple bytes of the word. 77def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; } 78def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 79 return ARM_AM::getT2SOImmVal(Imm) != -1; 80 }]> { 81 let ParserMatchClass = t2_so_imm_asmoperand; 82 let EncoderMethod = "getT2SOImmOpValue"; 83 let DecoderMethod = "DecodeT2SOImm"; 84} 85 86// t2_so_imm_not - Match an immediate that is a complement 87// of a t2_so_imm. 88// Note: this pattern doesn't require an encoder method and such, as it's 89// only used on aliases (Pat<> and InstAlias<>). The actual encoding 90// is handled by the destination instructions, which use t2_so_imm. 91def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; } 92def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 94}], t2_so_imm_not_XFORM> { 95 let ParserMatchClass = t2_so_imm_not_asmoperand; 96} 97 98// t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm 99// if the upper 16 bits are zero. 100def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{ 101 APInt apIntN = N->getAPIntValue(); 102 if (!apIntN.isIntN(16)) return false; 103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1; 105 }], t2_so_imm_notSext16_XFORM> { 106 let ParserMatchClass = t2_so_imm_not_asmoperand; 107} 108 109// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 110def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; } 111def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 112 int64_t Value = -(int)N->getZExtValue(); 113 return Value && ARM_AM::getT2SOImmVal(Value) != -1; 114}], t2_so_imm_neg_XFORM> { 115 let ParserMatchClass = t2_so_imm_neg_asmoperand; 116} 117 118/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 119def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; } 120def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{ 121 return Imm >= 0 && Imm < 4096; 122}]> { 123 let ParserMatchClass = imm0_4095_asmoperand; 124} 125 126def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; } 127def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{ 128 return (uint32_t)(-N->getZExtValue()) < 4096; 129}], imm_neg_XFORM> { 130 let ParserMatchClass = imm0_4095_neg_asmoperand; 131} 132 133def imm1_255_neg : PatLeaf<(i32 imm), [{ 134 uint32_t Val = -N->getZExtValue(); 135 return (Val > 0 && Val < 255); 136}], imm_neg_XFORM>; 137 138def imm0_255_not : PatLeaf<(i32 imm), [{ 139 return (uint32_t)(~N->getZExtValue()) < 255; 140}], imm_comp_XFORM>; 141 142def lo5AllOne : PatLeaf<(i32 imm), [{ 143 // Returns true if all low 5-bits are 1. 144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 145}]>; 146 147// Define Thumb2 specific addressing modes. 148 149// t2addrmode_imm12 := reg + imm12 150def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 151def t2addrmode_imm12 : Operand<i32>, 152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 153 let PrintMethod = "printAddrModeImm12Operand<false>"; 154 let EncoderMethod = "getAddrModeImm12OpValue"; 155 let DecoderMethod = "DecodeT2AddrModeImm12"; 156 let ParserMatchClass = t2addrmode_imm12_asmoperand; 157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 158} 159 160// t2ldrlabel := imm12 161def t2ldrlabel : Operand<i32> { 162 let EncoderMethod = "getAddrModeImm12OpValue"; 163 let PrintMethod = "printThumbLdrLabelOperand"; 164} 165 166def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";} 167def t2ldr_pcrel_imm12 : Operand<i32> { 168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand; 169 // used for assembler pseudo instruction and maps to t2ldrlabel, so 170 // doesn't need encoder or print methods of its own. 171} 172 173// ADR instruction labels. 174def t2adrlabel : Operand<i32> { 175 let EncoderMethod = "getT2AdrLabelOpValue"; 176 let PrintMethod = "printAdrLabelOperand<0>"; 177} 178 179// t2addrmode_posimm8 := reg + imm8 180def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";} 181def t2addrmode_posimm8 : Operand<i32> { 182 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 183 let EncoderMethod = "getT2AddrModeImm8OpValue"; 184 let DecoderMethod = "DecodeT2AddrModeImm8"; 185 let ParserMatchClass = MemPosImm8OffsetAsmOperand; 186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 187} 188 189// t2addrmode_negimm8 := reg - imm8 190def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";} 191def t2addrmode_negimm8 : Operand<i32>, 192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 193 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 194 let EncoderMethod = "getT2AddrModeImm8OpValue"; 195 let DecoderMethod = "DecodeT2AddrModeImm8"; 196 let ParserMatchClass = MemNegImm8OffsetAsmOperand; 197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 198} 199 200// t2addrmode_imm8 := reg +/- imm8 201def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } 202class T2AddrMode_Imm8 : Operand<i32>, 203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 204 let EncoderMethod = "getT2AddrModeImm8OpValue"; 205 let DecoderMethod = "DecodeT2AddrModeImm8"; 206 let ParserMatchClass = MemImm8OffsetAsmOperand; 207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 208} 209 210def t2addrmode_imm8 : T2AddrMode_Imm8 { 211 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 212} 213 214def t2addrmode_imm8_pre : T2AddrMode_Imm8 { 215 let PrintMethod = "printT2AddrModeImm8Operand<true>"; 216} 217 218def t2am_imm8_offset : Operand<i32>, 219 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 220 [], [SDNPWantRoot]> { 221 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 222 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 223 let DecoderMethod = "DecodeT2Imm8"; 224} 225 226// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 227def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";} 228class T2AddrMode_Imm8s4 : Operand<i32> { 229 let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 230 let DecoderMethod = "DecodeT2AddrModeImm8s4"; 231 let ParserMatchClass = MemImm8s4OffsetAsmOperand; 232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 233} 234 235def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 { 236 let PrintMethod = "printT2AddrModeImm8s4Operand<false>"; 237} 238 239def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 { 240 let PrintMethod = "printT2AddrModeImm8s4Operand<true>"; 241} 242 243def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; } 244def t2am_imm8s4_offset : Operand<i32> { 245 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 246 let EncoderMethod = "getT2Imm8s4OpValue"; 247 let DecoderMethod = "DecodeT2Imm8S4"; 248} 249 250// t2addrmode_imm0_1020s4 := reg + (imm8 << 2) 251def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { 252 let Name = "MemImm0_1020s4Offset"; 253} 254def t2addrmode_imm0_1020s4 : Operand<i32>, 255 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> { 256 let PrintMethod = "printT2AddrModeImm0_1020s4Operand"; 257 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue"; 258 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4"; 259 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand; 260 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 261} 262 263// t2addrmode_so_reg := reg + (reg << imm2) 264def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";} 265def t2addrmode_so_reg : Operand<i32>, 266 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 267 let PrintMethod = "printT2AddrModeSoRegOperand"; 268 let EncoderMethod = "getT2AddrModeSORegOpValue"; 269 let DecoderMethod = "DecodeT2AddrModeSOReg"; 270 let ParserMatchClass = t2addrmode_so_reg_asmoperand; 271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 272} 273 274// Addresses for the TBB/TBH instructions. 275def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; } 276def addrmode_tbb : Operand<i32> { 277 let PrintMethod = "printAddrModeTBB"; 278 let ParserMatchClass = addrmode_tbb_asmoperand; 279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 280} 281def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; } 282def addrmode_tbh : Operand<i32> { 283 let PrintMethod = "printAddrModeTBH"; 284 let ParserMatchClass = addrmode_tbh_asmoperand; 285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 286} 287 288//===----------------------------------------------------------------------===// 289// Multiclass helpers... 290// 291 292 293class T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 294 string opc, string asm, list<dag> pattern> 295 : T2I<oops, iops, itin, opc, asm, pattern> { 296 bits<4> Rd; 297 bits<12> imm; 298 299 let Inst{11-8} = Rd; 300 let Inst{26} = imm{11}; 301 let Inst{14-12} = imm{10-8}; 302 let Inst{7-0} = imm{7-0}; 303} 304 305 306class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 307 string opc, string asm, list<dag> pattern> 308 : T2sI<oops, iops, itin, opc, asm, pattern> { 309 bits<4> Rd; 310 bits<4> Rn; 311 bits<12> imm; 312 313 let Inst{11-8} = Rd; 314 let Inst{26} = imm{11}; 315 let Inst{14-12} = imm{10-8}; 316 let Inst{7-0} = imm{7-0}; 317} 318 319class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 320 string opc, string asm, list<dag> pattern> 321 : T2I<oops, iops, itin, opc, asm, pattern> { 322 bits<4> Rn; 323 bits<12> imm; 324 325 let Inst{19-16} = Rn; 326 let Inst{26} = imm{11}; 327 let Inst{14-12} = imm{10-8}; 328 let Inst{7-0} = imm{7-0}; 329} 330 331 332class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 333 string opc, string asm, list<dag> pattern> 334 : T2I<oops, iops, itin, opc, asm, pattern> { 335 bits<4> Rd; 336 bits<12> ShiftedRm; 337 338 let Inst{11-8} = Rd; 339 let Inst{3-0} = ShiftedRm{3-0}; 340 let Inst{5-4} = ShiftedRm{6-5}; 341 let Inst{14-12} = ShiftedRm{11-9}; 342 let Inst{7-6} = ShiftedRm{8-7}; 343} 344 345class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 346 string opc, string asm, list<dag> pattern> 347 : T2sI<oops, iops, itin, opc, asm, pattern> { 348 bits<4> Rd; 349 bits<12> ShiftedRm; 350 351 let Inst{11-8} = Rd; 352 let Inst{3-0} = ShiftedRm{3-0}; 353 let Inst{5-4} = ShiftedRm{6-5}; 354 let Inst{14-12} = ShiftedRm{11-9}; 355 let Inst{7-6} = ShiftedRm{8-7}; 356} 357 358class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 359 string opc, string asm, list<dag> pattern> 360 : T2I<oops, iops, itin, opc, asm, pattern> { 361 bits<4> Rn; 362 bits<12> ShiftedRm; 363 364 let Inst{19-16} = Rn; 365 let Inst{3-0} = ShiftedRm{3-0}; 366 let Inst{5-4} = ShiftedRm{6-5}; 367 let Inst{14-12} = ShiftedRm{11-9}; 368 let Inst{7-6} = ShiftedRm{8-7}; 369} 370 371class T2TwoReg<dag oops, dag iops, InstrItinClass itin, 372 string opc, string asm, list<dag> pattern> 373 : T2I<oops, iops, itin, opc, asm, pattern> { 374 bits<4> Rd; 375 bits<4> Rm; 376 377 let Inst{11-8} = Rd; 378 let Inst{3-0} = Rm; 379} 380 381class T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 382 string opc, string asm, list<dag> pattern> 383 : T2sI<oops, iops, itin, opc, asm, pattern> { 384 bits<4> Rd; 385 bits<4> Rm; 386 387 let Inst{11-8} = Rd; 388 let Inst{3-0} = Rm; 389} 390 391class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 392 string opc, string asm, list<dag> pattern> 393 : T2I<oops, iops, itin, opc, asm, pattern> { 394 bits<4> Rn; 395 bits<4> Rm; 396 397 let Inst{19-16} = Rn; 398 let Inst{3-0} = Rm; 399} 400 401 402class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 403 string opc, string asm, list<dag> pattern> 404 : T2I<oops, iops, itin, opc, asm, pattern> { 405 bits<4> Rd; 406 bits<4> Rn; 407 bits<12> imm; 408 409 let Inst{11-8} = Rd; 410 let Inst{19-16} = Rn; 411 let Inst{26} = imm{11}; 412 let Inst{14-12} = imm{10-8}; 413 let Inst{7-0} = imm{7-0}; 414} 415 416class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 417 string opc, string asm, list<dag> pattern> 418 : T2sI<oops, iops, itin, opc, asm, pattern> { 419 bits<4> Rd; 420 bits<4> Rn; 421 bits<12> imm; 422 423 let Inst{11-8} = Rd; 424 let Inst{19-16} = Rn; 425 let Inst{26} = imm{11}; 426 let Inst{14-12} = imm{10-8}; 427 let Inst{7-0} = imm{7-0}; 428} 429 430class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 431 string opc, string asm, list<dag> pattern> 432 : T2I<oops, iops, itin, opc, asm, pattern> { 433 bits<4> Rd; 434 bits<4> Rm; 435 bits<5> imm; 436 437 let Inst{11-8} = Rd; 438 let Inst{3-0} = Rm; 439 let Inst{14-12} = imm{4-2}; 440 let Inst{7-6} = imm{1-0}; 441} 442 443class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 444 string opc, string asm, list<dag> pattern> 445 : T2sI<oops, iops, itin, opc, asm, pattern> { 446 bits<4> Rd; 447 bits<4> Rm; 448 bits<5> imm; 449 450 let Inst{11-8} = Rd; 451 let Inst{3-0} = Rm; 452 let Inst{14-12} = imm{4-2}; 453 let Inst{7-6} = imm{1-0}; 454} 455 456class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 457 string opc, string asm, list<dag> pattern> 458 : T2I<oops, iops, itin, opc, asm, pattern> { 459 bits<4> Rd; 460 bits<4> Rn; 461 bits<4> Rm; 462 463 let Inst{11-8} = Rd; 464 let Inst{19-16} = Rn; 465 let Inst{3-0} = Rm; 466} 467 468class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin, 469 string asm, list<dag> pattern> 470 : T2XI<oops, iops, itin, asm, pattern> { 471 bits<4> Rd; 472 bits<4> Rn; 473 bits<4> Rm; 474 475 let Inst{11-8} = Rd; 476 let Inst{19-16} = Rn; 477 let Inst{3-0} = Rm; 478} 479 480class T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 481 string opc, string asm, list<dag> pattern> 482 : T2sI<oops, iops, itin, opc, asm, pattern> { 483 bits<4> Rd; 484 bits<4> Rn; 485 bits<4> Rm; 486 487 let Inst{11-8} = Rd; 488 let Inst{19-16} = Rn; 489 let Inst{3-0} = Rm; 490} 491 492class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 493 string opc, string asm, list<dag> pattern> 494 : T2I<oops, iops, itin, opc, asm, pattern> { 495 bits<4> Rd; 496 bits<4> Rn; 497 bits<12> ShiftedRm; 498 499 let Inst{11-8} = Rd; 500 let Inst{19-16} = Rn; 501 let Inst{3-0} = ShiftedRm{3-0}; 502 let Inst{5-4} = ShiftedRm{6-5}; 503 let Inst{14-12} = ShiftedRm{11-9}; 504 let Inst{7-6} = ShiftedRm{8-7}; 505} 506 507class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 508 string opc, string asm, list<dag> pattern> 509 : T2sI<oops, iops, itin, opc, asm, pattern> { 510 bits<4> Rd; 511 bits<4> Rn; 512 bits<12> ShiftedRm; 513 514 let Inst{11-8} = Rd; 515 let Inst{19-16} = Rn; 516 let Inst{3-0} = ShiftedRm{3-0}; 517 let Inst{5-4} = ShiftedRm{6-5}; 518 let Inst{14-12} = ShiftedRm{11-9}; 519 let Inst{7-6} = ShiftedRm{8-7}; 520} 521 522class T2FourReg<dag oops, dag iops, InstrItinClass itin, 523 string opc, string asm, list<dag> pattern> 524 : T2I<oops, iops, itin, opc, asm, pattern> { 525 bits<4> Rd; 526 bits<4> Rn; 527 bits<4> Rm; 528 bits<4> Ra; 529 530 let Inst{19-16} = Rn; 531 let Inst{15-12} = Ra; 532 let Inst{11-8} = Rd; 533 let Inst{3-0} = Rm; 534} 535 536class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 537 dag oops, dag iops, InstrItinClass itin, 538 string opc, string asm, list<dag> pattern> 539 : T2I<oops, iops, itin, opc, asm, pattern> { 540 bits<4> RdLo; 541 bits<4> RdHi; 542 bits<4> Rn; 543 bits<4> Rm; 544 545 let Inst{31-23} = 0b111110111; 546 let Inst{22-20} = opc22_20; 547 let Inst{19-16} = Rn; 548 let Inst{15-12} = RdLo; 549 let Inst{11-8} = RdHi; 550 let Inst{7-4} = opc7_4; 551 let Inst{3-0} = Rm; 552} 553class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, 554 dag oops, dag iops, InstrItinClass itin, 555 string opc, string asm, list<dag> pattern> 556 : T2I<oops, iops, itin, opc, asm, pattern> { 557 bits<4> RdLo; 558 bits<4> RdHi; 559 bits<4> Rn; 560 bits<4> Rm; 561 562 let Inst{31-23} = 0b111110111; 563 let Inst{22-20} = opc22_20; 564 let Inst{19-16} = Rn; 565 let Inst{15-12} = RdLo; 566 let Inst{11-8} = RdHi; 567 let Inst{7-4} = opc7_4; 568 let Inst{3-0} = Rm; 569} 570 571 572/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 573/// binary operation that produces a value. These are predicable and can be 574/// changed to modify CPSR. 575multiclass T2I_bin_irs<bits<4> opcod, string opc, 576 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 577 PatFrag opnode, bit Commutable = 0, 578 string wide = ""> { 579 // shifted imm 580 def ri : T2sTwoRegImm< 581 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 582 opc, "\t$Rd, $Rn, $imm", 583 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, 584 Sched<[WriteALU, ReadALU]> { 585 let Inst{31-27} = 0b11110; 586 let Inst{25} = 0; 587 let Inst{24-21} = opcod; 588 let Inst{15} = 0; 589 } 590 // register 591 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 592 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 593 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 594 Sched<[WriteALU, ReadALU, ReadALU]> { 595 let isCommutable = Commutable; 596 let Inst{31-27} = 0b11101; 597 let Inst{26-25} = 0b01; 598 let Inst{24-21} = opcod; 599 let Inst{14-12} = 0b000; // imm3 600 let Inst{7-6} = 0b00; // imm2 601 let Inst{5-4} = 0b00; // type 602 } 603 // shifted register 604 def rs : T2sTwoRegShiftedReg< 605 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 606 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 607 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, 608 Sched<[WriteALUsi, ReadALU]> { 609 let Inst{31-27} = 0b11101; 610 let Inst{26-25} = 0b01; 611 let Inst{24-21} = opcod; 612 } 613 // Assembly aliases for optional destination operand when it's the same 614 // as the source operand. 615 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 616 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, 617 t2_so_imm:$imm, pred:$p, 618 cc_out:$s)>; 619 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 620 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, 621 rGPR:$Rm, pred:$p, 622 cc_out:$s)>; 623 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 624 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, 625 t2_so_reg:$shift, pred:$p, 626 cc_out:$s)>; 627} 628 629/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 630// the ".w" suffix to indicate that they are wide. 631multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 632 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 633 PatFrag opnode, bit Commutable = 0> : 634 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> { 635 // Assembler aliases w/ the ".w" suffix. 636 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"), 637 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, 638 cc_out:$s)>; 639 // Assembler aliases w/o the ".w" suffix. 640 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 641 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 642 cc_out:$s)>; 643 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 644 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, 645 pred:$p, cc_out:$s)>; 646 647 // and with the optional destination operand, too. 648 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"), 649 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, 650 pred:$p, cc_out:$s)>; 651 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 652 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 653 cc_out:$s)>; 654 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 655 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, 656 pred:$p, cc_out:$s)>; 657} 658 659/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 660/// reversed. The 'rr' form is only defined for the disassembler; for codegen 661/// it is equivalent to the T2I_bin_irs counterpart. 662multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { 663 // shifted imm 664 def ri : T2sTwoRegImm< 665 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 666 opc, ".w\t$Rd, $Rn, $imm", 667 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>, 668 Sched<[WriteALU, ReadALU]> { 669 let Inst{31-27} = 0b11110; 670 let Inst{25} = 0; 671 let Inst{24-21} = opcod; 672 let Inst{15} = 0; 673 } 674 // register 675 def rr : T2sThreeReg< 676 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 677 opc, "\t$Rd, $Rn, $Rm", 678 [/* For disassembly only; pattern left blank */]>, 679 Sched<[WriteALU, ReadALU, ReadALU]> { 680 let Inst{31-27} = 0b11101; 681 let Inst{26-25} = 0b01; 682 let Inst{24-21} = opcod; 683 let Inst{14-12} = 0b000; // imm3 684 let Inst{7-6} = 0b00; // imm2 685 let Inst{5-4} = 0b00; // type 686 } 687 // shifted register 688 def rs : T2sTwoRegShiftedReg< 689 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 690 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 691 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>, 692 Sched<[WriteALUsi, ReadALU]> { 693 let Inst{31-27} = 0b11101; 694 let Inst{26-25} = 0b01; 695 let Inst{24-21} = opcod; 696 } 697} 698 699/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 700/// instruction modifies the CPSR register. 701/// 702/// These opcodes will be converted to the real non-S opcodes by 703/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 704let hasPostISelHook = 1, Defs = [CPSR] in { 705multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 706 InstrItinClass iis, PatFrag opnode, 707 bit Commutable = 0> { 708 // shifted imm 709 def ri : t2PseudoInst<(outs rGPR:$Rd), 710 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p), 711 4, iii, 712 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 713 t2_so_imm:$imm))]>, 714 Sched<[WriteALU, ReadALU]>; 715 // register 716 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p), 717 4, iir, 718 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 719 rGPR:$Rm))]>, 720 Sched<[WriteALU, ReadALU, ReadALU]> { 721 let isCommutable = Commutable; 722 } 723 // shifted register 724 def rs : t2PseudoInst<(outs rGPR:$Rd), 725 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 726 4, iis, 727 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 728 t2_so_reg:$ShiftedRm))]>, 729 Sched<[WriteALUsi, ReadALUsr]>; 730} 731} 732 733/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG 734/// operands are reversed. 735let hasPostISelHook = 1, Defs = [CPSR] in { 736multiclass T2I_rbin_s_is<PatFrag opnode> { 737 // shifted imm 738 def ri : t2PseudoInst<(outs rGPR:$Rd), 739 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p), 740 4, IIC_iALUi, 741 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, 742 rGPR:$Rn))]>, 743 Sched<[WriteALU, ReadALU]>; 744 // shifted register 745 def rs : t2PseudoInst<(outs rGPR:$Rd), 746 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 747 4, IIC_iALUsi, 748 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, 749 rGPR:$Rn))]>, 750 Sched<[WriteALUsi, ReadALU]>; 751} 752} 753 754/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 755/// patterns for a binary operation that produces a value. 756multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 757 bit Commutable = 0> { 758 // shifted imm 759 // The register-immediate version is re-materializable. This is useful 760 // in particular for taking the address of a local. 761 let isReMaterializable = 1 in { 762 def ri : T2sTwoRegImm< 763 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 764 opc, ".w\t$Rd, $Rn, $imm", 765 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>, 766 Sched<[WriteALU, ReadALU]> { 767 let Inst{31-27} = 0b11110; 768 let Inst{25} = 0; 769 let Inst{24} = 1; 770 let Inst{23-21} = op23_21; 771 let Inst{15} = 0; 772 } 773 } 774 // 12-bit imm 775 def ri12 : T2I< 776 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 777 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 778 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>, 779 Sched<[WriteALU, ReadALU]> { 780 bits<4> Rd; 781 bits<4> Rn; 782 bits<12> imm; 783 let Inst{31-27} = 0b11110; 784 let Inst{26} = imm{11}; 785 let Inst{25-24} = 0b10; 786 let Inst{23-21} = op23_21; 787 let Inst{20} = 0; // The S bit. 788 let Inst{19-16} = Rn; 789 let Inst{15} = 0; 790 let Inst{14-12} = imm{10-8}; 791 let Inst{11-8} = Rd; 792 let Inst{7-0} = imm{7-0}; 793 } 794 // register 795 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), 796 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", 797 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>, 798 Sched<[WriteALU, ReadALU, ReadALU]> { 799 let isCommutable = Commutable; 800 let Inst{31-27} = 0b11101; 801 let Inst{26-25} = 0b01; 802 let Inst{24} = 1; 803 let Inst{23-21} = op23_21; 804 let Inst{14-12} = 0b000; // imm3 805 let Inst{7-6} = 0b00; // imm2 806 let Inst{5-4} = 0b00; // type 807 } 808 // shifted register 809 def rs : T2sTwoRegShiftedReg< 810 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 811 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 812 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>, 813 Sched<[WriteALUsi, ReadALU]> { 814 let Inst{31-27} = 0b11101; 815 let Inst{26-25} = 0b01; 816 let Inst{24} = 1; 817 let Inst{23-21} = op23_21; 818 } 819} 820 821/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 822/// for a binary operation that produces a value and use the carry 823/// bit. It's not predicable. 824let Defs = [CPSR], Uses = [CPSR] in { 825multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 826 bit Commutable = 0> { 827 // shifted imm 828 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 829 IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 830 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 831 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> { 832 let Inst{31-27} = 0b11110; 833 let Inst{25} = 0; 834 let Inst{24-21} = opcod; 835 let Inst{15} = 0; 836 } 837 // register 838 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 839 opc, ".w\t$Rd, $Rn, $Rm", 840 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 841 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> { 842 let isCommutable = Commutable; 843 let Inst{31-27} = 0b11101; 844 let Inst{26-25} = 0b01; 845 let Inst{24-21} = opcod; 846 let Inst{14-12} = 0b000; // imm3 847 let Inst{7-6} = 0b00; // imm2 848 let Inst{5-4} = 0b00; // type 849 } 850 // shifted register 851 def rs : T2sTwoRegShiftedReg< 852 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 853 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 854 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 855 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { 856 let Inst{31-27} = 0b11101; 857 let Inst{26-25} = 0b01; 858 let Inst{24-21} = opcod; 859 } 860} 861} 862 863/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 864// rotate operation that produces a value. 865multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> { 866 // 5-bit imm 867 def ri : T2sTwoRegShiftImm< 868 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 869 opc, ".w\t$Rd, $Rm, $imm", 870 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>, 871 Sched<[WriteALU]> { 872 let Inst{31-27} = 0b11101; 873 let Inst{26-21} = 0b010010; 874 let Inst{19-16} = 0b1111; // Rn 875 let Inst{5-4} = opcod; 876 } 877 // register 878 def rr : T2sThreeReg< 879 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 880 opc, ".w\t$Rd, $Rn, $Rm", 881 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 882 Sched<[WriteALU]> { 883 let Inst{31-27} = 0b11111; 884 let Inst{26-23} = 0b0100; 885 let Inst{22-21} = opcod; 886 let Inst{15-12} = 0b1111; 887 let Inst{7-4} = 0b0000; 888 } 889 890 // Optional destination register 891 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 892 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 893 cc_out:$s)>; 894 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 895 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 896 cc_out:$s)>; 897 898 // Assembler aliases w/o the ".w" suffix. 899 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 900 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p, 901 cc_out:$s)>; 902 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 903 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 904 cc_out:$s)>; 905 906 // and with the optional destination operand, too. 907 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 908 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 909 cc_out:$s)>; 910 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 911 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 912 cc_out:$s)>; 913} 914 915/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 916/// patterns. Similar to T2I_bin_irs except the instruction does not produce 917/// a explicit result, only implicitly set CPSR. 918multiclass T2I_cmp_irs<bits<4> opcod, string opc, 919 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 920 PatFrag opnode> { 921let isCompare = 1, Defs = [CPSR] in { 922 // shifted imm 923 def ri : T2OneRegCmpImm< 924 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, 925 opc, ".w\t$Rn, $imm", 926 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> { 927 let Inst{31-27} = 0b11110; 928 let Inst{25} = 0; 929 let Inst{24-21} = opcod; 930 let Inst{20} = 1; // The S bit. 931 let Inst{15} = 0; 932 let Inst{11-8} = 0b1111; // Rd 933 } 934 // register 935 def rr : T2TwoRegCmp< 936 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir, 937 opc, ".w\t$Rn, $Rm", 938 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> { 939 let Inst{31-27} = 0b11101; 940 let Inst{26-25} = 0b01; 941 let Inst{24-21} = opcod; 942 let Inst{20} = 1; // The S bit. 943 let Inst{14-12} = 0b000; // imm3 944 let Inst{11-8} = 0b1111; // Rd 945 let Inst{7-6} = 0b00; // imm2 946 let Inst{5-4} = 0b00; // type 947 } 948 // shifted register 949 def rs : T2OneRegCmpShiftedReg< 950 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, 951 opc, ".w\t$Rn, $ShiftedRm", 952 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>, 953 Sched<[WriteCMPsi]> { 954 let Inst{31-27} = 0b11101; 955 let Inst{26-25} = 0b01; 956 let Inst{24-21} = opcod; 957 let Inst{20} = 1; // The S bit. 958 let Inst{11-8} = 0b1111; // Rd 959 } 960} 961 962 // Assembler aliases w/o the ".w" suffix. 963 // No alias here for 'rr' version as not all instantiations of this 964 // multiclass want one (CMP in particular, does not). 965 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 966 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>; 967 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 968 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>; 969} 970 971/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 972multiclass T2I_ld<bit signed, bits<2> opcod, string opc, 973 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 974 PatFrag opnode> { 975 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 976 opc, ".w\t$Rt, $addr", 977 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> { 978 bits<4> Rt; 979 bits<17> addr; 980 let Inst{31-25} = 0b1111100; 981 let Inst{24} = signed; 982 let Inst{23} = 1; 983 let Inst{22-21} = opcod; 984 let Inst{20} = 1; // load 985 let Inst{19-16} = addr{16-13}; // Rn 986 let Inst{15-12} = Rt; 987 let Inst{11-0} = addr{11-0}; // imm 988 989 let DecoderMethod = "DecodeT2LoadImm12"; 990 } 991 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 992 opc, "\t$Rt, $addr", 993 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> { 994 bits<4> Rt; 995 bits<13> addr; 996 let Inst{31-27} = 0b11111; 997 let Inst{26-25} = 0b00; 998 let Inst{24} = signed; 999 let Inst{23} = 0; 1000 let Inst{22-21} = opcod; 1001 let Inst{20} = 1; // load 1002 let Inst{19-16} = addr{12-9}; // Rn 1003 let Inst{15-12} = Rt; 1004 let Inst{11} = 1; 1005 // Offset: index==TRUE, wback==FALSE 1006 let Inst{10} = 1; // The P bit. 1007 let Inst{9} = addr{8}; // U 1008 let Inst{8} = 0; // The W bit. 1009 let Inst{7-0} = addr{7-0}; // imm 1010 1011 let DecoderMethod = "DecodeT2LoadImm8"; 1012 } 1013 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 1014 opc, ".w\t$Rt, $addr", 1015 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> { 1016 let Inst{31-27} = 0b11111; 1017 let Inst{26-25} = 0b00; 1018 let Inst{24} = signed; 1019 let Inst{23} = 0; 1020 let Inst{22-21} = opcod; 1021 let Inst{20} = 1; // load 1022 let Inst{11-6} = 0b000000; 1023 1024 bits<4> Rt; 1025 let Inst{15-12} = Rt; 1026 1027 bits<10> addr; 1028 let Inst{19-16} = addr{9-6}; // Rn 1029 let Inst{3-0} = addr{5-2}; // Rm 1030 let Inst{5-4} = addr{1-0}; // imm 1031 1032 let DecoderMethod = "DecodeT2LoadShift"; 1033 } 1034 1035 // pci variant is very similar to i12, but supports negative offsets 1036 // from the PC. 1037 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 1038 opc, ".w\t$Rt, $addr", 1039 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { 1040 let isReMaterializable = 1; 1041 let Inst{31-27} = 0b11111; 1042 let Inst{26-25} = 0b00; 1043 let Inst{24} = signed; 1044 let Inst{22-21} = opcod; 1045 let Inst{20} = 1; // load 1046 let Inst{19-16} = 0b1111; // Rn 1047 1048 bits<4> Rt; 1049 let Inst{15-12} = Rt{3-0}; 1050 1051 bits<13> addr; 1052 let Inst{23} = addr{12}; // add = (U == '1') 1053 let Inst{11-0} = addr{11-0}; 1054 1055 let DecoderMethod = "DecodeT2LoadLabel"; 1056 } 1057} 1058 1059/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 1060multiclass T2I_st<bits<2> opcod, string opc, 1061 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 1062 PatFrag opnode> { 1063 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 1064 opc, ".w\t$Rt, $addr", 1065 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> { 1066 let Inst{31-27} = 0b11111; 1067 let Inst{26-23} = 0b0001; 1068 let Inst{22-21} = opcod; 1069 let Inst{20} = 0; // !load 1070 1071 bits<4> Rt; 1072 let Inst{15-12} = Rt; 1073 1074 bits<17> addr; 1075 let addr{12} = 1; // add = TRUE 1076 let Inst{19-16} = addr{16-13}; // Rn 1077 let Inst{23} = addr{12}; // U 1078 let Inst{11-0} = addr{11-0}; // imm 1079 } 1080 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 1081 opc, "\t$Rt, $addr", 1082 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> { 1083 let Inst{31-27} = 0b11111; 1084 let Inst{26-23} = 0b0000; 1085 let Inst{22-21} = opcod; 1086 let Inst{20} = 0; // !load 1087 let Inst{11} = 1; 1088 // Offset: index==TRUE, wback==FALSE 1089 let Inst{10} = 1; // The P bit. 1090 let Inst{8} = 0; // The W bit. 1091 1092 bits<4> Rt; 1093 let Inst{15-12} = Rt; 1094 1095 bits<13> addr; 1096 let Inst{19-16} = addr{12-9}; // Rn 1097 let Inst{9} = addr{8}; // U 1098 let Inst{7-0} = addr{7-0}; // imm 1099 } 1100 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 1101 opc, ".w\t$Rt, $addr", 1102 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> { 1103 let Inst{31-27} = 0b11111; 1104 let Inst{26-23} = 0b0000; 1105 let Inst{22-21} = opcod; 1106 let Inst{20} = 0; // !load 1107 let Inst{11-6} = 0b000000; 1108 1109 bits<4> Rt; 1110 let Inst{15-12} = Rt; 1111 1112 bits<10> addr; 1113 let Inst{19-16} = addr{9-6}; // Rn 1114 let Inst{3-0} = addr{5-2}; // Rm 1115 let Inst{5-4} = addr{1-0}; // imm 1116 } 1117} 1118 1119/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 1120/// register and one whose operand is a register rotated by 8/16/24. 1121class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> 1122 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1123 opc, ".w\t$Rd, $Rm$rot", 1124 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1125 Requires<[IsThumb2]> { 1126 let Inst{31-27} = 0b11111; 1127 let Inst{26-23} = 0b0100; 1128 let Inst{22-20} = opcod; 1129 let Inst{19-16} = 0b1111; // Rn 1130 let Inst{15-12} = 0b1111; 1131 let Inst{7} = 1; 1132 1133 bits<2> rot; 1134 let Inst{5-4} = rot{1-0}; // rotate 1135} 1136 1137// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 1138class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> 1139 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), 1140 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1141 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1142 Requires<[HasT2ExtractPack, IsThumb2]> { 1143 bits<2> rot; 1144 let Inst{31-27} = 0b11111; 1145 let Inst{26-23} = 0b0100; 1146 let Inst{22-20} = opcod; 1147 let Inst{19-16} = 0b1111; // Rn 1148 let Inst{15-12} = 0b1111; 1149 let Inst{7} = 1; 1150 let Inst{5-4} = rot; 1151} 1152 1153// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 1154// supported yet. 1155class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> 1156 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1157 opc, "\t$Rd, $Rm$rot", []>, 1158 Requires<[IsThumb2, HasT2ExtractPack]> { 1159 bits<2> rot; 1160 let Inst{31-27} = 0b11111; 1161 let Inst{26-23} = 0b0100; 1162 let Inst{22-20} = opcod; 1163 let Inst{19-16} = 0b1111; // Rn 1164 let Inst{15-12} = 0b1111; 1165 let Inst{7} = 1; 1166 let Inst{5-4} = rot; 1167} 1168 1169/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1170/// register and one whose operand is a register rotated by 8/16/24. 1171class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> 1172 : T2ThreeReg<(outs rGPR:$Rd), 1173 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1174 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", 1175 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, 1176 Requires<[HasT2ExtractPack, IsThumb2]> { 1177 bits<2> rot; 1178 let Inst{31-27} = 0b11111; 1179 let Inst{26-23} = 0b0100; 1180 let Inst{22-20} = opcod; 1181 let Inst{15-12} = 0b1111; 1182 let Inst{7} = 1; 1183 let Inst{5-4} = rot; 1184} 1185 1186class T2I_exta_rrot_np<bits<3> opcod, string opc> 1187 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), 1188 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { 1189 bits<2> rot; 1190 let Inst{31-27} = 0b11111; 1191 let Inst{26-23} = 0b0100; 1192 let Inst{22-20} = opcod; 1193 let Inst{15-12} = 0b1111; 1194 let Inst{7} = 1; 1195 let Inst{5-4} = rot; 1196} 1197 1198//===----------------------------------------------------------------------===// 1199// Instructions 1200//===----------------------------------------------------------------------===// 1201 1202//===----------------------------------------------------------------------===// 1203// Miscellaneous Instructions. 1204// 1205 1206class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1207 string asm, list<dag> pattern> 1208 : T2XI<oops, iops, itin, asm, pattern> { 1209 bits<4> Rd; 1210 bits<12> label; 1211 1212 let Inst{11-8} = Rd; 1213 let Inst{26} = label{11}; 1214 let Inst{14-12} = label{10-8}; 1215 let Inst{7-0} = label{7-0}; 1216} 1217 1218// LEApcrel - Load a pc-relative address into a register without offending the 1219// assembler. 1220def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1221 (ins t2adrlabel:$addr, pred:$p), 1222 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>, 1223 Sched<[WriteALU, ReadALU]> { 1224 let Inst{31-27} = 0b11110; 1225 let Inst{25-24} = 0b10; 1226 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1227 let Inst{22} = 0; 1228 let Inst{20} = 0; 1229 let Inst{19-16} = 0b1111; // Rn 1230 let Inst{15} = 0; 1231 1232 bits<4> Rd; 1233 bits<13> addr; 1234 let Inst{11-8} = Rd; 1235 let Inst{23} = addr{12}; 1236 let Inst{21} = addr{12}; 1237 let Inst{26} = addr{11}; 1238 let Inst{14-12} = addr{10-8}; 1239 let Inst{7-0} = addr{7-0}; 1240 1241 let DecoderMethod = "DecodeT2Adr"; 1242} 1243 1244let hasSideEffects = 0, isReMaterializable = 1 in 1245def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1246 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1247let hasSideEffects = 1 in 1248def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1249 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1250 4, IIC_iALUi, 1251 []>, Sched<[WriteALU, ReadALU]>; 1252 1253 1254//===----------------------------------------------------------------------===// 1255// Load / store Instructions. 1256// 1257 1258// Load 1259let canFoldAsLoad = 1, isReMaterializable = 1 in 1260defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, 1261 UnOpFrag<(load node:$Src)>>; 1262 1263// Loads with zero extension 1264defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1265 GPRnopc, UnOpFrag<(zextloadi16 node:$Src)>>; 1266defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1267 GPRnopc, UnOpFrag<(zextloadi8 node:$Src)>>; 1268 1269// Loads with sign extension 1270defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1271 GPRnopc, UnOpFrag<(sextloadi16 node:$Src)>>; 1272defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1273 GPRnopc, UnOpFrag<(sextloadi8 node:$Src)>>; 1274 1275let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 1276// Load doubleword 1277def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1278 (ins t2addrmode_imm8s4:$addr), 1279 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>; 1280} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 1281 1282// zextload i1 -> zextload i8 1283def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1284 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1285def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1286 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1287def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1288 (t2LDRBs t2addrmode_so_reg:$addr)>; 1289def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1290 (t2LDRBpci tconstpool:$addr)>; 1291 1292// extload -> zextload 1293// FIXME: Reduce the number of patterns by legalizing extload to zextload 1294// earlier? 1295def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1296 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1297def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1298 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1299def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1300 (t2LDRBs t2addrmode_so_reg:$addr)>; 1301def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1302 (t2LDRBpci tconstpool:$addr)>; 1303 1304def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1305 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1306def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1307 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1308def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1309 (t2LDRBs t2addrmode_so_reg:$addr)>; 1310def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1311 (t2LDRBpci tconstpool:$addr)>; 1312 1313def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1314 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1315def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1316 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1317def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1318 (t2LDRHs t2addrmode_so_reg:$addr)>; 1319def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1320 (t2LDRHpci tconstpool:$addr)>; 1321 1322// FIXME: The destination register of the loads and stores can't be PC, but 1323// can be SP. We need another regclass (similar to rGPR) to represent 1324// that. Not a pressing issue since these are selected manually, 1325// not via pattern. 1326 1327// Indexed loads 1328 1329let mayLoad = 1, hasSideEffects = 0 in { 1330def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1331 (ins t2addrmode_imm8_pre:$addr), 1332 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1333 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; 1334 1335def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1336 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1337 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1338 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1339 1340def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1341 (ins t2addrmode_imm8_pre:$addr), 1342 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1343 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; 1344 1345def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1346 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1348 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1349 1350def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1351 (ins t2addrmode_imm8_pre:$addr), 1352 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1353 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; 1354 1355def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1356 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1357 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1358 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1359 1360def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1361 (ins t2addrmode_imm8_pre:$addr), 1362 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1363 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1364 []>; 1365 1366def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1367 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1368 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1369 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1370 1371def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1372 (ins t2addrmode_imm8_pre:$addr), 1373 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1374 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1375 []>; 1376 1377def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1378 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1379 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1380 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1381} // mayLoad = 1, hasSideEffects = 0 1382 1383// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). 1384// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1385class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1386 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc, 1387 "\t$Rt, $addr", []> { 1388 bits<4> Rt; 1389 bits<13> addr; 1390 let Inst{31-27} = 0b11111; 1391 let Inst{26-25} = 0b00; 1392 let Inst{24} = signed; 1393 let Inst{23} = 0; 1394 let Inst{22-21} = type; 1395 let Inst{20} = 1; // load 1396 let Inst{19-16} = addr{12-9}; 1397 let Inst{15-12} = Rt; 1398 let Inst{11} = 1; 1399 let Inst{10-8} = 0b110; // PUW. 1400 let Inst{7-0} = addr{7-0}; 1401 1402 let DecoderMethod = "DecodeT2LoadT"; 1403} 1404 1405def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1406def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1407def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1408def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1409def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1410 1411class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, 1412 string opc, string asm, list<dag> pattern> 1413 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, 1414 opc, asm, "", pattern>, Requires<[IsThumb, HasV8]> { 1415 bits<4> Rt; 1416 bits<4> addr; 1417 1418 let Inst{31-27} = 0b11101; 1419 let Inst{26-24} = 0b000; 1420 let Inst{23-20} = bits23_20; 1421 let Inst{11-6} = 0b111110; 1422 let Inst{5-4} = bit54; 1423 let Inst{3-0} = 0b1111; 1424 1425 // Encode instruction operands 1426 let Inst{19-16} = addr; 1427 let Inst{15-12} = Rt; 1428} 1429 1430def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), 1431 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>; 1432def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), 1433 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>; 1434def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), 1435 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>; 1436 1437// Store 1438defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, 1439 BinOpFrag<(store node:$LHS, node:$RHS)>>; 1440defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1441 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1442defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1443 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1444 1445// Store doubleword 1446let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in 1447def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1448 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), 1449 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>; 1450 1451// Indexed stores 1452 1453let mayStore = 1, hasSideEffects = 0 in { 1454def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), 1455 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr), 1456 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1457 "str", "\t$Rt, $addr!", 1458 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>; 1459 1460def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), 1461 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1462 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1463 "strh", "\t$Rt, $addr!", 1464 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>; 1465 1466def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), 1467 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1468 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1469 "strb", "\t$Rt, $addr!", 1470 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>; 1471} // mayStore = 1, hasSideEffects = 0 1472 1473def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), 1474 (ins GPRnopc:$Rt, addr_offset_none:$Rn, 1475 t2am_imm8_offset:$offset), 1476 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1477 "str", "\t$Rt, $Rn$offset", 1478 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1479 [(set GPRnopc:$Rn_wb, 1480 (post_store GPRnopc:$Rt, addr_offset_none:$Rn, 1481 t2am_imm8_offset:$offset))]>; 1482 1483def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), 1484 (ins rGPR:$Rt, addr_offset_none:$Rn, 1485 t2am_imm8_offset:$offset), 1486 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1487 "strh", "\t$Rt, $Rn$offset", 1488 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1489 [(set GPRnopc:$Rn_wb, 1490 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, 1491 t2am_imm8_offset:$offset))]>; 1492 1493def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), 1494 (ins rGPR:$Rt, addr_offset_none:$Rn, 1495 t2am_imm8_offset:$offset), 1496 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1497 "strb", "\t$Rt, $Rn$offset", 1498 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1499 [(set GPRnopc:$Rn_wb, 1500 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, 1501 t2am_imm8_offset:$offset))]>; 1502 1503// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 1504// put the patterns on the instruction definitions directly as ISel wants 1505// the address base and offset to be separate operands, not a single 1506// complex operand like we represent the instructions themselves. The 1507// pseudos map between the two. 1508let usesCustomInserter = 1, 1509 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 1510def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1511 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1512 4, IIC_iStore_ru, 1513 [(set GPRnopc:$Rn_wb, 1514 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1515def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1516 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1517 4, IIC_iStore_ru, 1518 [(set GPRnopc:$Rn_wb, 1519 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1520def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1521 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1522 4, IIC_iStore_ru, 1523 [(set GPRnopc:$Rn_wb, 1524 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1525} 1526 1527// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1528// only. 1529// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1530class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1531 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1532 "\t$Rt, $addr", []> { 1533 let Inst{31-27} = 0b11111; 1534 let Inst{26-25} = 0b00; 1535 let Inst{24} = 0; // not signed 1536 let Inst{23} = 0; 1537 let Inst{22-21} = type; 1538 let Inst{20} = 0; // store 1539 let Inst{11} = 1; 1540 let Inst{10-8} = 0b110; // PUW 1541 1542 bits<4> Rt; 1543 bits<13> addr; 1544 let Inst{15-12} = Rt; 1545 let Inst{19-16} = addr{12-9}; 1546 let Inst{7-0} = addr{7-0}; 1547} 1548 1549def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1550def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1551def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1552 1553// ldrd / strd pre / post variants 1554// For disassembly only. 1555 1556def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1557 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru, 1558 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> { 1559 let DecoderMethod = "DecodeT2LDRDPreInstruction"; 1560} 1561 1562def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1563 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), 1564 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", 1565 "$addr.base = $wb", []>; 1566 1567def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), 1568 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr), 1569 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", 1570 "$addr.base = $wb", []> { 1571 let DecoderMethod = "DecodeT2STRDPreInstruction"; 1572} 1573 1574def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), 1575 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, 1576 t2am_imm8s4_offset:$imm), 1577 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", 1578 "$addr.base = $wb", []>; 1579 1580class T2Istrrel<bits<2> bit54, dag oops, dag iops, 1581 string opc, string asm, list<dag> pattern> 1582 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, 1583 asm, "", pattern>, Requires<[IsThumb, HasV8]> { 1584 bits<4> Rt; 1585 bits<4> addr; 1586 1587 let Inst{31-27} = 0b11101; 1588 let Inst{26-20} = 0b0001100; 1589 let Inst{11-6} = 0b111110; 1590 let Inst{5-4} = bit54; 1591 let Inst{3-0} = 0b1111; 1592 1593 // Encode instruction operands 1594 let Inst{19-16} = addr; 1595 let Inst{15-12} = Rt; 1596} 1597 1598def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1599 "stl", "\t$Rt, $addr", []>; 1600def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1601 "stlb", "\t$Rt, $addr", []>; 1602def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1603 "stlh", "\t$Rt, $addr", []>; 1604 1605// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1606// data/instruction access. 1607// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1608// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1609multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1610 1611 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1612 "\t$addr", 1613 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>, 1614 Sched<[WritePreLd]> { 1615 let Inst{31-25} = 0b1111100; 1616 let Inst{24} = instr; 1617 let Inst{23} = 1; 1618 let Inst{22} = 0; 1619 let Inst{21} = write; 1620 let Inst{20} = 1; 1621 let Inst{15-12} = 0b1111; 1622 1623 bits<17> addr; 1624 let Inst{19-16} = addr{16-13}; // Rn 1625 let Inst{11-0} = addr{11-0}; // imm12 1626 1627 let DecoderMethod = "DecodeT2LoadImm12"; 1628 } 1629 1630 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1631 "\t$addr", 1632 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>, 1633 Sched<[WritePreLd]> { 1634 let Inst{31-25} = 0b1111100; 1635 let Inst{24} = instr; 1636 let Inst{23} = 0; // U = 0 1637 let Inst{22} = 0; 1638 let Inst{21} = write; 1639 let Inst{20} = 1; 1640 let Inst{15-12} = 0b1111; 1641 let Inst{11-8} = 0b1100; 1642 1643 bits<13> addr; 1644 let Inst{19-16} = addr{12-9}; // Rn 1645 let Inst{7-0} = addr{7-0}; // imm8 1646 1647 let DecoderMethod = "DecodeT2LoadImm8"; 1648 } 1649 1650 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1651 "\t$addr", 1652 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>, 1653 Sched<[WritePreLd]> { 1654 let Inst{31-25} = 0b1111100; 1655 let Inst{24} = instr; 1656 let Inst{23} = 0; // add = TRUE for T1 1657 let Inst{22} = 0; 1658 let Inst{21} = write; 1659 let Inst{20} = 1; 1660 let Inst{15-12} = 0b1111; 1661 let Inst{11-6} = 0b000000; 1662 1663 bits<10> addr; 1664 let Inst{19-16} = addr{9-6}; // Rn 1665 let Inst{3-0} = addr{5-2}; // Rm 1666 let Inst{5-4} = addr{1-0}; // imm2 1667 1668 let DecoderMethod = "DecodeT2LoadShift"; 1669 } 1670} 1671 1672defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1673defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1674defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1675 1676// pci variant is very similar to i12, but supports negative offsets 1677// from the PC. Only PLD and PLI have pci variants (not PLDW) 1678class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr), 1679 IIC_Preload, opc, "\t$addr", 1680 [(ARMPreload (ARMWrapper tconstpool:$addr), 1681 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> { 1682 let Inst{31-25} = 0b1111100; 1683 let Inst{24} = inst; 1684 let Inst{22-20} = 0b001; 1685 let Inst{19-16} = 0b1111; 1686 let Inst{15-12} = 0b1111; 1687 1688 bits<13> addr; 1689 let Inst{23} = addr{12}; // add = (U == '1') 1690 let Inst{11-0} = addr{11-0}; // imm12 1691 1692 let DecoderMethod = "DecodeT2LoadLabel"; 1693} 1694 1695def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>; 1696def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>; 1697 1698//===----------------------------------------------------------------------===// 1699// Load / store multiple Instructions. 1700// 1701 1702multiclass thumb2_ld_mult<string asm, InstrItinClass itin, 1703 InstrItinClass itin_upd, bit L_bit> { 1704 def IA : 1705 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1706 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1707 bits<4> Rn; 1708 bits<16> regs; 1709 1710 let Inst{31-27} = 0b11101; 1711 let Inst{26-25} = 0b00; 1712 let Inst{24-23} = 0b01; // Increment After 1713 let Inst{22} = 0; 1714 let Inst{21} = 0; // No writeback 1715 let Inst{20} = L_bit; 1716 let Inst{19-16} = Rn; 1717 let Inst{15-0} = regs; 1718 } 1719 def IA_UPD : 1720 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1721 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1722 bits<4> Rn; 1723 bits<16> regs; 1724 1725 let Inst{31-27} = 0b11101; 1726 let Inst{26-25} = 0b00; 1727 let Inst{24-23} = 0b01; // Increment After 1728 let Inst{22} = 0; 1729 let Inst{21} = 1; // Writeback 1730 let Inst{20} = L_bit; 1731 let Inst{19-16} = Rn; 1732 let Inst{15-0} = regs; 1733 } 1734 def DB : 1735 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1736 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1737 bits<4> Rn; 1738 bits<16> regs; 1739 1740 let Inst{31-27} = 0b11101; 1741 let Inst{26-25} = 0b00; 1742 let Inst{24-23} = 0b10; // Decrement Before 1743 let Inst{22} = 0; 1744 let Inst{21} = 0; // No writeback 1745 let Inst{20} = L_bit; 1746 let Inst{19-16} = Rn; 1747 let Inst{15-0} = regs; 1748 } 1749 def DB_UPD : 1750 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1751 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1752 bits<4> Rn; 1753 bits<16> regs; 1754 1755 let Inst{31-27} = 0b11101; 1756 let Inst{26-25} = 0b00; 1757 let Inst{24-23} = 0b10; // Decrement Before 1758 let Inst{22} = 0; 1759 let Inst{21} = 1; // Writeback 1760 let Inst{20} = L_bit; 1761 let Inst{19-16} = Rn; 1762 let Inst{15-0} = regs; 1763 } 1764} 1765 1766let hasSideEffects = 0 in { 1767 1768let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 1769defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 1770 1771multiclass thumb2_st_mult<string asm, InstrItinClass itin, 1772 InstrItinClass itin_upd, bit L_bit> { 1773 def IA : 1774 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1775 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1776 bits<4> Rn; 1777 bits<16> regs; 1778 1779 let Inst{31-27} = 0b11101; 1780 let Inst{26-25} = 0b00; 1781 let Inst{24-23} = 0b01; // Increment After 1782 let Inst{22} = 0; 1783 let Inst{21} = 0; // No writeback 1784 let Inst{20} = L_bit; 1785 let Inst{19-16} = Rn; 1786 let Inst{15} = 0; 1787 let Inst{14} = regs{14}; 1788 let Inst{13} = 0; 1789 let Inst{12-0} = regs{12-0}; 1790 } 1791 def IA_UPD : 1792 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1793 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1794 bits<4> Rn; 1795 bits<16> regs; 1796 1797 let Inst{31-27} = 0b11101; 1798 let Inst{26-25} = 0b00; 1799 let Inst{24-23} = 0b01; // Increment After 1800 let Inst{22} = 0; 1801 let Inst{21} = 1; // Writeback 1802 let Inst{20} = L_bit; 1803 let Inst{19-16} = Rn; 1804 let Inst{15} = 0; 1805 let Inst{14} = regs{14}; 1806 let Inst{13} = 0; 1807 let Inst{12-0} = regs{12-0}; 1808 } 1809 def DB : 1810 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1811 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1812 bits<4> Rn; 1813 bits<16> regs; 1814 1815 let Inst{31-27} = 0b11101; 1816 let Inst{26-25} = 0b00; 1817 let Inst{24-23} = 0b10; // Decrement Before 1818 let Inst{22} = 0; 1819 let Inst{21} = 0; // No writeback 1820 let Inst{20} = L_bit; 1821 let Inst{19-16} = Rn; 1822 let Inst{15} = 0; 1823 let Inst{14} = regs{14}; 1824 let Inst{13} = 0; 1825 let Inst{12-0} = regs{12-0}; 1826 } 1827 def DB_UPD : 1828 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1829 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1830 bits<4> Rn; 1831 bits<16> regs; 1832 1833 let Inst{31-27} = 0b11101; 1834 let Inst{26-25} = 0b00; 1835 let Inst{24-23} = 0b10; // Decrement Before 1836 let Inst{22} = 0; 1837 let Inst{21} = 1; // Writeback 1838 let Inst{20} = L_bit; 1839 let Inst{19-16} = Rn; 1840 let Inst{15} = 0; 1841 let Inst{14} = regs{14}; 1842 let Inst{13} = 0; 1843 let Inst{12-0} = regs{12-0}; 1844 } 1845} 1846 1847 1848let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1849defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 1850 1851} // hasSideEffects 1852 1853 1854//===----------------------------------------------------------------------===// 1855// Move Instructions. 1856// 1857 1858let hasSideEffects = 0 in 1859def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1860 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> { 1861 let Inst{31-27} = 0b11101; 1862 let Inst{26-25} = 0b01; 1863 let Inst{24-21} = 0b0010; 1864 let Inst{19-16} = 0b1111; // Rn 1865 let Inst{14-12} = 0b000; 1866 let Inst{7-4} = 0b0000; 1867} 1868def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1869 pred:$p, zero_reg)>; 1870def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1871 pred:$p, CPSR)>; 1872def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1873 pred:$p, CPSR)>; 1874 1875// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1876let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 1877 AddedComplexity = 1 in 1878def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 1879 "mov", ".w\t$Rd, $imm", 1880 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> { 1881 let Inst{31-27} = 0b11110; 1882 let Inst{25} = 0; 1883 let Inst{24-21} = 0b0010; 1884 let Inst{19-16} = 0b1111; // Rn 1885 let Inst{15} = 0; 1886} 1887 1888// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'. 1889// Use aliases to get that to play nice here. 1890def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1891 pred:$p, CPSR)>; 1892def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1893 pred:$p, CPSR)>; 1894 1895def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1896 pred:$p, zero_reg)>; 1897def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1898 pred:$p, zero_reg)>; 1899 1900let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 1901def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 1902 "movw", "\t$Rd, $imm", 1903 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> { 1904 let Inst{31-27} = 0b11110; 1905 let Inst{25} = 1; 1906 let Inst{24-21} = 0b0010; 1907 let Inst{20} = 0; // The S bit. 1908 let Inst{15} = 0; 1909 1910 bits<4> Rd; 1911 bits<16> imm; 1912 1913 let Inst{11-8} = Rd; 1914 let Inst{19-16} = imm{15-12}; 1915 let Inst{26} = imm{11}; 1916 let Inst{14-12} = imm{10-8}; 1917 let Inst{7-0} = imm{7-0}; 1918 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1919} 1920 1921def : t2InstAlias<"mov${p} $Rd, $imm", 1922 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>; 1923 1924def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1925 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1926 1927let Constraints = "$src = $Rd" in { 1928def t2MOVTi16 : T2I<(outs rGPR:$Rd), 1929 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 1930 "movt", "\t$Rd, $imm", 1931 [(set rGPR:$Rd, 1932 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>, 1933 Sched<[WriteALU]> { 1934 let Inst{31-27} = 0b11110; 1935 let Inst{25} = 1; 1936 let Inst{24-21} = 0b0110; 1937 let Inst{20} = 0; // The S bit. 1938 let Inst{15} = 0; 1939 1940 bits<4> Rd; 1941 bits<16> imm; 1942 1943 let Inst{11-8} = Rd; 1944 let Inst{19-16} = imm{15-12}; 1945 let Inst{26} = imm{11}; 1946 let Inst{14-12} = imm{10-8}; 1947 let Inst{7-0} = imm{7-0}; 1948 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1949} 1950 1951def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1952 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 1953 Sched<[WriteALU]>; 1954} // Constraints 1955 1956def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1957 1958//===----------------------------------------------------------------------===// 1959// Extend Instructions. 1960// 1961 1962// Sign extenders 1963 1964def t2SXTB : T2I_ext_rrot<0b100, "sxtb", 1965 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1966def t2SXTH : T2I_ext_rrot<0b000, "sxth", 1967 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1968def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1969 1970def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", 1971 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1972def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", 1973 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1974def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 1975 1976// A simple right-shift can also be used in most cases (the exception is the 1977// SXTH operations with a rotate of 24: there the non-contiguous bits are 1978// relevant). 1979def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 1980 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>, 1981 Requires<[HasT2ExtractPack, IsThumb2]>; 1982def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)), 1983 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>, 1984 Requires<[HasT2ExtractPack, IsThumb2]>; 1985 1986// Zero extenders 1987 1988let AddedComplexity = 16 in { 1989def t2UXTB : T2I_ext_rrot<0b101, "uxtb", 1990 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1991def t2UXTH : T2I_ext_rrot<0b001, "uxth", 1992 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1993def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", 1994 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1995 1996// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1997// The transformation should probably be done as a combiner action 1998// instead so we can include a check for masking back in the upper 1999// eight bits of the source into the lower eight bits of the result. 2000//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 2001// (t2UXTB16 rGPR:$Src, 3)>, 2002// Requires<[HasT2ExtractPack, IsThumb2]>; 2003def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 2004 (t2UXTB16 rGPR:$Src, 1)>, 2005 Requires<[HasT2ExtractPack, IsThumb2]>; 2006 2007def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", 2008 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 2009def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", 2010 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 2011def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; 2012 2013def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 2014 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>, 2015 Requires<[HasT2ExtractPack, IsThumb2]>; 2016def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 2017 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>, 2018 Requires<[HasT2ExtractPack, IsThumb2]>; 2019} 2020 2021 2022//===----------------------------------------------------------------------===// 2023// Arithmetic Instructions. 2024// 2025 2026defm t2ADD : T2I_bin_ii12rs<0b000, "add", 2027 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 2028defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 2029 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 2030 2031// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 2032// 2033// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the 2034// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by 2035// AdjustInstrPostInstrSelection where we determine whether or not to 2036// set the "s" bit based on CPSR liveness. 2037// 2038// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen 2039// support for an optional CPSR definition that corresponds to the DAG 2040// node's second value. We can then eliminate the implicit def of CPSR. 2041defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, 2042 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 2043defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, 2044 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 2045 2046let hasPostISelHook = 1 in { 2047defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 2048 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 2049defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 2050 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 2051} 2052 2053// RSB 2054defm t2RSB : T2I_rbin_irs <0b1110, "rsb", 2055 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 2056 2057// FIXME: Eliminate them if we can write def : Pat patterns which defines 2058// CPSR and the implicit def of CPSR is not needed. 2059defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 2060 2061// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 2062// The assume-no-carry-in form uses the negation of the input since add/sub 2063// assume opposite meanings of the carry flag (i.e., carry == !borrow). 2064// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 2065// details. 2066// The AddedComplexity preferences the first variant over the others since 2067// it can be shrunk to a 16-bit wide encoding, while the others cannot. 2068let AddedComplexity = 1 in 2069def : T2Pat<(add GPR:$src, imm1_255_neg:$imm), 2070 (t2SUBri GPR:$src, imm1_255_neg:$imm)>; 2071def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 2072 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 2073def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 2074 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 2075def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm), 2076 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2077 2078let AddedComplexity = 1 in 2079def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm), 2080 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>; 2081def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 2082 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 2083def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm), 2084 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2085// The with-carry-in form matches bitwise not instead of the negation. 2086// Effectively, the inverse interpretation of the carry flag already accounts 2087// for part of the negation. 2088let AddedComplexity = 1 in 2089def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 2090 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 2091def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 2092 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 2093def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR), 2094 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>; 2095 2096// Select Bytes -- for disassembly only 2097 2098def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2099 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>, 2100 Requires<[IsThumb2, HasThumb2DSP]> { 2101 let Inst{31-27} = 0b11111; 2102 let Inst{26-24} = 0b010; 2103 let Inst{23} = 0b1; 2104 let Inst{22-20} = 0b010; 2105 let Inst{15-12} = 0b1111; 2106 let Inst{7} = 0b1; 2107 let Inst{6-4} = 0b000; 2108} 2109 2110// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 2111// And Miscellaneous operations -- for disassembly only 2112class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 2113 list<dag> pat = [/* For disassembly only; pattern left blank */], 2114 dag iops = (ins rGPR:$Rn, rGPR:$Rm), 2115 string asm = "\t$Rd, $Rn, $Rm"> 2116 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 2117 Requires<[IsThumb2, HasThumb2DSP]> { 2118 let Inst{31-27} = 0b11111; 2119 let Inst{26-23} = 0b0101; 2120 let Inst{22-20} = op22_20; 2121 let Inst{15-12} = 0b1111; 2122 let Inst{7-4} = op7_4; 2123 2124 bits<4> Rd; 2125 bits<4> Rn; 2126 bits<4> Rm; 2127 2128 let Inst{11-8} = Rd; 2129 let Inst{19-16} = Rn; 2130 let Inst{3-0} = Rm; 2131} 2132 2133// Saturating add/subtract -- for disassembly only 2134 2135def t2QADD : T2I_pam<0b000, 0b1000, "qadd", 2136 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))], 2137 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2138def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 2139def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 2140def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 2141def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [], 2142 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2143def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [], 2144 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2145def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 2146def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", 2147 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))], 2148 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2149def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 2150def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 2151def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 2152def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 2153def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 2154def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 2155def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 2156def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 2157 2158// Signed/Unsigned add/subtract -- for disassembly only 2159 2160def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 2161def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 2162def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 2163def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 2164def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 2165def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 2166def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 2167def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 2168def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 2169def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 2170def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 2171def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 2172 2173// Signed/Unsigned halving add/subtract -- for disassembly only 2174 2175def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 2176def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 2177def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 2178def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 2179def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 2180def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 2181def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 2182def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 2183def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 2184def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 2185def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 2186def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 2187 2188// Helper class for disassembly only 2189// A6.3.16 & A6.3.17 2190// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 2191class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2192 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2193 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2194 let Inst{31-27} = 0b11111; 2195 let Inst{26-24} = 0b011; 2196 let Inst{23} = long; 2197 let Inst{22-20} = op22_20; 2198 let Inst{7-4} = op7_4; 2199} 2200 2201class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2202 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2203 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 2204 let Inst{31-27} = 0b11111; 2205 let Inst{26-24} = 0b011; 2206 let Inst{23} = long; 2207 let Inst{22-20} = op22_20; 2208 let Inst{7-4} = op7_4; 2209} 2210 2211// Unsigned Sum of Absolute Differences [and Accumulate]. 2212def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2213 (ins rGPR:$Rn, rGPR:$Rm), 2214 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>, 2215 Requires<[IsThumb2, HasThumb2DSP]> { 2216 let Inst{15-12} = 0b1111; 2217} 2218def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2219 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 2220 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>, 2221 Requires<[IsThumb2, HasThumb2DSP]>; 2222 2223// Signed/Unsigned saturate. 2224class T2SatI<dag oops, dag iops, InstrItinClass itin, 2225 string opc, string asm, list<dag> pattern> 2226 : T2I<oops, iops, itin, opc, asm, pattern> { 2227 bits<4> Rd; 2228 bits<4> Rn; 2229 bits<5> sat_imm; 2230 bits<7> sh; 2231 2232 let Inst{11-8} = Rd; 2233 let Inst{19-16} = Rn; 2234 let Inst{4-0} = sat_imm; 2235 let Inst{21} = sh{5}; 2236 let Inst{14-12} = sh{4-2}; 2237 let Inst{7-6} = sh{1-0}; 2238} 2239 2240def t2SSAT: T2SatI< 2241 (outs rGPR:$Rd), 2242 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2243 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2244 let Inst{31-27} = 0b11110; 2245 let Inst{25-22} = 0b1100; 2246 let Inst{20} = 0; 2247 let Inst{15} = 0; 2248 let Inst{5} = 0; 2249} 2250 2251def t2SSAT16: T2SatI< 2252 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary, 2253 "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 2254 Requires<[IsThumb2, HasThumb2DSP]> { 2255 let Inst{31-27} = 0b11110; 2256 let Inst{25-22} = 0b1100; 2257 let Inst{20} = 0; 2258 let Inst{15} = 0; 2259 let Inst{21} = 1; // sh = '1' 2260 let Inst{14-12} = 0b000; // imm3 = '000' 2261 let Inst{7-6} = 0b00; // imm2 = '00' 2262 let Inst{5-4} = 0b00; 2263} 2264 2265def t2USAT: T2SatI< 2266 (outs rGPR:$Rd), 2267 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2268 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2269 let Inst{31-27} = 0b11110; 2270 let Inst{25-22} = 0b1110; 2271 let Inst{20} = 0; 2272 let Inst{15} = 0; 2273} 2274 2275def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn), 2276 NoItinerary, 2277 "usat16", "\t$Rd, $sat_imm, $Rn", []>, 2278 Requires<[IsThumb2, HasThumb2DSP]> { 2279 let Inst{31-22} = 0b1111001110; 2280 let Inst{20} = 0; 2281 let Inst{15} = 0; 2282 let Inst{21} = 1; // sh = '1' 2283 let Inst{14-12} = 0b000; // imm3 = '000' 2284 let Inst{7-6} = 0b00; // imm2 = '00' 2285 let Inst{5-4} = 0b00; 2286} 2287 2288def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>; 2289def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>; 2290 2291//===----------------------------------------------------------------------===// 2292// Shift and rotate Instructions. 2293// 2294 2295defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, 2296 BinOpFrag<(shl node:$LHS, node:$RHS)>>; 2297defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, 2298 BinOpFrag<(srl node:$LHS, node:$RHS)>>; 2299defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, 2300 BinOpFrag<(sra node:$LHS, node:$RHS)>>; 2301defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, 2302 BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 2303 2304// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 2305def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 2306 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 2307 2308let Uses = [CPSR] in { 2309def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2310 "rrx", "\t$Rd, $Rm", 2311 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> { 2312 let Inst{31-27} = 0b11101; 2313 let Inst{26-25} = 0b01; 2314 let Inst{24-21} = 0b0010; 2315 let Inst{19-16} = 0b1111; // Rn 2316 let Inst{14-12} = 0b000; 2317 let Inst{7-4} = 0b0011; 2318} 2319} 2320 2321let isCodeGenOnly = 1, Defs = [CPSR] in { 2322def t2MOVsrl_flag : T2TwoRegShiftImm< 2323 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2324 "lsrs", ".w\t$Rd, $Rm, #1", 2325 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>, 2326 Sched<[WriteALU]> { 2327 let Inst{31-27} = 0b11101; 2328 let Inst{26-25} = 0b01; 2329 let Inst{24-21} = 0b0010; 2330 let Inst{20} = 1; // The S bit. 2331 let Inst{19-16} = 0b1111; // Rn 2332 let Inst{5-4} = 0b01; // Shift type. 2333 // Shift amount = Inst{14-12:7-6} = 1. 2334 let Inst{14-12} = 0b000; 2335 let Inst{7-6} = 0b01; 2336} 2337def t2MOVsra_flag : T2TwoRegShiftImm< 2338 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2339 "asrs", ".w\t$Rd, $Rm, #1", 2340 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>, 2341 Sched<[WriteALU]> { 2342 let Inst{31-27} = 0b11101; 2343 let Inst{26-25} = 0b01; 2344 let Inst{24-21} = 0b0010; 2345 let Inst{20} = 1; // The S bit. 2346 let Inst{19-16} = 0b1111; // Rn 2347 let Inst{5-4} = 0b10; // Shift type. 2348 // Shift amount = Inst{14-12:7-6} = 1. 2349 let Inst{14-12} = 0b000; 2350 let Inst{7-6} = 0b01; 2351} 2352} 2353 2354//===----------------------------------------------------------------------===// 2355// Bitwise Instructions. 2356// 2357 2358defm t2AND : T2I_bin_w_irs<0b0000, "and", 2359 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2360 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 2361defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2362 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2363 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 2364defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2365 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2366 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 2367 2368defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2369 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2370 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 2371 2372class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2373 string opc, string asm, list<dag> pattern> 2374 : T2I<oops, iops, itin, opc, asm, pattern> { 2375 bits<4> Rd; 2376 bits<5> msb; 2377 bits<5> lsb; 2378 2379 let Inst{11-8} = Rd; 2380 let Inst{4-0} = msb{4-0}; 2381 let Inst{14-12} = lsb{4-2}; 2382 let Inst{7-6} = lsb{1-0}; 2383} 2384 2385class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2386 string opc, string asm, list<dag> pattern> 2387 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2388 bits<4> Rn; 2389 2390 let Inst{19-16} = Rn; 2391} 2392 2393let Constraints = "$src = $Rd" in 2394def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2395 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2396 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 2397 let Inst{31-27} = 0b11110; 2398 let Inst{26} = 0; // should be 0. 2399 let Inst{25} = 1; 2400 let Inst{24-20} = 0b10110; 2401 let Inst{19-16} = 0b1111; // Rn 2402 let Inst{15} = 0; 2403 let Inst{5} = 0; // should be 0. 2404 2405 bits<10> imm; 2406 let msb{4-0} = imm{9-5}; 2407 let lsb{4-0} = imm{4-0}; 2408} 2409 2410def t2SBFX: T2TwoRegBitFI< 2411 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2412 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2413 let Inst{31-27} = 0b11110; 2414 let Inst{25} = 1; 2415 let Inst{24-20} = 0b10100; 2416 let Inst{15} = 0; 2417} 2418 2419def t2UBFX: T2TwoRegBitFI< 2420 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2421 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2422 let Inst{31-27} = 0b11110; 2423 let Inst{25} = 1; 2424 let Inst{24-20} = 0b11100; 2425 let Inst{15} = 0; 2426} 2427 2428// A8.8.247 UDF - Undefined (Encoding T2) 2429def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", 2430 [(int_arm_undefined imm0_65535:$imm16)]> { 2431 bits<16> imm16; 2432 let Inst{31-29} = 0b111; 2433 let Inst{28-27} = 0b10; 2434 let Inst{26-20} = 0b1111111; 2435 let Inst{19-16} = imm16{15-12}; 2436 let Inst{15} = 0b1; 2437 let Inst{14-12} = 0b010; 2438 let Inst{11-0} = imm16{11-0}; 2439} 2440 2441// A8.6.18 BFI - Bitfield insert (Encoding T1) 2442let Constraints = "$src = $Rd" in { 2443 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2444 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2445 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2446 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2447 bf_inv_mask_imm:$imm))]> { 2448 let Inst{31-27} = 0b11110; 2449 let Inst{26} = 0; // should be 0. 2450 let Inst{25} = 1; 2451 let Inst{24-20} = 0b10110; 2452 let Inst{15} = 0; 2453 let Inst{5} = 0; // should be 0. 2454 2455 bits<10> imm; 2456 let msb{4-0} = imm{9-5}; 2457 let lsb{4-0} = imm{4-0}; 2458 } 2459} 2460 2461defm t2ORN : T2I_bin_irs<0b0011, "orn", 2462 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2463 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; 2464 2465/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 2466/// unary operation that produces a value. These are predicable and can be 2467/// changed to modify CPSR. 2468multiclass T2I_un_irs<bits<4> opcod, string opc, 2469 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 2470 PatFrag opnode, 2471 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> { 2472 // shifted imm 2473 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 2474 opc, "\t$Rd, $imm", 2475 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> { 2476 let isAsCheapAsAMove = Cheap; 2477 let isReMaterializable = ReMat; 2478 let isMoveImm = MoveImm; 2479 let Inst{31-27} = 0b11110; 2480 let Inst{25} = 0; 2481 let Inst{24-21} = opcod; 2482 let Inst{19-16} = 0b1111; // Rn 2483 let Inst{15} = 0; 2484 } 2485 // register 2486 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 2487 opc, ".w\t$Rd, $Rm", 2488 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> { 2489 let Inst{31-27} = 0b11101; 2490 let Inst{26-25} = 0b01; 2491 let Inst{24-21} = opcod; 2492 let Inst{19-16} = 0b1111; // Rn 2493 let Inst{14-12} = 0b000; // imm3 2494 let Inst{7-6} = 0b00; // imm2 2495 let Inst{5-4} = 0b00; // type 2496 } 2497 // shifted register 2498 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 2499 opc, ".w\t$Rd, $ShiftedRm", 2500 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>, 2501 Sched<[WriteALU]> { 2502 let Inst{31-27} = 0b11101; 2503 let Inst{26-25} = 0b01; 2504 let Inst{24-21} = opcod; 2505 let Inst{19-16} = 0b1111; // Rn 2506 } 2507} 2508 2509// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2510let AddedComplexity = 1 in 2511defm t2MVN : T2I_un_irs <0b0011, "mvn", 2512 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2513 UnOpFrag<(not node:$Src)>, 1, 1, 1>; 2514 2515let AddedComplexity = 1 in 2516def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2517 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2518 2519// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise 2520def top16Zero: PatLeaf<(i32 rGPR:$src), [{ 2521 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16)); 2522 }]>; 2523 2524// so_imm_notSext is needed instead of so_imm_not, as the value of imm 2525// will match the extended, not the original bitWidth for $src. 2526def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm), 2527 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>; 2528 2529 2530// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2531def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2532 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2533 Requires<[IsThumb2]>; 2534 2535def : T2Pat<(t2_so_imm_not:$src), 2536 (t2MVNi t2_so_imm_not:$src)>; 2537 2538//===----------------------------------------------------------------------===// 2539// Multiply Instructions. 2540// 2541let isCommutable = 1 in 2542def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2543 "mul", "\t$Rd, $Rn, $Rm", 2544 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { 2545 let Inst{31-27} = 0b11111; 2546 let Inst{26-23} = 0b0110; 2547 let Inst{22-20} = 0b000; 2548 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2549 let Inst{7-4} = 0b0000; // Multiply 2550} 2551 2552def t2MLA: T2FourReg< 2553 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2554 "mla", "\t$Rd, $Rn, $Rm, $Ra", 2555 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>, 2556 Requires<[IsThumb2, UseMulOps]> { 2557 let Inst{31-27} = 0b11111; 2558 let Inst{26-23} = 0b0110; 2559 let Inst{22-20} = 0b000; 2560 let Inst{7-4} = 0b0000; // Multiply 2561} 2562 2563def t2MLS: T2FourReg< 2564 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2565 "mls", "\t$Rd, $Rn, $Rm, $Ra", 2566 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>, 2567 Requires<[IsThumb2, UseMulOps]> { 2568 let Inst{31-27} = 0b11111; 2569 let Inst{26-23} = 0b0110; 2570 let Inst{22-20} = 0b000; 2571 let Inst{7-4} = 0b0001; // Multiply and Subtract 2572} 2573 2574// Extra precision multiplies with low / high results 2575let hasSideEffects = 0 in { 2576let isCommutable = 1 in { 2577def t2SMULL : T2MulLong<0b000, 0b0000, 2578 (outs rGPR:$RdLo, rGPR:$RdHi), 2579 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2580 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2581 2582def t2UMULL : T2MulLong<0b010, 0b0000, 2583 (outs rGPR:$RdLo, rGPR:$RdHi), 2584 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2585 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2586} // isCommutable 2587 2588// Multiply + accumulate 2589def t2SMLAL : T2MlaLong<0b100, 0b0000, 2590 (outs rGPR:$RdLo, rGPR:$RdHi), 2591 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2592 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2593 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2594 2595def t2UMLAL : T2MlaLong<0b110, 0b0000, 2596 (outs rGPR:$RdLo, rGPR:$RdHi), 2597 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2598 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2599 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2600 2601def t2UMAAL : T2MulLong<0b110, 0b0110, 2602 (outs rGPR:$RdLo, rGPR:$RdHi), 2603 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2604 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2605 Requires<[IsThumb2, HasThumb2DSP]>; 2606} // hasSideEffects 2607 2608// Rounding variants of the below included for disassembly only 2609 2610// Most significant word multiply 2611def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2612 "smmul", "\t$Rd, $Rn, $Rm", 2613 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, 2614 Requires<[IsThumb2, HasThumb2DSP]> { 2615 let Inst{31-27} = 0b11111; 2616 let Inst{26-23} = 0b0110; 2617 let Inst{22-20} = 0b101; 2618 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2619 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2620} 2621 2622def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2623 "smmulr", "\t$Rd, $Rn, $Rm", []>, 2624 Requires<[IsThumb2, HasThumb2DSP]> { 2625 let Inst{31-27} = 0b11111; 2626 let Inst{26-23} = 0b0110; 2627 let Inst{22-20} = 0b101; 2628 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2629 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2630} 2631 2632def t2SMMLA : T2FourReg< 2633 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2634 "smmla", "\t$Rd, $Rn, $Rm, $Ra", 2635 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>, 2636 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2637 let Inst{31-27} = 0b11111; 2638 let Inst{26-23} = 0b0110; 2639 let Inst{22-20} = 0b101; 2640 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2641} 2642 2643def t2SMMLAR: T2FourReg< 2644 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2645 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 2646 Requires<[IsThumb2, HasThumb2DSP]> { 2647 let Inst{31-27} = 0b11111; 2648 let Inst{26-23} = 0b0110; 2649 let Inst{22-20} = 0b101; 2650 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2651} 2652 2653def t2SMMLS: T2FourReg< 2654 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2655 "smmls", "\t$Rd, $Rn, $Rm, $Ra", 2656 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>, 2657 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2658 let Inst{31-27} = 0b11111; 2659 let Inst{26-23} = 0b0110; 2660 let Inst{22-20} = 0b110; 2661 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2662} 2663 2664def t2SMMLSR:T2FourReg< 2665 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2666 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 2667 Requires<[IsThumb2, HasThumb2DSP]> { 2668 let Inst{31-27} = 0b11111; 2669 let Inst{26-23} = 0b0110; 2670 let Inst{22-20} = 0b110; 2671 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2672} 2673 2674multiclass T2I_smul<string opc, PatFrag opnode> { 2675 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2676 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 2677 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2678 (sext_inreg rGPR:$Rm, i16)))]>, 2679 Requires<[IsThumb2, HasThumb2DSP]> { 2680 let Inst{31-27} = 0b11111; 2681 let Inst{26-23} = 0b0110; 2682 let Inst{22-20} = 0b001; 2683 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2684 let Inst{7-6} = 0b00; 2685 let Inst{5-4} = 0b00; 2686 } 2687 2688 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2689 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 2690 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2691 (sra rGPR:$Rm, (i32 16))))]>, 2692 Requires<[IsThumb2, HasThumb2DSP]> { 2693 let Inst{31-27} = 0b11111; 2694 let Inst{26-23} = 0b0110; 2695 let Inst{22-20} = 0b001; 2696 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2697 let Inst{7-6} = 0b00; 2698 let Inst{5-4} = 0b01; 2699 } 2700 2701 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2702 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 2703 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2704 (sext_inreg rGPR:$Rm, i16)))]>, 2705 Requires<[IsThumb2, HasThumb2DSP]> { 2706 let Inst{31-27} = 0b11111; 2707 let Inst{26-23} = 0b0110; 2708 let Inst{22-20} = 0b001; 2709 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2710 let Inst{7-6} = 0b00; 2711 let Inst{5-4} = 0b10; 2712 } 2713 2714 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2715 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 2716 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2717 (sra rGPR:$Rm, (i32 16))))]>, 2718 Requires<[IsThumb2, HasThumb2DSP]> { 2719 let Inst{31-27} = 0b11111; 2720 let Inst{26-23} = 0b0110; 2721 let Inst{22-20} = 0b001; 2722 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2723 let Inst{7-6} = 0b00; 2724 let Inst{5-4} = 0b11; 2725 } 2726 2727 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2728 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 2729 []>, 2730 Requires<[IsThumb2, HasThumb2DSP]> { 2731 let Inst{31-27} = 0b11111; 2732 let Inst{26-23} = 0b0110; 2733 let Inst{22-20} = 0b011; 2734 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2735 let Inst{7-6} = 0b00; 2736 let Inst{5-4} = 0b00; 2737 } 2738 2739 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2740 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 2741 []>, 2742 Requires<[IsThumb2, HasThumb2DSP]> { 2743 let Inst{31-27} = 0b11111; 2744 let Inst{26-23} = 0b0110; 2745 let Inst{22-20} = 0b011; 2746 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2747 let Inst{7-6} = 0b00; 2748 let Inst{5-4} = 0b01; 2749 } 2750} 2751 2752 2753multiclass T2I_smla<string opc, PatFrag opnode> { 2754 def BB : T2FourReg< 2755 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2756 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 2757 [(set rGPR:$Rd, (add rGPR:$Ra, 2758 (opnode (sext_inreg rGPR:$Rn, i16), 2759 (sext_inreg rGPR:$Rm, i16))))]>, 2760 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2761 let Inst{31-27} = 0b11111; 2762 let Inst{26-23} = 0b0110; 2763 let Inst{22-20} = 0b001; 2764 let Inst{7-6} = 0b00; 2765 let Inst{5-4} = 0b00; 2766 } 2767 2768 def BT : T2FourReg< 2769 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2770 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 2771 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16), 2772 (sra rGPR:$Rm, (i32 16)))))]>, 2773 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2774 let Inst{31-27} = 0b11111; 2775 let Inst{26-23} = 0b0110; 2776 let Inst{22-20} = 0b001; 2777 let Inst{7-6} = 0b00; 2778 let Inst{5-4} = 0b01; 2779 } 2780 2781 def TB : T2FourReg< 2782 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2783 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 2784 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2785 (sext_inreg rGPR:$Rm, i16))))]>, 2786 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2787 let Inst{31-27} = 0b11111; 2788 let Inst{26-23} = 0b0110; 2789 let Inst{22-20} = 0b001; 2790 let Inst{7-6} = 0b00; 2791 let Inst{5-4} = 0b10; 2792 } 2793 2794 def TT : T2FourReg< 2795 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2796 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 2797 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2798 (sra rGPR:$Rm, (i32 16)))))]>, 2799 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2800 let Inst{31-27} = 0b11111; 2801 let Inst{26-23} = 0b0110; 2802 let Inst{22-20} = 0b001; 2803 let Inst{7-6} = 0b00; 2804 let Inst{5-4} = 0b11; 2805 } 2806 2807 def WB : T2FourReg< 2808 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2809 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 2810 []>, 2811 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2812 let Inst{31-27} = 0b11111; 2813 let Inst{26-23} = 0b0110; 2814 let Inst{22-20} = 0b011; 2815 let Inst{7-6} = 0b00; 2816 let Inst{5-4} = 0b00; 2817 } 2818 2819 def WT : T2FourReg< 2820 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2821 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 2822 []>, 2823 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> { 2824 let Inst{31-27} = 0b11111; 2825 let Inst{26-23} = 0b0110; 2826 let Inst{22-20} = 0b011; 2827 let Inst{7-6} = 0b00; 2828 let Inst{5-4} = 0b01; 2829 } 2830} 2831 2832defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2833defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2834 2835// Halfword multiple accumulate long: SMLAL<x><y> 2836def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), 2837 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", 2838 [/* For disassembly only; pattern left blank */]>, 2839 Requires<[IsThumb2, HasThumb2DSP]>; 2840def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd), 2841 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm", 2842 [/* For disassembly only; pattern left blank */]>, 2843 Requires<[IsThumb2, HasThumb2DSP]>; 2844def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd), 2845 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm", 2846 [/* For disassembly only; pattern left blank */]>, 2847 Requires<[IsThumb2, HasThumb2DSP]>; 2848def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd), 2849 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm", 2850 [/* For disassembly only; pattern left blank */]>, 2851 Requires<[IsThumb2, HasThumb2DSP]>; 2852 2853// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2854def t2SMUAD: T2ThreeReg_mac< 2855 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2856 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>, 2857 Requires<[IsThumb2, HasThumb2DSP]> { 2858 let Inst{15-12} = 0b1111; 2859} 2860def t2SMUADX:T2ThreeReg_mac< 2861 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2862 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>, 2863 Requires<[IsThumb2, HasThumb2DSP]> { 2864 let Inst{15-12} = 0b1111; 2865} 2866def t2SMUSD: T2ThreeReg_mac< 2867 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2868 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>, 2869 Requires<[IsThumb2, HasThumb2DSP]> { 2870 let Inst{15-12} = 0b1111; 2871} 2872def t2SMUSDX:T2ThreeReg_mac< 2873 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2874 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>, 2875 Requires<[IsThumb2, HasThumb2DSP]> { 2876 let Inst{15-12} = 0b1111; 2877} 2878def t2SMLAD : T2FourReg_mac< 2879 0, 0b010, 0b0000, (outs rGPR:$Rd), 2880 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", 2881 "\t$Rd, $Rn, $Rm, $Ra", []>, 2882 Requires<[IsThumb2, HasThumb2DSP]>; 2883def t2SMLADX : T2FourReg_mac< 2884 0, 0b010, 0b0001, (outs rGPR:$Rd), 2885 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx", 2886 "\t$Rd, $Rn, $Rm, $Ra", []>, 2887 Requires<[IsThumb2, HasThumb2DSP]>; 2888def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), 2889 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", 2890 "\t$Rd, $Rn, $Rm, $Ra", []>, 2891 Requires<[IsThumb2, HasThumb2DSP]>; 2892def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd), 2893 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx", 2894 "\t$Rd, $Rn, $Rm, $Ra", []>, 2895 Requires<[IsThumb2, HasThumb2DSP]>; 2896def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2897 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald", 2898 "\t$Ra, $Rd, $Rn, $Rm", []>, 2899 Requires<[IsThumb2, HasThumb2DSP]>; 2900def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2901 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx", 2902 "\t$Ra, $Rd, $Rn, $Rm", []>, 2903 Requires<[IsThumb2, HasThumb2DSP]>; 2904def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2905 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld", 2906 "\t$Ra, $Rd, $Rn, $Rm", []>, 2907 Requires<[IsThumb2, HasThumb2DSP]>; 2908def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2909 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx", 2910 "\t$Ra, $Rd, $Rn, $Rm", []>, 2911 Requires<[IsThumb2, HasThumb2DSP]>; 2912 2913//===----------------------------------------------------------------------===// 2914// Division Instructions. 2915// Signed and unsigned division on v7-M 2916// 2917def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 2918 "sdiv", "\t$Rd, $Rn, $Rm", 2919 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 2920 Requires<[HasDivide, IsThumb2]> { 2921 let Inst{31-27} = 0b11111; 2922 let Inst{26-21} = 0b011100; 2923 let Inst{20} = 0b1; 2924 let Inst{15-12} = 0b1111; 2925 let Inst{7-4} = 0b1111; 2926} 2927 2928def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 2929 "udiv", "\t$Rd, $Rn, $Rm", 2930 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 2931 Requires<[HasDivide, IsThumb2]> { 2932 let Inst{31-27} = 0b11111; 2933 let Inst{26-21} = 0b011101; 2934 let Inst{20} = 0b1; 2935 let Inst{15-12} = 0b1111; 2936 let Inst{7-4} = 0b1111; 2937} 2938 2939//===----------------------------------------------------------------------===// 2940// Misc. Arithmetic Instructions. 2941// 2942 2943class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2944 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2945 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2946 let Inst{31-27} = 0b11111; 2947 let Inst{26-22} = 0b01010; 2948 let Inst{21-20} = op1; 2949 let Inst{15-12} = 0b1111; 2950 let Inst{7-6} = 0b10; 2951 let Inst{5-4} = op2; 2952 let Rn{3-0} = Rm; 2953} 2954 2955def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2956 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>, 2957 Sched<[WriteALU]>; 2958 2959def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2960 "rbit", "\t$Rd, $Rm", 2961 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>, 2962 Sched<[WriteALU]>; 2963 2964def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2965 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>, 2966 Sched<[WriteALU]>; 2967 2968def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2969 "rev16", ".w\t$Rd, $Rm", 2970 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>, 2971 Sched<[WriteALU]>; 2972 2973def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2974 "revsh", ".w\t$Rd, $Rm", 2975 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>, 2976 Sched<[WriteALU]>; 2977 2978def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 2979 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 2980 (t2REVSH rGPR:$Rm)>; 2981 2982def t2PKHBT : T2ThreeReg< 2983 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh), 2984 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 2985 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 2986 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 2987 0xFFFF0000)))]>, 2988 Requires<[HasT2ExtractPack, IsThumb2]>, 2989 Sched<[WriteALUsi, ReadALU]> { 2990 let Inst{31-27} = 0b11101; 2991 let Inst{26-25} = 0b01; 2992 let Inst{24-20} = 0b01100; 2993 let Inst{5} = 0; // BT form 2994 let Inst{4} = 0; 2995 2996 bits<5> sh; 2997 let Inst{14-12} = sh{4-2}; 2998 let Inst{7-6} = sh{1-0}; 2999} 3000 3001// Alternate cases for PKHBT where identities eliminate some nodes. 3002def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 3003 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 3004 Requires<[HasT2ExtractPack, IsThumb2]>; 3005def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 3006 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 3007 Requires<[HasT2ExtractPack, IsThumb2]>; 3008 3009// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 3010// will match the pattern below. 3011def t2PKHTB : T2ThreeReg< 3012 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh), 3013 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 3014 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 3015 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 3016 0xFFFF)))]>, 3017 Requires<[HasT2ExtractPack, IsThumb2]>, 3018 Sched<[WriteALUsi, ReadALU]> { 3019 let Inst{31-27} = 0b11101; 3020 let Inst{26-25} = 0b01; 3021 let Inst{24-20} = 0b01100; 3022 let Inst{5} = 1; // TB form 3023 let Inst{4} = 0; 3024 3025 bits<5> sh; 3026 let Inst{14-12} = sh{4-2}; 3027 let Inst{7-6} = sh{1-0}; 3028} 3029 3030// Alternate cases for PKHTB where identities eliminate some nodes. Note that 3031// a shift amount of 0 is *not legal* here, it is PKHBT instead. 3032// We also can not replace a srl (17..31) by an arithmetic shift we would use in 3033// pkhtb src1, src2, asr (17..31). 3034def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)), 3035 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>, 3036 Requires<[HasT2ExtractPack, IsThumb2]>; 3037def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)), 3038 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 3039 Requires<[HasT2ExtractPack, IsThumb2]>; 3040def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 3041 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 3042 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 3043 Requires<[HasT2ExtractPack, IsThumb2]>; 3044 3045//===----------------------------------------------------------------------===// 3046// CRC32 Instructions 3047// 3048// Polynomials: 3049// + CRC32{B,H,W} 0x04C11DB7 3050// + CRC32C{B,H,W} 0x1EDC6F41 3051// 3052 3053class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 3054 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, 3055 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"), 3056 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>, 3057 Requires<[IsThumb2, HasV8, HasCRC]> { 3058 let Inst{31-27} = 0b11111; 3059 let Inst{26-21} = 0b010110; 3060 let Inst{20} = C; 3061 let Inst{15-12} = 0b1111; 3062 let Inst{7-6} = 0b10; 3063 let Inst{5-4} = sz; 3064} 3065 3066def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>; 3067def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>; 3068def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>; 3069def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>; 3070def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>; 3071def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>; 3072 3073//===----------------------------------------------------------------------===// 3074// Comparison Instructions... 3075// 3076defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 3077 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 3078 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 3079 3080def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 3081 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 3082def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 3083 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 3084def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 3085 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 3086 3087let isCompare = 1, Defs = [CPSR] in { 3088 // shifted imm 3089 def t2CMNri : T2OneRegCmpImm< 3090 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi, 3091 "cmn", ".w\t$Rn, $imm", 3092 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>, 3093 Sched<[WriteCMP, ReadALU]> { 3094 let Inst{31-27} = 0b11110; 3095 let Inst{25} = 0; 3096 let Inst{24-21} = 0b1000; 3097 let Inst{20} = 1; // The S bit. 3098 let Inst{15} = 0; 3099 let Inst{11-8} = 0b1111; // Rd 3100 } 3101 // register 3102 def t2CMNzrr : T2TwoRegCmp< 3103 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr, 3104 "cmn", ".w\t$Rn, $Rm", 3105 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3106 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 3107 let Inst{31-27} = 0b11101; 3108 let Inst{26-25} = 0b01; 3109 let Inst{24-21} = 0b1000; 3110 let Inst{20} = 1; // The S bit. 3111 let Inst{14-12} = 0b000; // imm3 3112 let Inst{11-8} = 0b1111; // Rd 3113 let Inst{7-6} = 0b00; // imm2 3114 let Inst{5-4} = 0b00; // type 3115 } 3116 // shifted register 3117 def t2CMNzrs : T2OneRegCmpShiftedReg< 3118 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi, 3119 "cmn", ".w\t$Rn, $ShiftedRm", 3120 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3121 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>, 3122 Sched<[WriteCMPsi, ReadALU, ReadALU]> { 3123 let Inst{31-27} = 0b11101; 3124 let Inst{26-25} = 0b01; 3125 let Inst{24-21} = 0b1000; 3126 let Inst{20} = 1; // The S bit. 3127 let Inst{11-8} = 0b1111; // Rd 3128 } 3129} 3130 3131// Assembler aliases w/o the ".w" suffix. 3132// No alias here for 'rr' version as not all instantiations of this multiclass 3133// want one (CMP in particular, does not). 3134def : t2InstAlias<"cmn${p} $Rn, $imm", 3135 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>; 3136def : t2InstAlias<"cmn${p} $Rn, $shift", 3137 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>; 3138 3139def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 3140 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 3141 3142def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 3143 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>; 3144 3145defm t2TST : T2I_cmp_irs<0b0000, "tst", 3146 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3147 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>; 3148defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 3149 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3150 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>; 3151 3152// Conditional moves 3153let hasSideEffects = 0 in { 3154 3155let isCommutable = 1, isSelect = 1 in 3156def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 3157 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p), 3158 4, IIC_iCMOVr, 3159 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, 3160 cmovpred:$p))]>, 3161 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3162 3163let isMoveImm = 1 in 3164def t2MOVCCi 3165 : t2PseudoInst<(outs rGPR:$Rd), 3166 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3167 4, IIC_iCMOVi, 3168 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm, 3169 cmovpred:$p))]>, 3170 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3171 3172let isCodeGenOnly = 1 in { 3173let isMoveImm = 1 in 3174def t2MOVCCi16 3175 : t2PseudoInst<(outs rGPR:$Rd), 3176 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 3177 4, IIC_iCMOVi, 3178 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm, 3179 cmovpred:$p))]>, 3180 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3181 3182let isMoveImm = 1 in 3183def t2MVNCCi 3184 : t2PseudoInst<(outs rGPR:$Rd), 3185 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3186 4, IIC_iCMOVi, 3187 [(set rGPR:$Rd, 3188 (ARMcmov rGPR:$false, t2_so_imm_not:$imm, 3189 cmovpred:$p))]>, 3190 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3191 3192class MOVCCShPseudo<SDPatternOperator opnode, Operand ty> 3193 : t2PseudoInst<(outs rGPR:$Rd), 3194 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p), 3195 4, IIC_iCMOVsi, 3196 [(set rGPR:$Rd, (ARMcmov rGPR:$false, 3197 (opnode rGPR:$Rm, (i32 ty:$imm)), 3198 cmovpred:$p))]>, 3199 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3200 3201def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>; 3202def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>; 3203def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>; 3204def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>; 3205 3206let isMoveImm = 1 in 3207def t2MOVCCi32imm 3208 : t2PseudoInst<(outs rGPR:$dst), 3209 (ins rGPR:$false, i32imm:$src, cmovpred:$p), 3210 8, IIC_iCMOVix2, 3211 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src, 3212 cmovpred:$p))]>, 3213 RegConstraint<"$false = $dst">; 3214} // isCodeGenOnly = 1 3215 3216} // hasSideEffects 3217 3218//===----------------------------------------------------------------------===// 3219// Atomic operations intrinsics 3220// 3221 3222// memory barriers protect the atomic sequences 3223let hasSideEffects = 1 in { 3224def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3225 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 3226 Requires<[IsThumb, HasDB]> { 3227 bits<4> opt; 3228 let Inst{31-4} = 0xf3bf8f5; 3229 let Inst{3-0} = opt; 3230} 3231 3232def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3233 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 3234 Requires<[IsThumb, HasDB]> { 3235 bits<4> opt; 3236 let Inst{31-4} = 0xf3bf8f4; 3237 let Inst{3-0} = opt; 3238} 3239 3240def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary, 3241 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 3242 Requires<[IsThumb, HasDB]> { 3243 bits<4> opt; 3244 let Inst{31-4} = 0xf3bf8f6; 3245 let Inst{3-0} = opt; 3246} 3247} 3248 3249class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3250 InstrItinClass itin, string opc, string asm, string cstr, 3251 list<dag> pattern, bits<4> rt2 = 0b1111> 3252 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3253 let Inst{31-27} = 0b11101; 3254 let Inst{26-20} = 0b0001101; 3255 let Inst{11-8} = rt2; 3256 let Inst{7-4} = opcod; 3257 let Inst{3-0} = 0b1111; 3258 3259 bits<4> addr; 3260 bits<4> Rt; 3261 let Inst{19-16} = addr; 3262 let Inst{15-12} = Rt; 3263} 3264class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3265 InstrItinClass itin, string opc, string asm, string cstr, 3266 list<dag> pattern, bits<4> rt2 = 0b1111> 3267 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3268 let Inst{31-27} = 0b11101; 3269 let Inst{26-20} = 0b0001100; 3270 let Inst{11-8} = rt2; 3271 let Inst{7-4} = opcod; 3272 3273 bits<4> Rd; 3274 bits<4> addr; 3275 bits<4> Rt; 3276 let Inst{3-0} = Rd; 3277 let Inst{19-16} = addr; 3278 let Inst{15-12} = Rt; 3279} 3280 3281let mayLoad = 1 in { 3282def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3283 AddrModeNone, 4, NoItinerary, 3284 "ldrexb", "\t$Rt, $addr", "", 3285 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 3286def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3287 AddrModeNone, 4, NoItinerary, 3288 "ldrexh", "\t$Rt, $addr", "", 3289 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 3290def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), 3291 AddrModeNone, 4, NoItinerary, 3292 "ldrex", "\t$Rt, $addr", "", 3293 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> { 3294 bits<4> Rt; 3295 bits<12> addr; 3296 let Inst{31-27} = 0b11101; 3297 let Inst{26-20} = 0b0000101; 3298 let Inst{19-16} = addr{11-8}; 3299 let Inst{15-12} = Rt; 3300 let Inst{11-8} = 0b1111; 3301 let Inst{7-0} = addr{7-0}; 3302} 3303let hasExtraDefRegAllocReq = 1 in 3304def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2), 3305 (ins addr_offset_none:$addr), 3306 AddrModeNone, 4, NoItinerary, 3307 "ldrexd", "\t$Rt, $Rt2, $addr", "", 3308 [], {?, ?, ?, ?}>, 3309 Requires<[IsThumb2, IsNotMClass]> { 3310 bits<4> Rt2; 3311 let Inst{11-8} = Rt2; 3312} 3313def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3314 AddrModeNone, 4, NoItinerary, 3315 "ldaexb", "\t$Rt, $addr", "", 3316 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>, 3317 Requires<[IsThumb, HasV8]>; 3318def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3319 AddrModeNone, 4, NoItinerary, 3320 "ldaexh", "\t$Rt, $addr", "", 3321 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>, 3322 Requires<[IsThumb, HasV8]>; 3323def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr), 3324 AddrModeNone, 4, NoItinerary, 3325 "ldaex", "\t$Rt, $addr", "", 3326 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>, 3327 Requires<[IsThumb, HasV8]> { 3328 bits<4> Rt; 3329 bits<4> addr; 3330 let Inst{31-27} = 0b11101; 3331 let Inst{26-20} = 0b0001101; 3332 let Inst{19-16} = addr; 3333 let Inst{15-12} = Rt; 3334 let Inst{11-8} = 0b1111; 3335 let Inst{7-0} = 0b11101111; 3336} 3337let hasExtraDefRegAllocReq = 1 in 3338def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2), 3339 (ins addr_offset_none:$addr), 3340 AddrModeNone, 4, NoItinerary, 3341 "ldaexd", "\t$Rt, $Rt2, $addr", "", 3342 [], {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> { 3343 bits<4> Rt2; 3344 let Inst{11-8} = Rt2; 3345 3346 let Inst{7} = 1; 3347} 3348} 3349 3350let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 3351def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd), 3352 (ins rGPR:$Rt, addr_offset_none:$addr), 3353 AddrModeNone, 4, NoItinerary, 3354 "strexb", "\t$Rd, $Rt, $addr", "", 3355 [(set rGPR:$Rd, 3356 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>; 3357def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd), 3358 (ins rGPR:$Rt, addr_offset_none:$addr), 3359 AddrModeNone, 4, NoItinerary, 3360 "strexh", "\t$Rd, $Rt, $addr", "", 3361 [(set rGPR:$Rd, 3362 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>; 3363 3364def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3365 t2addrmode_imm0_1020s4:$addr), 3366 AddrModeNone, 4, NoItinerary, 3367 "strex", "\t$Rd, $Rt, $addr", "", 3368 [(set rGPR:$Rd, 3369 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]> { 3370 bits<4> Rd; 3371 bits<4> Rt; 3372 bits<12> addr; 3373 let Inst{31-27} = 0b11101; 3374 let Inst{26-20} = 0b0000100; 3375 let Inst{19-16} = addr{11-8}; 3376 let Inst{15-12} = Rt; 3377 let Inst{11-8} = Rd; 3378 let Inst{7-0} = addr{7-0}; 3379} 3380let hasExtraSrcRegAllocReq = 1 in 3381def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd), 3382 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3383 AddrModeNone, 4, NoItinerary, 3384 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3385 {?, ?, ?, ?}>, 3386 Requires<[IsThumb2, IsNotMClass]> { 3387 bits<4> Rt2; 3388 let Inst{11-8} = Rt2; 3389} 3390def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd), 3391 (ins rGPR:$Rt, addr_offset_none:$addr), 3392 AddrModeNone, 4, NoItinerary, 3393 "stlexb", "\t$Rd, $Rt, $addr", "", 3394 [(set rGPR:$Rd, 3395 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>, 3396 Requires<[IsThumb, HasV8]>; 3397 3398def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd), 3399 (ins rGPR:$Rt, addr_offset_none:$addr), 3400 AddrModeNone, 4, NoItinerary, 3401 "stlexh", "\t$Rd, $Rt, $addr", "", 3402 [(set rGPR:$Rd, 3403 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>, 3404 Requires<[IsThumb, HasV8]>; 3405 3406def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3407 addr_offset_none:$addr), 3408 AddrModeNone, 4, NoItinerary, 3409 "stlex", "\t$Rd, $Rt, $addr", "", 3410 [(set rGPR:$Rd, 3411 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>, 3412 Requires<[IsThumb, HasV8]> { 3413 bits<4> Rd; 3414 bits<4> Rt; 3415 bits<4> addr; 3416 let Inst{31-27} = 0b11101; 3417 let Inst{26-20} = 0b0001100; 3418 let Inst{19-16} = addr; 3419 let Inst{15-12} = Rt; 3420 let Inst{11-4} = 0b11111110; 3421 let Inst{3-0} = Rd; 3422} 3423let hasExtraSrcRegAllocReq = 1 in 3424def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd), 3425 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3426 AddrModeNone, 4, NoItinerary, 3427 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3428 {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> { 3429 bits<4> Rt2; 3430 let Inst{11-8} = Rt2; 3431} 3432} 3433 3434def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>, 3435 Requires<[IsThumb2, HasV7]> { 3436 let Inst{31-16} = 0xf3bf; 3437 let Inst{15-14} = 0b10; 3438 let Inst{13} = 0; 3439 let Inst{12} = 0; 3440 let Inst{11-8} = 0b1111; 3441 let Inst{7-4} = 0b0010; 3442 let Inst{3-0} = 0b1111; 3443} 3444 3445def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff), 3446 (t2LDREXB addr_offset_none:$addr)>; 3447def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), 3448 (t2LDREXH addr_offset_none:$addr)>; 3449def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3450 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>; 3451def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3452 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>; 3453 3454def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff), 3455 (t2LDAEXB addr_offset_none:$addr)>; 3456def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff), 3457 (t2LDAEXH addr_offset_none:$addr)>; 3458def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3459 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>; 3460def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3461 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>; 3462 3463//===----------------------------------------------------------------------===// 3464// SJLJ Exception handling intrinsics 3465// eh_sjlj_setjmp() is an instruction sequence to store the return 3466// address and save #0 in R0 for the non-longjmp case. 3467// Since by its nature we may be coming from some other function to get 3468// here, and we're using the stack frame for the containing function to 3469// save/restore registers, we can't keep anything live in regs across 3470// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3471// when we get here from a longjmp(). We force everything out of registers 3472// except for our own input by listing the relevant registers in Defs. By 3473// doing so, we also cause the prologue/epilogue code to actively preserve 3474// all of the callee-saved resgisters, which is exactly what we want. 3475// $val is a scratch register for our use. 3476let Defs = 3477 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 3478 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 3479 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3480 usesCustomInserter = 1 in { 3481 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3482 AddrModeNone, 0, NoItinerary, "", "", 3483 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3484 Requires<[IsThumb2, HasVFP2]>; 3485} 3486 3487let Defs = 3488 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 3489 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3490 usesCustomInserter = 1 in { 3491 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3492 AddrModeNone, 0, NoItinerary, "", "", 3493 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3494 Requires<[IsThumb2, NoVFP]>; 3495} 3496 3497 3498//===----------------------------------------------------------------------===// 3499// Control-Flow Instructions 3500// 3501 3502// FIXME: remove when we have a way to marking a MI with these properties. 3503// FIXME: Should pc be an implicit operand like PICADD, etc? 3504let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3505 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3506def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3507 reglist:$regs, variable_ops), 3508 4, IIC_iLoad_mBr, [], 3509 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3510 RegConstraint<"$Rn = $wb">; 3511 3512let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 3513let isPredicable = 1 in 3514def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br, 3515 "b", ".w\t$target", 3516 [(br bb:$target)]>, Sched<[WriteBr]> { 3517 let Inst{31-27} = 0b11110; 3518 let Inst{15-14} = 0b10; 3519 let Inst{12} = 1; 3520 3521 bits<24> target; 3522 let Inst{26} = target{23}; 3523 let Inst{13} = target{22}; 3524 let Inst{11} = target{21}; 3525 let Inst{25-16} = target{20-11}; 3526 let Inst{10-0} = target{10-0}; 3527 let DecoderMethod = "DecodeT2BInstruction"; 3528 let AsmMatchConverter = "cvtThumbBranches"; 3529} 3530 3531let isNotDuplicable = 1, isIndirectBranch = 1 in { 3532def t2BR_JT : t2PseudoInst<(outs), 3533 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id), 3534 0, IIC_Br, 3535 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>, 3536 Sched<[WriteBr]>; 3537 3538// FIXME: Add a non-pc based case that can be predicated. 3539def t2TBB_JT : t2PseudoInst<(outs), 3540 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>, 3541 Sched<[WriteBr]>; 3542 3543def t2TBH_JT : t2PseudoInst<(outs), 3544 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>, 3545 Sched<[WriteBr]>; 3546 3547def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br, 3548 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> { 3549 bits<4> Rn; 3550 bits<4> Rm; 3551 let Inst{31-20} = 0b111010001101; 3552 let Inst{19-16} = Rn; 3553 let Inst{15-5} = 0b11110000000; 3554 let Inst{4} = 0; // B form 3555 let Inst{3-0} = Rm; 3556 3557 let DecoderMethod = "DecodeThumbTableBranch"; 3558} 3559 3560def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br, 3561 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> { 3562 bits<4> Rn; 3563 bits<4> Rm; 3564 let Inst{31-20} = 0b111010001101; 3565 let Inst{19-16} = Rn; 3566 let Inst{15-5} = 0b11110000000; 3567 let Inst{4} = 1; // H form 3568 let Inst{3-0} = Rm; 3569 3570 let DecoderMethod = "DecodeThumbTableBranch"; 3571} 3572} // isNotDuplicable, isIndirectBranch 3573 3574} // isBranch, isTerminator, isBarrier 3575 3576// FIXME: should be able to write a pattern for ARMBrcond, but can't use 3577// a two-value operand where a dag node expects ", "two operands. :( 3578let isBranch = 1, isTerminator = 1 in 3579def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3580 "b", ".w\t$target", 3581 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> { 3582 let Inst{31-27} = 0b11110; 3583 let Inst{15-14} = 0b10; 3584 let Inst{12} = 0; 3585 3586 bits<4> p; 3587 let Inst{25-22} = p; 3588 3589 bits<21> target; 3590 let Inst{26} = target{20}; 3591 let Inst{11} = target{19}; 3592 let Inst{13} = target{18}; 3593 let Inst{21-16} = target{17-12}; 3594 let Inst{10-0} = target{11-1}; 3595 3596 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3597 let AsmMatchConverter = "cvtThumbBranches"; 3598} 3599 3600// Tail calls. The MachO version of thumb tail calls uses a t2 branch, so 3601// it goes here. 3602let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3603 // IOS version. 3604 let Uses = [SP] in 3605 def tTAILJMPd: tPseudoExpand<(outs), 3606 (ins uncondbrtarget:$dst, pred:$p), 3607 4, IIC_Br, [], 3608 (t2B uncondbrtarget:$dst, pred:$p)>, 3609 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>; 3610} 3611 3612// IT block 3613let Defs = [ITSTATE] in 3614def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3615 AddrModeNone, 2, IIC_iALUx, 3616 "it$mask\t$cc", "", []>, 3617 ComplexDeprecationPredicate<"IT"> { 3618 // 16-bit instruction. 3619 let Inst{31-16} = 0x0000; 3620 let Inst{15-8} = 0b10111111; 3621 3622 bits<4> cc; 3623 bits<4> mask; 3624 let Inst{7-4} = cc; 3625 let Inst{3-0} = mask; 3626 3627 let DecoderMethod = "DecodeIT"; 3628} 3629 3630// Branch and Exchange Jazelle -- for disassembly only 3631// Rm = Inst{19-16} 3632def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>, 3633 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass, PreV8]> { 3634 bits<4> func; 3635 let Inst{31-27} = 0b11110; 3636 let Inst{26} = 0; 3637 let Inst{25-20} = 0b111100; 3638 let Inst{19-16} = func; 3639 let Inst{15-0} = 0b1000111100000000; 3640} 3641 3642// Compare and branch on zero / non-zero 3643let isBranch = 1, isTerminator = 1 in { 3644 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3645 "cbz\t$Rn, $target", []>, 3646 T1Misc<{0,0,?,1,?,?,?}>, 3647 Requires<[IsThumb2]>, Sched<[WriteBr]> { 3648 // A8.6.27 3649 bits<6> target; 3650 bits<3> Rn; 3651 let Inst{9} = target{5}; 3652 let Inst{7-3} = target{4-0}; 3653 let Inst{2-0} = Rn; 3654 } 3655 3656 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3657 "cbnz\t$Rn, $target", []>, 3658 T1Misc<{1,0,?,1,?,?,?}>, 3659 Requires<[IsThumb2]>, Sched<[WriteBr]> { 3660 // A8.6.27 3661 bits<6> target; 3662 bits<3> Rn; 3663 let Inst{9} = target{5}; 3664 let Inst{7-3} = target{4-0}; 3665 let Inst{2-0} = Rn; 3666 } 3667} 3668 3669 3670// Change Processor State is a system instruction. 3671// FIXME: Since the asm parser has currently no clean way to handle optional 3672// operands, create 3 versions of the same instruction. Once there's a clean 3673// framework to represent optional operands, change this behavior. 3674class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3675 !strconcat("cps", asm_op), []>, 3676 Requires<[IsThumb2, IsNotMClass]> { 3677 bits<2> imod; 3678 bits<3> iflags; 3679 bits<5> mode; 3680 bit M; 3681 3682 let Inst{31-11} = 0b111100111010111110000; 3683 let Inst{10-9} = imod; 3684 let Inst{8} = M; 3685 let Inst{7-5} = iflags; 3686 let Inst{4-0} = mode; 3687 let DecoderMethod = "DecodeT2CPSInstruction"; 3688} 3689 3690let M = 1 in 3691 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3692 "$imod\t$iflags, $mode">; 3693let mode = 0, M = 0 in 3694 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3695 "$imod.w\t$iflags">; 3696let imod = 0, iflags = 0, M = 1 in 3697 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">; 3698 3699def : t2InstAlias<"cps$imod.w $iflags, $mode", 3700 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>; 3701def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>; 3702 3703// A6.3.4 Branches and miscellaneous control 3704// Table A6-14 Change Processor State, and hint instructions 3705def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm", 3706 [(int_arm_hint imm0_239:$imm)]> { 3707 bits<8> imm; 3708 let Inst{31-3} = 0b11110011101011111000000000000; 3709 let Inst{7-0} = imm; 3710} 3711 3712def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p)>; 3713def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>; 3714def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>; 3715def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>; 3716def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>; 3717def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>; 3718def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> { 3719 let Predicates = [IsThumb2, HasV8]; 3720} 3721 3722def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", 3723 [(int_arm_dbg imm0_15:$opt)]> { 3724 bits<4> opt; 3725 let Inst{31-20} = 0b111100111010; 3726 let Inst{19-16} = 0b1111; 3727 let Inst{15-8} = 0b10000000; 3728 let Inst{7-4} = 0b1111; 3729 let Inst{3-0} = opt; 3730} 3731 3732// Secure Monitor Call is a system instruction. 3733// Option = Inst{19-16} 3734def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 3735 []>, Requires<[IsThumb2, HasTrustZone]> { 3736 let Inst{31-27} = 0b11110; 3737 let Inst{26-20} = 0b1111111; 3738 let Inst{15-12} = 0b1000; 3739 3740 bits<4> opt; 3741 let Inst{19-16} = opt; 3742} 3743 3744class T2DCPS<bits<2> opt, string opc> 3745 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> { 3746 let Inst{31-27} = 0b11110; 3747 let Inst{26-20} = 0b1111000; 3748 let Inst{19-16} = 0b1111; 3749 let Inst{15-12} = 0b1000; 3750 let Inst{11-2} = 0b0000000000; 3751 let Inst{1-0} = opt; 3752} 3753 3754def t2DCPS1 : T2DCPS<0b01, "dcps1">; 3755def t2DCPS2 : T2DCPS<0b10, "dcps2">; 3756def t2DCPS3 : T2DCPS<0b11, "dcps3">; 3757 3758class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, 3759 string opc, string asm, list<dag> pattern> 3760 : T2I<oops, iops, itin, opc, asm, pattern>, 3761 Requires<[IsThumb2,IsNotMClass]> { 3762 bits<5> mode; 3763 let Inst{31-25} = 0b1110100; 3764 let Inst{24-23} = Op; 3765 let Inst{22} = 0; 3766 let Inst{21} = W; 3767 let Inst{20-16} = 0b01101; 3768 let Inst{15-5} = 0b11000000000; 3769 let Inst{4-0} = mode{4-0}; 3770} 3771 3772// Store Return State is a system instruction. 3773def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3774 "srsdb", "\tsp!, $mode", []>; 3775def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3776 "srsdb","\tsp, $mode", []>; 3777def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3778 "srsia","\tsp!, $mode", []>; 3779def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3780 "srsia","\tsp, $mode", []>; 3781 3782 3783def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>; 3784def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>; 3785 3786def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>; 3787def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>; 3788 3789// Return From Exception is a system instruction. 3790class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 3791 string opc, string asm, list<dag> pattern> 3792 : T2I<oops, iops, itin, opc, asm, pattern>, 3793 Requires<[IsThumb2,IsNotMClass]> { 3794 let Inst{31-20} = op31_20{11-0}; 3795 3796 bits<4> Rn; 3797 let Inst{19-16} = Rn; 3798 let Inst{15-0} = 0xc000; 3799} 3800 3801def t2RFEDBW : T2RFE<0b111010000011, 3802 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 3803 [/* For disassembly only; pattern left blank */]>; 3804def t2RFEDB : T2RFE<0b111010000001, 3805 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 3806 [/* For disassembly only; pattern left blank */]>; 3807def t2RFEIAW : T2RFE<0b111010011011, 3808 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 3809 [/* For disassembly only; pattern left blank */]>; 3810def t2RFEIA : T2RFE<0b111010011001, 3811 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 3812 [/* For disassembly only; pattern left blank */]>; 3813 3814// B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. 3815// Exception return instruction is "subs pc, lr, #imm". 3816let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 3817def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary, 3818 "subs", "\tpc, lr, $imm", 3819 [(ARMintretflag imm0_255:$imm)]>, 3820 Requires<[IsThumb2,IsNotMClass]> { 3821 let Inst{31-8} = 0b111100111101111010001111; 3822 3823 bits<8> imm; 3824 let Inst{7-0} = imm; 3825} 3826 3827// Hypervisor Call is a system instruction. 3828let isCall = 1 in { 3829def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>, 3830 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> { 3831 bits<16> imm16; 3832 let Inst{31-20} = 0b111101111110; 3833 let Inst{19-16} = imm16{15-12}; 3834 let Inst{15-12} = 0b1000; 3835 let Inst{11-0} = imm16{11-0}; 3836} 3837} 3838 3839// Alias for HVC without the ".w" optional width specifier 3840def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>; 3841 3842// ERET - Return from exception in Hypervisor mode. 3843// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that 3844// includes virtualization extensions. 3845def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p)>, 3846 Requires<[IsThumb2, HasVirtualization]>; 3847 3848//===----------------------------------------------------------------------===// 3849// Non-Instruction Patterns 3850// 3851 3852// 32-bit immediate using movw + movt. 3853// This is a single pseudo instruction to make it re-materializable. 3854// FIXME: Remove this when we can do generalized remat. 3855let isReMaterializable = 1, isMoveImm = 1 in 3856def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 3857 [(set rGPR:$dst, (i32 imm:$src))]>, 3858 Requires<[IsThumb, UseMovt]>; 3859 3860// Pseudo instruction that combines movw + movt + add pc (if pic). 3861// It also makes it possible to rematerialize the instructions. 3862// FIXME: Remove this when we can do generalized remat and when machine licm 3863// can properly the instructions. 3864let isReMaterializable = 1 in { 3865def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3866 IIC_iMOVix2addpc, 3867 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 3868 Requires<[IsThumb2, UseMovt]>; 3869 3870} 3871 3872// ConstantPool, GlobalAddress, and JumpTable 3873def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 3874def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 3875 Requires<[IsThumb2, UseMovt]>; 3876 3877def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 3878 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 3879 3880// Pseudo instruction that combines ldr from constpool and add pc. This should 3881// be expanded into two instructions late to allow if-conversion and 3882// scheduling. 3883let canFoldAsLoad = 1, isReMaterializable = 1 in 3884def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 3885 IIC_iLoadiALU, 3886 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 3887 imm:$cp))]>, 3888 Requires<[IsThumb2]>; 3889 3890// Pseudo isntruction that combines movs + predicated rsbmi 3891// to implement integer ABS 3892let usesCustomInserter = 1, Defs = [CPSR] in { 3893def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), 3894 NoItinerary, []>, Requires<[IsThumb2]>; 3895} 3896 3897//===----------------------------------------------------------------------===// 3898// Coprocessor load/store -- for disassembly only 3899// 3900class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm> 3901 : T2I<oops, iops, NoItinerary, opc, asm, []> { 3902 let Inst{31-28} = op31_28; 3903 let Inst{27-25} = 0b110; 3904} 3905 3906multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> { 3907 def _OFFSET : T2CI<op31_28, 3908 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3909 asm, "\t$cop, $CRd, $addr"> { 3910 bits<13> addr; 3911 bits<4> cop; 3912 bits<4> CRd; 3913 let Inst{24} = 1; // P = 1 3914 let Inst{23} = addr{8}; 3915 let Inst{22} = Dbit; 3916 let Inst{21} = 0; // W = 0 3917 let Inst{20} = load; 3918 let Inst{19-16} = addr{12-9}; 3919 let Inst{15-12} = CRd; 3920 let Inst{11-8} = cop; 3921 let Inst{7-0} = addr{7-0}; 3922 let DecoderMethod = "DecodeCopMemInstruction"; 3923 } 3924 def _PRE : T2CI<op31_28, 3925 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 3926 asm, "\t$cop, $CRd, $addr!"> { 3927 bits<13> addr; 3928 bits<4> cop; 3929 bits<4> CRd; 3930 let Inst{24} = 1; // P = 1 3931 let Inst{23} = addr{8}; 3932 let Inst{22} = Dbit; 3933 let Inst{21} = 1; // W = 1 3934 let Inst{20} = load; 3935 let Inst{19-16} = addr{12-9}; 3936 let Inst{15-12} = CRd; 3937 let Inst{11-8} = cop; 3938 let Inst{7-0} = addr{7-0}; 3939 let DecoderMethod = "DecodeCopMemInstruction"; 3940 } 3941 def _POST: T2CI<op31_28, 3942 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3943 postidx_imm8s4:$offset), 3944 asm, "\t$cop, $CRd, $addr, $offset"> { 3945 bits<9> offset; 3946 bits<4> addr; 3947 bits<4> cop; 3948 bits<4> CRd; 3949 let Inst{24} = 0; // P = 0 3950 let Inst{23} = offset{8}; 3951 let Inst{22} = Dbit; 3952 let Inst{21} = 1; // W = 1 3953 let Inst{20} = load; 3954 let Inst{19-16} = addr; 3955 let Inst{15-12} = CRd; 3956 let Inst{11-8} = cop; 3957 let Inst{7-0} = offset{7-0}; 3958 let DecoderMethod = "DecodeCopMemInstruction"; 3959 } 3960 def _OPTION : T2CI<op31_28, (outs), 3961 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3962 coproc_option_imm:$option), 3963 asm, "\t$cop, $CRd, $addr, $option"> { 3964 bits<8> option; 3965 bits<4> addr; 3966 bits<4> cop; 3967 bits<4> CRd; 3968 let Inst{24} = 0; // P = 0 3969 let Inst{23} = 1; // U = 1 3970 let Inst{22} = Dbit; 3971 let Inst{21} = 0; // W = 0 3972 let Inst{20} = load; 3973 let Inst{19-16} = addr; 3974 let Inst{15-12} = CRd; 3975 let Inst{11-8} = cop; 3976 let Inst{7-0} = option; 3977 let DecoderMethod = "DecodeCopMemInstruction"; 3978 } 3979} 3980 3981defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">; 3982defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">; 3983defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">; 3984defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">; 3985defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">, Requires<[PreV8,IsThumb2]>; 3986defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">, Requires<[PreV8,IsThumb2]>; 3987defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">, Requires<[PreV8,IsThumb2]>; 3988defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">, Requires<[PreV8,IsThumb2]>; 3989 3990 3991//===----------------------------------------------------------------------===// 3992// Move between special register and ARM core register -- for disassembly only 3993// 3994// Move to ARM core register from Special Register 3995 3996// A/R class MRS. 3997// 3998// A/R class can only move from CPSR or SPSR. 3999def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", 4000 []>, Requires<[IsThumb2,IsNotMClass]> { 4001 bits<4> Rd; 4002 let Inst{31-12} = 0b11110011111011111000; 4003 let Inst{11-8} = Rd; 4004 let Inst{7-0} = 0b00000000; 4005} 4006 4007def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; 4008 4009def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", 4010 []>, Requires<[IsThumb2,IsNotMClass]> { 4011 bits<4> Rd; 4012 let Inst{31-12} = 0b11110011111111111000; 4013 let Inst{11-8} = Rd; 4014 let Inst{7-0} = 0b00000000; 4015} 4016 4017def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked), 4018 NoItinerary, "mrs", "\t$Rd, $banked", []>, 4019 Requires<[IsThumb, HasVirtualization]> { 4020 bits<6> banked; 4021 bits<4> Rd; 4022 4023 let Inst{31-21} = 0b11110011111; 4024 let Inst{20} = banked{5}; // R bit 4025 let Inst{19-16} = banked{3-0}; 4026 let Inst{15-12} = 0b1000; 4027 let Inst{11-8} = Rd; 4028 let Inst{7-5} = 0b001; 4029 let Inst{4} = banked{4}; 4030 let Inst{3-0} = 0b0000; 4031} 4032 4033 4034// M class MRS. 4035// 4036// This MRS has a mask field in bits 7-0 and can take more values than 4037// the A/R class (a full msr_mask). 4038def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary, 4039 "mrs", "\t$Rd, $SYSm", []>, 4040 Requires<[IsThumb,IsMClass]> { 4041 bits<4> Rd; 4042 bits<8> SYSm; 4043 let Inst{31-12} = 0b11110011111011111000; 4044 let Inst{11-8} = Rd; 4045 let Inst{7-0} = SYSm; 4046 4047 let Unpredictable{20-16} = 0b11111; 4048 let Unpredictable{13} = 0b1; 4049} 4050 4051 4052// Move from ARM core register to Special Register 4053// 4054// A/R class MSR. 4055// 4056// No need to have both system and application versions, the encodings are the 4057// same and the assembly parser has no way to distinguish between them. The mask 4058// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 4059// the mask with the fields to be accessed in the special register. 4060def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), 4061 NoItinerary, "msr", "\t$mask, $Rn", []>, 4062 Requires<[IsThumb2,IsNotMClass]> { 4063 bits<5> mask; 4064 bits<4> Rn; 4065 let Inst{31-21} = 0b11110011100; 4066 let Inst{20} = mask{4}; // R Bit 4067 let Inst{19-16} = Rn; 4068 let Inst{15-12} = 0b1000; 4069 let Inst{11-8} = mask{3-0}; 4070 let Inst{7-0} = 0; 4071} 4072 4073// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 4074// separate encoding (distinguished by bit 5. 4075def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn), 4076 NoItinerary, "msr", "\t$banked, $Rn", []>, 4077 Requires<[IsThumb, HasVirtualization]> { 4078 bits<6> banked; 4079 bits<4> Rn; 4080 4081 let Inst{31-21} = 0b11110011100; 4082 let Inst{20} = banked{5}; // R bit 4083 let Inst{19-16} = Rn; 4084 let Inst{15-12} = 0b1000; 4085 let Inst{11-8} = banked{3-0}; 4086 let Inst{7-5} = 0b001; 4087 let Inst{4} = banked{4}; 4088 let Inst{3-0} = 0b0000; 4089} 4090 4091 4092// M class MSR. 4093// 4094// Move from ARM core register to Special Register 4095def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), 4096 NoItinerary, "msr", "\t$SYSm, $Rn", []>, 4097 Requires<[IsThumb,IsMClass]> { 4098 bits<12> SYSm; 4099 bits<4> Rn; 4100 let Inst{31-21} = 0b11110011100; 4101 let Inst{20} = 0b0; 4102 let Inst{19-16} = Rn; 4103 let Inst{15-12} = 0b1000; 4104 let Inst{11-10} = SYSm{11-10}; 4105 let Inst{9-8} = 0b00; 4106 let Inst{7-0} = SYSm{7-0}; 4107 4108 let Unpredictable{20} = 0b1; 4109 let Unpredictable{13} = 0b1; 4110 let Unpredictable{9-8} = 0b11; 4111} 4112 4113 4114//===----------------------------------------------------------------------===// 4115// Move between coprocessor and ARM core register 4116// 4117 4118class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 4119 list<dag> pattern> 4120 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4121 pattern> { 4122 let Inst{27-24} = 0b1110; 4123 let Inst{20} = direction; 4124 let Inst{4} = 1; 4125 4126 bits<4> Rt; 4127 bits<4> cop; 4128 bits<3> opc1; 4129 bits<3> opc2; 4130 bits<4> CRm; 4131 bits<4> CRn; 4132 4133 let Inst{15-12} = Rt; 4134 let Inst{11-8} = cop; 4135 let Inst{23-21} = opc1; 4136 let Inst{7-5} = opc2; 4137 let Inst{3-0} = CRm; 4138 let Inst{19-16} = CRn; 4139} 4140 4141class t2MovRRCopro<bits<4> Op, string opc, bit direction, 4142 list<dag> pattern = []> 4143 : T2Cop<Op, (outs), 4144 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 4145 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4146 let Inst{27-24} = 0b1100; 4147 let Inst{23-21} = 0b010; 4148 let Inst{20} = direction; 4149 4150 bits<4> Rt; 4151 bits<4> Rt2; 4152 bits<4> cop; 4153 bits<4> opc1; 4154 bits<4> CRm; 4155 4156 let Inst{15-12} = Rt; 4157 let Inst{19-16} = Rt2; 4158 let Inst{11-8} = cop; 4159 let Inst{7-4} = opc1; 4160 let Inst{3-0} = CRm; 4161} 4162 4163/* from ARM core register to coprocessor */ 4164def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 4165 (outs), 4166 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4167 c_imm:$CRm, imm0_7:$opc2), 4168 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4169 imm:$CRm, imm:$opc2)]>, 4170 ComplexDeprecationPredicate<"MCR">; 4171def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4172 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4173 c_imm:$CRm, 0, pred:$p)>; 4174def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 4175 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4176 c_imm:$CRm, imm0_7:$opc2), 4177 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4178 imm:$CRm, imm:$opc2)]> { 4179 let Predicates = [IsThumb2, PreV8]; 4180} 4181def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4182 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4183 c_imm:$CRm, 0, pred:$p)>; 4184 4185/* from coprocessor to ARM core register */ 4186def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 4187 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4188 c_imm:$CRm, imm0_7:$opc2), []>; 4189def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4190 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4191 c_imm:$CRm, 0, pred:$p)>; 4192 4193def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 4194 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4195 c_imm:$CRm, imm0_7:$opc2), []> { 4196 let Predicates = [IsThumb2, PreV8]; 4197} 4198def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4199 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4200 c_imm:$CRm, 0, pred:$p)>; 4201 4202def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4203 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4204 4205def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4206 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4207 4208 4209/* from ARM core register to coprocessor */ 4210def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, 4211 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 4212 imm:$CRm)]>; 4213def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, 4214 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, 4215 GPR:$Rt2, imm:$CRm)]> { 4216 let Predicates = [IsThumb2, PreV8]; 4217} 4218 4219/* from coprocessor to ARM core register */ 4220def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>; 4221 4222def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1> { 4223 let Predicates = [IsThumb2, PreV8]; 4224} 4225 4226//===----------------------------------------------------------------------===// 4227// Other Coprocessor Instructions. 4228// 4229 4230def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4231 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4232 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4233 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4234 imm:$CRm, imm:$opc2)]> { 4235 let Inst{27-24} = 0b1110; 4236 4237 bits<4> opc1; 4238 bits<4> CRn; 4239 bits<4> CRd; 4240 bits<4> cop; 4241 bits<3> opc2; 4242 bits<4> CRm; 4243 4244 let Inst{3-0} = CRm; 4245 let Inst{4} = 0; 4246 let Inst{7-5} = opc2; 4247 let Inst{11-8} = cop; 4248 let Inst{15-12} = CRd; 4249 let Inst{19-16} = CRn; 4250 let Inst{23-20} = opc1; 4251 4252 let Predicates = [IsThumb2, PreV8]; 4253} 4254 4255def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4256 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4257 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4258 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4259 imm:$CRm, imm:$opc2)]> { 4260 let Inst{27-24} = 0b1110; 4261 4262 bits<4> opc1; 4263 bits<4> CRn; 4264 bits<4> CRd; 4265 bits<4> cop; 4266 bits<3> opc2; 4267 bits<4> CRm; 4268 4269 let Inst{3-0} = CRm; 4270 let Inst{4} = 0; 4271 let Inst{7-5} = opc2; 4272 let Inst{11-8} = cop; 4273 let Inst{15-12} = CRd; 4274 let Inst{19-16} = CRn; 4275 let Inst{23-20} = opc1; 4276 4277 let Predicates = [IsThumb2, PreV8]; 4278} 4279 4280 4281 4282//===----------------------------------------------------------------------===// 4283// Non-Instruction Patterns 4284// 4285 4286// SXT/UXT with no rotate 4287let AddedComplexity = 16 in { 4288def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 4289 Requires<[IsThumb2]>; 4290def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 4291 Requires<[IsThumb2]>; 4292def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 4293 Requires<[HasT2ExtractPack, IsThumb2]>; 4294def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 4295 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4296 Requires<[HasT2ExtractPack, IsThumb2]>; 4297def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 4298 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4299 Requires<[HasT2ExtractPack, IsThumb2]>; 4300} 4301 4302def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 4303 Requires<[IsThumb2]>; 4304def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 4305 Requires<[IsThumb2]>; 4306def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 4307 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4308 Requires<[HasT2ExtractPack, IsThumb2]>; 4309def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 4310 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4311 Requires<[HasT2ExtractPack, IsThumb2]>; 4312 4313// Atomic load/store patterns 4314def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 4315 (t2LDRBi12 t2addrmode_imm12:$addr)>; 4316def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 4317 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 4318def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 4319 (t2LDRBs t2addrmode_so_reg:$addr)>; 4320def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 4321 (t2LDRHi12 t2addrmode_imm12:$addr)>; 4322def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 4323 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 4324def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 4325 (t2LDRHs t2addrmode_so_reg:$addr)>; 4326def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 4327 (t2LDRi12 t2addrmode_imm12:$addr)>; 4328def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 4329 (t2LDRi8 t2addrmode_negimm8:$addr)>; 4330def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 4331 (t2LDRs t2addrmode_so_reg:$addr)>; 4332def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 4333 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 4334def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 4335 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4336def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 4337 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 4338def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 4339 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 4340def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 4341 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4342def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 4343 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 4344def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 4345 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 4346def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 4347 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4348def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 4349 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 4350 4351let AddedComplexity = 8 in { 4352 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>; 4353 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>; 4354 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>; 4355 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>; 4356 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>; 4357 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>; 4358} 4359 4360 4361//===----------------------------------------------------------------------===// 4362// Assembler aliases 4363// 4364 4365// Aliases for ADC without the ".w" optional width specifier. 4366def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 4367 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4368def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 4369 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4370 pred:$p, cc_out:$s)>; 4371 4372// Aliases for SBC without the ".w" optional width specifier. 4373def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 4374 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4375def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 4376 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4377 pred:$p, cc_out:$s)>; 4378 4379// Aliases for ADD without the ".w" optional width specifier. 4380def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4381 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, 4382 cc_out:$s)>; 4383def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4384 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4385def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 4386 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4387def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 4388 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4389 pred:$p, cc_out:$s)>; 4390// ... and with the destination and source register combined. 4391def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4392 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4393def : t2InstAlias<"add${p} $Rdn, $imm", 4394 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 4395def : t2InstAlias<"add${s}${p} $Rdn, $Rm", 4396 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4397def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm", 4398 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4399 pred:$p, cc_out:$s)>; 4400 4401// add w/ negative immediates is just a sub. 4402def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4403 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4404 cc_out:$s)>; 4405def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4406 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4407def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4408 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4409 cc_out:$s)>; 4410def : t2InstAlias<"add${p} $Rdn, $imm", 4411 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4412 4413def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm", 4414 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4415 cc_out:$s)>; 4416def : t2InstAlias<"addw${p} $Rd, $Rn, $imm", 4417 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4418def : t2InstAlias<"add${s}${p}.w $Rdn, $imm", 4419 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4420 cc_out:$s)>; 4421def : t2InstAlias<"addw${p} $Rdn, $imm", 4422 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4423 4424 4425// Aliases for SUB without the ".w" optional width specifier. 4426def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 4427 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4428def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 4429 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4430def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm", 4431 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4432def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm", 4433 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4434 pred:$p, cc_out:$s)>; 4435// ... and with the destination and source register combined. 4436def : t2InstAlias<"sub${s}${p} $Rdn, $imm", 4437 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4438def : t2InstAlias<"sub${p} $Rdn, $imm", 4439 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 4440def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm", 4441 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4442def : t2InstAlias<"sub${s}${p} $Rdn, $Rm", 4443 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4444def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm", 4445 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4446 pred:$p, cc_out:$s)>; 4447 4448// Alias for compares without the ".w" optional width specifier. 4449def : t2InstAlias<"cmn${p} $Rn, $Rm", 4450 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4451def : t2InstAlias<"teq${p} $Rn, $Rm", 4452 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4453def : t2InstAlias<"tst${p} $Rn, $Rm", 4454 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4455 4456// Memory barriers 4457def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[HasDB]>; 4458def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[HasDB]>; 4459def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[HasDB]>; 4460 4461// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional 4462// width specifier. 4463def : t2InstAlias<"ldr${p} $Rt, $addr", 4464 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4465def : t2InstAlias<"ldrb${p} $Rt, $addr", 4466 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4467def : t2InstAlias<"ldrh${p} $Rt, $addr", 4468 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4469def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4470 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4471def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4472 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4473 4474def : t2InstAlias<"ldr${p} $Rt, $addr", 4475 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4476def : t2InstAlias<"ldrb${p} $Rt, $addr", 4477 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4478def : t2InstAlias<"ldrh${p} $Rt, $addr", 4479 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4480def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4481 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4482def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4483 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4484 4485def : t2InstAlias<"ldr${p} $Rt, $addr", 4486 (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p)>; 4487def : t2InstAlias<"ldrb${p} $Rt, $addr", 4488 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4489def : t2InstAlias<"ldrh${p} $Rt, $addr", 4490 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4491def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4492 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4493def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4494 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4495 4496// Alias for MVN with(out) the ".w" optional width specifier. 4497def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm", 4498 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4499def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", 4500 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; 4501def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", 4502 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; 4503 4504// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 4505// shift amount is zero (i.e., unspecified). 4506def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 4507 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 4508 Requires<[HasT2ExtractPack, IsThumb2]>; 4509def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 4510 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 4511 Requires<[HasT2ExtractPack, IsThumb2]>; 4512 4513// PUSH/POP aliases for STM/LDM 4514def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4515def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4516def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4517def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4518 4519// STMIA/STMIA_UPD aliases w/o the optional .w suffix 4520def : t2InstAlias<"stm${p} $Rn, $regs", 4521 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4522def : t2InstAlias<"stm${p} $Rn!, $regs", 4523 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4524 4525// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix 4526def : t2InstAlias<"ldm${p} $Rn, $regs", 4527 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4528def : t2InstAlias<"ldm${p} $Rn!, $regs", 4529 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4530 4531// STMDB/STMDB_UPD aliases w/ the optional .w suffix 4532def : t2InstAlias<"stmdb${p}.w $Rn, $regs", 4533 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4534def : t2InstAlias<"stmdb${p}.w $Rn!, $regs", 4535 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4536 4537// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix 4538def : t2InstAlias<"ldmdb${p}.w $Rn, $regs", 4539 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4540def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs", 4541 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4542 4543// Alias for REV/REV16/REVSH without the ".w" optional width specifier. 4544def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4545def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4546def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4547 4548 4549// Alias for RSB without the ".w" optional width specifier, and with optional 4550// implied destination register. 4551def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm", 4552 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4553def : t2InstAlias<"rsb${s}${p} $Rdn, $imm", 4554 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4555def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm", 4556 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4557def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm", 4558 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, 4559 cc_out:$s)>; 4560 4561// SSAT/USAT optional shift operand. 4562def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 4563 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4564def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", 4565 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4566 4567// STM w/o the .w suffix. 4568def : t2InstAlias<"stm${p} $Rn, $regs", 4569 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4570 4571// Alias for STR, STRB, and STRH without the ".w" optional 4572// width specifier. 4573def : t2InstAlias<"str${p} $Rt, $addr", 4574 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4575def : t2InstAlias<"strb${p} $Rt, $addr", 4576 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4577def : t2InstAlias<"strh${p} $Rt, $addr", 4578 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4579 4580def : t2InstAlias<"str${p} $Rt, $addr", 4581 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4582def : t2InstAlias<"strb${p} $Rt, $addr", 4583 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4584def : t2InstAlias<"strh${p} $Rt, $addr", 4585 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4586 4587// Extend instruction optional rotate operand. 4588def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm", 4589 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4590def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm", 4591 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4592def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 4593 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4594 4595def : t2InstAlias<"sxtb${p} $Rd, $Rm", 4596 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4597def : t2InstAlias<"sxtb16${p} $Rd, $Rm", 4598 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4599def : t2InstAlias<"sxth${p} $Rd, $Rm", 4600 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4601def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", 4602 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4603def : t2InstAlias<"sxth${p}.w $Rd, $Rm", 4604 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4605 4606def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", 4607 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4608def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm", 4609 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4610def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 4611 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 4612def : t2InstAlias<"uxtb${p} $Rd, $Rm", 4613 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4614def : t2InstAlias<"uxtb16${p} $Rd, $Rm", 4615 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4616def : t2InstAlias<"uxth${p} $Rd, $Rm", 4617 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4618 4619def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", 4620 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4621def : t2InstAlias<"uxth${p}.w $Rd, $Rm", 4622 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4623 4624// Extend instruction w/o the ".w" optional width specifier. 4625def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", 4626 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4627def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot", 4628 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4629def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", 4630 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4631 4632def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot", 4633 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4634def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot", 4635 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4636def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", 4637 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4638 4639 4640// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like 4641// for isel. 4642def : t2InstAlias<"mov${p} $Rd, $imm", 4643 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 4644def : t2InstAlias<"mvn${p} $Rd, $imm", 4645 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 4646// Same for AND <--> BIC 4647def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm", 4648 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4649 pred:$p, cc_out:$s)>; 4650def : t2InstAlias<"bic${s}${p} $Rdn, $imm", 4651 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4652 pred:$p, cc_out:$s)>; 4653def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm", 4654 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4655 pred:$p, cc_out:$s)>; 4656def : t2InstAlias<"and${s}${p} $Rdn, $imm", 4657 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4658 pred:$p, cc_out:$s)>; 4659// Likewise, "add Rd, t2_so_imm_neg" -> sub 4660def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4661 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, 4662 pred:$p, cc_out:$s)>; 4663def : t2InstAlias<"add${s}${p} $Rd, $imm", 4664 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm, 4665 pred:$p, cc_out:$s)>; 4666// Same for CMP <--> CMN via t2_so_imm_neg 4667def : t2InstAlias<"cmp${p} $Rd, $imm", 4668 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4669def : t2InstAlias<"cmn${p} $Rd, $imm", 4670 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4671 4672 4673// Wide 'mul' encoding can be specified with only two operands. 4674def : t2InstAlias<"mul${p} $Rn, $Rm", 4675 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>; 4676 4677// "neg" is and alias for "rsb rd, rn, #0" 4678def : t2InstAlias<"neg${s}${p} $Rd, $Rm", 4679 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>; 4680 4681// MOV so_reg assembler pseudos. InstAlias isn't expressive enough for 4682// these, unfortunately. 4683def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift", 4684 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4685def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift", 4686 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4687 4688def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", 4689 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4690def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", 4691 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4692 4693// ADR w/o the .w suffix 4694def : t2InstAlias<"adr${p} $Rd, $addr", 4695 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; 4696 4697// LDR(literal) w/ alternate [pc, #imm] syntax. 4698def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr", 4699 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4700def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr", 4701 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4702def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr", 4703 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4704def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr", 4705 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4706def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr", 4707 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4708 // Version w/ the .w suffix. 4709def : t2InstAlias<"ldr${p}.w $Rt, $addr", 4710 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>; 4711def : t2InstAlias<"ldrb${p}.w $Rt, $addr", 4712 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4713def : t2InstAlias<"ldrh${p}.w $Rt, $addr", 4714 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4715def : t2InstAlias<"ldrsb${p}.w $Rt, $addr", 4716 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4717def : t2InstAlias<"ldrsh${p}.w $Rt, $addr", 4718 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4719 4720def : t2InstAlias<"add${p} $Rd, pc, $imm", 4721 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>; 4722 4723// PLD/PLDW/PLI with alternate literal form. 4724def : t2InstAlias<"pld${p} $addr", 4725 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>; 4726def : InstAlias<"pli${p} $addr", 4727 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>, 4728 Requires<[IsThumb2,HasV7]>; 4729