1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "ARM.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMSubtarget.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "Thumb2InstrInfo.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/IR/Function.h" // To access Function attributes
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Target/TargetMachine.h"
25 using namespace llvm;
26
27 #define DEBUG_TYPE "t2-reduce-size"
28
29 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
30 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
31 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
32
33 static cl::opt<int> ReduceLimit("t2-reduce-limit",
34 cl::init(-1), cl::Hidden);
35 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
36 cl::init(-1), cl::Hidden);
37 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
38 cl::init(-1), cl::Hidden);
39
40 namespace {
41 /// ReduceTable - A static table with information on mapping from wide
42 /// opcodes to narrow
43 struct ReduceEntry {
44 uint16_t WideOpc; // Wide opcode
45 uint16_t NarrowOpc1; // Narrow opcode to transform to
46 uint16_t NarrowOpc2; // Narrow opcode when it's two-address
47 uint8_t Imm1Limit; // Limit of immediate field (bits)
48 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
49 unsigned LowRegs1 : 1; // Only possible if low-registers are used
50 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
51 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
52 // 1 - No cc field.
53 // 2 - Always set CPSR.
54 unsigned PredCC2 : 2;
55 unsigned PartFlag : 1; // 16-bit instruction does partial flag update
56 unsigned Special : 1; // Needs to be dealt with specially
57 unsigned AvoidMovs: 1; // Avoid movs with shifter operand (for Swift)
58 };
59
60 static const ReduceEntry ReduceTable[] = {
61 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
62 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
63 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
64 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
65 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
66 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
67 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
68 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
69 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
70 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
71 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
72 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
73 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
74 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
75 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
76 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
77 // FIXME: adr.n immediate offset must be multiple of 4.
78 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
79 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
80 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
81 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
82 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
83 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
84 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
85 // FIXME: Do we need the 16-bit 'S' variant?
86 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
87 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
88 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
89 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
91 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
92 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
94 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
95 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
96 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
97 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
98 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
99 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
100 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
101 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
102 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
103 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
104 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
105 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
106
107 // FIXME: Clean this up after splitting each Thumb load / store opcode
108 // into multiple ones.
109 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
110 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
111 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
123
124 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
125 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
126 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
128 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
129 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
130 };
131
132 class Thumb2SizeReduce : public MachineFunctionPass {
133 public:
134 static char ID;
135 Thumb2SizeReduce();
136
137 const Thumb2InstrInfo *TII;
138 const ARMSubtarget *STI;
139
140 bool runOnMachineFunction(MachineFunction &MF) override;
141
getPassName() const142 const char *getPassName() const override {
143 return "Thumb2 instruction size reduction pass";
144 }
145
146 private:
147 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
148 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
149
150 bool canAddPseudoFlagDep(MachineInstr *Use, bool IsSelfLoop);
151
152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
153 bool is2Addr, ARMCC::CondCodes Pred,
154 bool LiveCPSR, bool &HasCC, bool &CCDead);
155
156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
157 const ReduceEntry &Entry);
158
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
160 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
161
162 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
163 /// instruction.
164 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
165 const ReduceEntry &Entry, bool LiveCPSR,
166 bool IsSelfLoop);
167
168 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
169 /// non-two-address instruction.
170 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
171 const ReduceEntry &Entry, bool LiveCPSR,
172 bool IsSelfLoop);
173
174 /// ReduceMI - Attempt to reduce MI, return true on success.
175 bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
176 bool LiveCPSR, bool IsSelfLoop);
177
178 /// ReduceMBB - Reduce width of instructions in the specified basic block.
179 bool ReduceMBB(MachineBasicBlock &MBB);
180
181 bool OptimizeSize;
182 bool MinimizeSize;
183
184 // Last instruction to define CPSR in the current block.
185 MachineInstr *CPSRDef;
186 // Was CPSR last defined by a high latency instruction?
187 // When CPSRDef is null, this refers to CPSR defs in predecessors.
188 bool HighLatencyCPSR;
189
190 struct MBBInfo {
191 // The flags leaving this block have high latency.
192 bool HighLatencyCPSR;
193 // Has this block been visited yet?
194 bool Visited;
195
MBBInfo__anon7f3c275a0111::Thumb2SizeReduce::MBBInfo196 MBBInfo() : HighLatencyCPSR(false), Visited(false) {}
197 };
198
199 SmallVector<MBBInfo, 8> BlockInfo;
200 };
201 char Thumb2SizeReduce::ID = 0;
202 }
203
Thumb2SizeReduce()204 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) {
205 OptimizeSize = MinimizeSize = false;
206 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
207 unsigned FromOpc = ReduceTable[i].WideOpc;
208 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
209 assert(false && "Duplicated entries?");
210 }
211 }
212
HasImplicitCPSRDef(const MCInstrDesc & MCID)213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
215 if (*Regs == ARM::CPSR)
216 return true;
217 return false;
218 }
219
220 // Check for a likely high-latency flag def.
isHighLatencyCPSR(MachineInstr * Def)221 static bool isHighLatencyCPSR(MachineInstr *Def) {
222 switch(Def->getOpcode()) {
223 case ARM::FMSTAT:
224 case ARM::tMUL:
225 return true;
226 }
227 return false;
228 }
229
230 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
231 /// the 's' 16-bit instruction partially update CPSR. Abort the
232 /// transformation to avoid adding false dependency on last CPSR setting
233 /// instruction which hurts the ability for out-of-order execution engine
234 /// to do register renaming magic.
235 /// This function checks if there is a read-of-write dependency between the
236 /// last instruction that defines the CPSR and the current instruction. If there
237 /// is, then there is no harm done since the instruction cannot be retired
238 /// before the CPSR setting instruction anyway.
239 /// Note, we are not doing full dependency analysis here for the sake of compile
240 /// time. We're not looking for cases like:
241 /// r0 = muls ...
242 /// r1 = add.w r0, ...
243 /// ...
244 /// = mul.w r1
245 /// In this case it would have been ok to narrow the mul.w to muls since there
246 /// are indirect RAW dependency between the muls and the mul.w
247 bool
canAddPseudoFlagDep(MachineInstr * Use,bool FirstInSelfLoop)248 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
249 // Disable the check for -Oz (aka OptimizeForSizeHarder).
250 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
251 return false;
252
253 if (!CPSRDef)
254 // If this BB loops back to itself, conservatively avoid narrowing the
255 // first instruction that does partial flag update.
256 return HighLatencyCPSR || FirstInSelfLoop;
257
258 SmallSet<unsigned, 2> Defs;
259 for (const MachineOperand &MO : CPSRDef->operands()) {
260 if (!MO.isReg() || MO.isUndef() || MO.isUse())
261 continue;
262 unsigned Reg = MO.getReg();
263 if (Reg == 0 || Reg == ARM::CPSR)
264 continue;
265 Defs.insert(Reg);
266 }
267
268 for (const MachineOperand &MO : Use->operands()) {
269 if (!MO.isReg() || MO.isUndef() || MO.isDef())
270 continue;
271 unsigned Reg = MO.getReg();
272 if (Defs.count(Reg))
273 return false;
274 }
275
276 // If the current CPSR has high latency, try to avoid the false dependency.
277 if (HighLatencyCPSR)
278 return true;
279
280 // tMOVi8 usually doesn't start long dependency chains, and there are a lot
281 // of them, so always shrink them when CPSR doesn't have high latency.
282 if (Use->getOpcode() == ARM::t2MOVi ||
283 Use->getOpcode() == ARM::t2MOVi16)
284 return false;
285
286 // No read-after-write dependency. The narrowing will add false dependency.
287 return true;
288 }
289
290 bool
VerifyPredAndCC(MachineInstr * MI,const ReduceEntry & Entry,bool is2Addr,ARMCC::CondCodes Pred,bool LiveCPSR,bool & HasCC,bool & CCDead)291 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
292 bool is2Addr, ARMCC::CondCodes Pred,
293 bool LiveCPSR, bool &HasCC, bool &CCDead) {
294 if ((is2Addr && Entry.PredCC2 == 0) ||
295 (!is2Addr && Entry.PredCC1 == 0)) {
296 if (Pred == ARMCC::AL) {
297 // Not predicated, must set CPSR.
298 if (!HasCC) {
299 // Original instruction was not setting CPSR, but CPSR is not
300 // currently live anyway. It's ok to set it. The CPSR def is
301 // dead though.
302 if (!LiveCPSR) {
303 HasCC = true;
304 CCDead = true;
305 return true;
306 }
307 return false;
308 }
309 } else {
310 // Predicated, must not set CPSR.
311 if (HasCC)
312 return false;
313 }
314 } else if ((is2Addr && Entry.PredCC2 == 2) ||
315 (!is2Addr && Entry.PredCC1 == 2)) {
316 /// Old opcode has an optional def of CPSR.
317 if (HasCC)
318 return true;
319 // If old opcode does not implicitly define CPSR, then it's not ok since
320 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
321 if (!HasImplicitCPSRDef(MI->getDesc()))
322 return false;
323 HasCC = true;
324 } else {
325 // 16-bit instruction does not set CPSR.
326 if (HasCC)
327 return false;
328 }
329
330 return true;
331 }
332
VerifyLowRegs(MachineInstr * MI)333 static bool VerifyLowRegs(MachineInstr *MI) {
334 unsigned Opc = MI->getOpcode();
335 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
336 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
337 Opc == ARM::t2LDMDB_UPD);
338 bool isLROk = (Opc == ARM::t2STMDB_UPD);
339 bool isSPOk = isPCOk || isLROk;
340 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
341 const MachineOperand &MO = MI->getOperand(i);
342 if (!MO.isReg() || MO.isImplicit())
343 continue;
344 unsigned Reg = MO.getReg();
345 if (Reg == 0 || Reg == ARM::CPSR)
346 continue;
347 if (isPCOk && Reg == ARM::PC)
348 continue;
349 if (isLROk && Reg == ARM::LR)
350 continue;
351 if (Reg == ARM::SP) {
352 if (isSPOk)
353 continue;
354 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
355 // Special case for these ldr / str with sp as base register.
356 continue;
357 }
358 if (!isARMLowRegister(Reg))
359 return false;
360 }
361 return true;
362 }
363
364 bool
ReduceLoadStore(MachineBasicBlock & MBB,MachineInstr * MI,const ReduceEntry & Entry)365 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
366 const ReduceEntry &Entry) {
367 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
368 return false;
369
370 unsigned Scale = 1;
371 bool HasImmOffset = false;
372 bool HasShift = false;
373 bool HasOffReg = true;
374 bool isLdStMul = false;
375 unsigned Opc = Entry.NarrowOpc1;
376 unsigned OpNum = 3; // First 'rest' of operands.
377 uint8_t ImmLimit = Entry.Imm1Limit;
378
379 switch (Entry.WideOpc) {
380 default:
381 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
382 case ARM::t2LDRi12:
383 case ARM::t2STRi12:
384 if (MI->getOperand(1).getReg() == ARM::SP) {
385 Opc = Entry.NarrowOpc2;
386 ImmLimit = Entry.Imm2Limit;
387 }
388
389 Scale = 4;
390 HasImmOffset = true;
391 HasOffReg = false;
392 break;
393 case ARM::t2LDRBi12:
394 case ARM::t2STRBi12:
395 HasImmOffset = true;
396 HasOffReg = false;
397 break;
398 case ARM::t2LDRHi12:
399 case ARM::t2STRHi12:
400 Scale = 2;
401 HasImmOffset = true;
402 HasOffReg = false;
403 break;
404 case ARM::t2LDRs:
405 case ARM::t2LDRBs:
406 case ARM::t2LDRHs:
407 case ARM::t2LDRSBs:
408 case ARM::t2LDRSHs:
409 case ARM::t2STRs:
410 case ARM::t2STRBs:
411 case ARM::t2STRHs:
412 HasShift = true;
413 OpNum = 4;
414 break;
415 case ARM::t2LDMIA:
416 case ARM::t2LDMDB: {
417 unsigned BaseReg = MI->getOperand(0).getReg();
418 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
419 return false;
420
421 // For the non-writeback version (this one), the base register must be
422 // one of the registers being loaded.
423 bool isOK = false;
424 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
425 if (MI->getOperand(i).getReg() == BaseReg) {
426 isOK = true;
427 break;
428 }
429 }
430
431 if (!isOK)
432 return false;
433
434 OpNum = 0;
435 isLdStMul = true;
436 break;
437 }
438 case ARM::t2LDMIA_RET: {
439 unsigned BaseReg = MI->getOperand(1).getReg();
440 if (BaseReg != ARM::SP)
441 return false;
442 Opc = Entry.NarrowOpc2; // tPOP_RET
443 OpNum = 2;
444 isLdStMul = true;
445 break;
446 }
447 case ARM::t2LDMIA_UPD:
448 case ARM::t2LDMDB_UPD:
449 case ARM::t2STMIA_UPD:
450 case ARM::t2STMDB_UPD: {
451 OpNum = 0;
452
453 unsigned BaseReg = MI->getOperand(1).getReg();
454 if (BaseReg == ARM::SP &&
455 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
456 Entry.WideOpc == ARM::t2STMDB_UPD)) {
457 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
458 OpNum = 2;
459 } else if (!isARMLowRegister(BaseReg) ||
460 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
461 Entry.WideOpc != ARM::t2STMIA_UPD)) {
462 return false;
463 }
464
465 isLdStMul = true;
466 break;
467 }
468 }
469
470 unsigned OffsetReg = 0;
471 bool OffsetKill = false;
472 if (HasShift) {
473 OffsetReg = MI->getOperand(2).getReg();
474 OffsetKill = MI->getOperand(2).isKill();
475
476 if (MI->getOperand(3).getImm())
477 // Thumb1 addressing mode doesn't support shift.
478 return false;
479 }
480
481 unsigned OffsetImm = 0;
482 if (HasImmOffset) {
483 OffsetImm = MI->getOperand(2).getImm();
484 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
485
486 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
487 // Make sure the immediate field fits.
488 return false;
489 }
490
491 // Add the 16-bit load / store instruction.
492 DebugLoc dl = MI->getDebugLoc();
493 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
494 if (!isLdStMul) {
495 MIB.addOperand(MI->getOperand(0));
496 MIB.addOperand(MI->getOperand(1));
497
498 if (HasImmOffset)
499 MIB.addImm(OffsetImm / Scale);
500
501 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
502
503 if (HasOffReg)
504 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
505 }
506
507 // Transfer the rest of operands.
508 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
509 MIB.addOperand(MI->getOperand(OpNum));
510
511 // Transfer memoperands.
512 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
513
514 // Transfer MI flags.
515 MIB.setMIFlags(MI->getFlags());
516
517 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
518
519 MBB.erase_instr(MI);
520 ++NumLdSts;
521 return true;
522 }
523
524 bool
ReduceSpecial(MachineBasicBlock & MBB,MachineInstr * MI,const ReduceEntry & Entry,bool LiveCPSR,bool IsSelfLoop)525 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
526 const ReduceEntry &Entry,
527 bool LiveCPSR, bool IsSelfLoop) {
528 unsigned Opc = MI->getOpcode();
529 if (Opc == ARM::t2ADDri) {
530 // If the source register is SP, try to reduce to tADDrSPi, otherwise
531 // it's a normal reduce.
532 if (MI->getOperand(1).getReg() != ARM::SP) {
533 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
534 return true;
535 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
536 }
537 // Try to reduce to tADDrSPi.
538 unsigned Imm = MI->getOperand(2).getImm();
539 // The immediate must be in range, the destination register must be a low
540 // reg, the predicate must be "always" and the condition flags must not
541 // be being set.
542 if (Imm & 3 || Imm > 1020)
543 return false;
544 if (!isARMLowRegister(MI->getOperand(0).getReg()))
545 return false;
546 if (MI->getOperand(3).getImm() != ARMCC::AL)
547 return false;
548 const MCInstrDesc &MCID = MI->getDesc();
549 if (MCID.hasOptionalDef() &&
550 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
551 return false;
552
553 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(),
554 TII->get(ARM::tADDrSPi))
555 .addOperand(MI->getOperand(0))
556 .addOperand(MI->getOperand(1))
557 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
558 AddDefaultPred(MIB);
559
560 // Transfer MI flags.
561 MIB.setMIFlags(MI->getFlags());
562
563 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
564
565 MBB.erase_instr(MI);
566 ++NumNarrows;
567 return true;
568 }
569
570 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
571 return false;
572
573 if (MI->mayLoad() || MI->mayStore())
574 return ReduceLoadStore(MBB, MI, Entry);
575
576 switch (Opc) {
577 default: break;
578 case ARM::t2ADDSri:
579 case ARM::t2ADDSrr: {
580 unsigned PredReg = 0;
581 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
582 switch (Opc) {
583 default: break;
584 case ARM::t2ADDSri: {
585 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
586 return true;
587 // fallthrough
588 }
589 case ARM::t2ADDSrr:
590 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
591 }
592 }
593 break;
594 }
595 case ARM::t2RSBri:
596 case ARM::t2RSBSri:
597 case ARM::t2SXTB:
598 case ARM::t2SXTH:
599 case ARM::t2UXTB:
600 case ARM::t2UXTH:
601 if (MI->getOperand(2).getImm() == 0)
602 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
603 break;
604 case ARM::t2MOVi16:
605 // Can convert only 'pure' immediate operands, not immediates obtained as
606 // globals' addresses.
607 if (MI->getOperand(1).isImm())
608 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
609 break;
610 case ARM::t2CMPrr: {
611 // Try to reduce to the lo-reg only version first. Why there are two
612 // versions of the instruction is a mystery.
613 // It would be nice to just have two entries in the master table that
614 // are prioritized, but the table assumes a unique entry for each
615 // source insn opcode. So for now, we hack a local entry record to use.
616 static const ReduceEntry NarrowEntry =
617 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
618 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
619 return true;
620 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
621 }
622 }
623 return false;
624 }
625
626 bool
ReduceTo2Addr(MachineBasicBlock & MBB,MachineInstr * MI,const ReduceEntry & Entry,bool LiveCPSR,bool IsSelfLoop)627 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
628 const ReduceEntry &Entry,
629 bool LiveCPSR, bool IsSelfLoop) {
630
631 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
632 return false;
633
634 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
635 STI->avoidMOVsShifterOperand())
636 // Don't issue movs with shifter operand for some CPUs unless we
637 // are optimizing / minimizing for size.
638 return false;
639
640 unsigned Reg0 = MI->getOperand(0).getReg();
641 unsigned Reg1 = MI->getOperand(1).getReg();
642 // t2MUL is "special". The tied source operand is second, not first.
643 if (MI->getOpcode() == ARM::t2MUL) {
644 unsigned Reg2 = MI->getOperand(2).getReg();
645 // Early exit if the regs aren't all low regs.
646 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
647 || !isARMLowRegister(Reg2))
648 return false;
649 if (Reg0 != Reg2) {
650 // If the other operand also isn't the same as the destination, we
651 // can't reduce.
652 if (Reg1 != Reg0)
653 return false;
654 // Try to commute the operands to make it a 2-address instruction.
655 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
656 if (!CommutedMI)
657 return false;
658 }
659 } else if (Reg0 != Reg1) {
660 // Try to commute the operands to make it a 2-address instruction.
661 unsigned CommOpIdx1, CommOpIdx2;
662 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
663 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
664 return false;
665 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
666 if (!CommutedMI)
667 return false;
668 }
669 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
670 return false;
671 if (Entry.Imm2Limit) {
672 unsigned Imm = MI->getOperand(2).getImm();
673 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
674 if (Imm > Limit)
675 return false;
676 } else {
677 unsigned Reg2 = MI->getOperand(2).getReg();
678 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
679 return false;
680 }
681
682 // Check if it's possible / necessary to transfer the predicate.
683 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
684 unsigned PredReg = 0;
685 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
686 bool SkipPred = false;
687 if (Pred != ARMCC::AL) {
688 if (!NewMCID.isPredicable())
689 // Can't transfer predicate, fail.
690 return false;
691 } else {
692 SkipPred = !NewMCID.isPredicable();
693 }
694
695 bool HasCC = false;
696 bool CCDead = false;
697 const MCInstrDesc &MCID = MI->getDesc();
698 if (MCID.hasOptionalDef()) {
699 unsigned NumOps = MCID.getNumOperands();
700 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
701 if (HasCC && MI->getOperand(NumOps-1).isDead())
702 CCDead = true;
703 }
704 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
705 return false;
706
707 // Avoid adding a false dependency on partial flag update by some 16-bit
708 // instructions which has the 's' bit set.
709 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
710 canAddPseudoFlagDep(MI, IsSelfLoop))
711 return false;
712
713 // Add the 16-bit instruction.
714 DebugLoc dl = MI->getDebugLoc();
715 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
716 MIB.addOperand(MI->getOperand(0));
717 if (NewMCID.hasOptionalDef()) {
718 if (HasCC)
719 AddDefaultT1CC(MIB, CCDead);
720 else
721 AddNoT1CC(MIB);
722 }
723
724 // Transfer the rest of operands.
725 unsigned NumOps = MCID.getNumOperands();
726 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
727 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
728 continue;
729 if (SkipPred && MCID.OpInfo[i].isPredicate())
730 continue;
731 MIB.addOperand(MI->getOperand(i));
732 }
733
734 // Transfer MI flags.
735 MIB.setMIFlags(MI->getFlags());
736
737 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
738
739 MBB.erase_instr(MI);
740 ++Num2Addrs;
741 return true;
742 }
743
744 bool
ReduceToNarrow(MachineBasicBlock & MBB,MachineInstr * MI,const ReduceEntry & Entry,bool LiveCPSR,bool IsSelfLoop)745 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
746 const ReduceEntry &Entry,
747 bool LiveCPSR, bool IsSelfLoop) {
748 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
749 return false;
750
751 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
752 STI->avoidMOVsShifterOperand())
753 // Don't issue movs with shifter operand for some CPUs unless we
754 // are optimizing / minimizing for size.
755 return false;
756
757 unsigned Limit = ~0U;
758 if (Entry.Imm1Limit)
759 Limit = (1 << Entry.Imm1Limit) - 1;
760
761 const MCInstrDesc &MCID = MI->getDesc();
762 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
763 if (MCID.OpInfo[i].isPredicate())
764 continue;
765 const MachineOperand &MO = MI->getOperand(i);
766 if (MO.isReg()) {
767 unsigned Reg = MO.getReg();
768 if (!Reg || Reg == ARM::CPSR)
769 continue;
770 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
771 return false;
772 } else if (MO.isImm() &&
773 !MCID.OpInfo[i].isPredicate()) {
774 if (((unsigned)MO.getImm()) > Limit)
775 return false;
776 }
777 }
778
779 // Check if it's possible / necessary to transfer the predicate.
780 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
781 unsigned PredReg = 0;
782 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
783 bool SkipPred = false;
784 if (Pred != ARMCC::AL) {
785 if (!NewMCID.isPredicable())
786 // Can't transfer predicate, fail.
787 return false;
788 } else {
789 SkipPred = !NewMCID.isPredicable();
790 }
791
792 bool HasCC = false;
793 bool CCDead = false;
794 if (MCID.hasOptionalDef()) {
795 unsigned NumOps = MCID.getNumOperands();
796 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
797 if (HasCC && MI->getOperand(NumOps-1).isDead())
798 CCDead = true;
799 }
800 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
801 return false;
802
803 // Avoid adding a false dependency on partial flag update by some 16-bit
804 // instructions which has the 's' bit set.
805 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
806 canAddPseudoFlagDep(MI, IsSelfLoop))
807 return false;
808
809 // Add the 16-bit instruction.
810 DebugLoc dl = MI->getDebugLoc();
811 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
812 MIB.addOperand(MI->getOperand(0));
813 if (NewMCID.hasOptionalDef()) {
814 if (HasCC)
815 AddDefaultT1CC(MIB, CCDead);
816 else
817 AddNoT1CC(MIB);
818 }
819
820 // Transfer the rest of operands.
821 unsigned NumOps = MCID.getNumOperands();
822 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
823 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
824 continue;
825 if ((MCID.getOpcode() == ARM::t2RSBSri ||
826 MCID.getOpcode() == ARM::t2RSBri ||
827 MCID.getOpcode() == ARM::t2SXTB ||
828 MCID.getOpcode() == ARM::t2SXTH ||
829 MCID.getOpcode() == ARM::t2UXTB ||
830 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
831 // Skip the zero immediate operand, it's now implicit.
832 continue;
833 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
834 if (SkipPred && isPred)
835 continue;
836 const MachineOperand &MO = MI->getOperand(i);
837 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
838 // Skip implicit def of CPSR. Either it's modeled as an optional
839 // def now or it's already an implicit def on the new instruction.
840 continue;
841 MIB.addOperand(MO);
842 }
843 if (!MCID.isPredicable() && NewMCID.isPredicable())
844 AddDefaultPred(MIB);
845
846 // Transfer MI flags.
847 MIB.setMIFlags(MI->getFlags());
848
849 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
850
851 MBB.erase_instr(MI);
852 ++NumNarrows;
853 return true;
854 }
855
UpdateCPSRDef(MachineInstr & MI,bool LiveCPSR,bool & DefCPSR)856 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
857 bool HasDef = false;
858 for (const MachineOperand &MO : MI.operands()) {
859 if (!MO.isReg() || MO.isUndef() || MO.isUse())
860 continue;
861 if (MO.getReg() != ARM::CPSR)
862 continue;
863
864 DefCPSR = true;
865 if (!MO.isDead())
866 HasDef = true;
867 }
868
869 return HasDef || LiveCPSR;
870 }
871
UpdateCPSRUse(MachineInstr & MI,bool LiveCPSR)872 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
873 for (const MachineOperand &MO : MI.operands()) {
874 if (!MO.isReg() || MO.isUndef() || MO.isDef())
875 continue;
876 if (MO.getReg() != ARM::CPSR)
877 continue;
878 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
879 if (MO.isKill()) {
880 LiveCPSR = false;
881 break;
882 }
883 }
884
885 return LiveCPSR;
886 }
887
ReduceMI(MachineBasicBlock & MBB,MachineInstr * MI,bool LiveCPSR,bool IsSelfLoop)888 bool Thumb2SizeReduce::ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
889 bool LiveCPSR, bool IsSelfLoop) {
890 unsigned Opcode = MI->getOpcode();
891 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
892 if (OPI == ReduceOpcodeMap.end())
893 return false;
894 const ReduceEntry &Entry = ReduceTable[OPI->second];
895
896 // Don't attempt normal reductions on "special" cases for now.
897 if (Entry.Special)
898 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
899
900 // Try to transform to a 16-bit two-address instruction.
901 if (Entry.NarrowOpc2 &&
902 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
903 return true;
904
905 // Try to transform to a 16-bit non-two-address instruction.
906 if (Entry.NarrowOpc1 &&
907 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
908 return true;
909
910 return false;
911 }
912
ReduceMBB(MachineBasicBlock & MBB)913 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
914 bool Modified = false;
915
916 // Yes, CPSR could be livein.
917 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
918 MachineInstr *BundleMI = nullptr;
919
920 CPSRDef = nullptr;
921 HighLatencyCPSR = false;
922
923 // Check predecessors for the latest CPSRDef.
924 for (auto *Pred : MBB.predecessors()) {
925 const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
926 if (!PInfo.Visited) {
927 // Since blocks are visited in RPO, this must be a back-edge.
928 continue;
929 }
930 if (PInfo.HighLatencyCPSR) {
931 HighLatencyCPSR = true;
932 break;
933 }
934 }
935
936 // If this BB loops back to itself, conservatively avoid narrowing the
937 // first instruction that does partial flag update.
938 bool IsSelfLoop = MBB.isSuccessor(&MBB);
939 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),E = MBB.instr_end();
940 MachineBasicBlock::instr_iterator NextMII;
941 for (; MII != E; MII = NextMII) {
942 NextMII = std::next(MII);
943
944 MachineInstr *MI = &*MII;
945 if (MI->isBundle()) {
946 BundleMI = MI;
947 continue;
948 }
949 if (MI->isDebugValue())
950 continue;
951
952 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
953
954 // Does NextMII belong to the same bundle as MI?
955 bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();
956
957 if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
958 Modified = true;
959 MachineBasicBlock::instr_iterator I = std::prev(NextMII);
960 MI = &*I;
961 // Removing and reinserting the first instruction in a bundle will break
962 // up the bundle. Fix the bundling if it was broken.
963 if (NextInSameBundle && !NextMII->isBundledWithPred())
964 NextMII->bundleWithPred();
965 }
966
967 if (!NextInSameBundle && MI->isInsideBundle()) {
968 // FIXME: Since post-ra scheduler operates on bundles, the CPSR kill
969 // marker is only on the BUNDLE instruction. Process the BUNDLE
970 // instruction as we finish with the bundled instruction to work around
971 // the inconsistency.
972 if (BundleMI->killsRegister(ARM::CPSR))
973 LiveCPSR = false;
974 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
975 if (MO && !MO->isDead())
976 LiveCPSR = true;
977 MO = BundleMI->findRegisterUseOperand(ARM::CPSR);
978 if (MO && !MO->isKill())
979 LiveCPSR = true;
980 }
981
982 bool DefCPSR = false;
983 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
984 if (MI->isCall()) {
985 // Calls don't really set CPSR.
986 CPSRDef = nullptr;
987 HighLatencyCPSR = false;
988 IsSelfLoop = false;
989 } else if (DefCPSR) {
990 // This is the last CPSR defining instruction.
991 CPSRDef = MI;
992 HighLatencyCPSR = isHighLatencyCPSR(CPSRDef);
993 IsSelfLoop = false;
994 }
995 }
996
997 MBBInfo &Info = BlockInfo[MBB.getNumber()];
998 Info.HighLatencyCPSR = HighLatencyCPSR;
999 Info.Visited = true;
1000 return Modified;
1001 }
1002
runOnMachineFunction(MachineFunction & MF)1003 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
1004 const TargetMachine &TM = MF.getTarget();
1005 TII = static_cast<const Thumb2InstrInfo *>(
1006 TM.getSubtargetImpl()->getInstrInfo());
1007 STI = &TM.getSubtarget<ARMSubtarget>();
1008
1009 // Optimizing / minimizing size?
1010 AttributeSet FnAttrs = MF.getFunction()->getAttributes();
1011 OptimizeSize = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
1012 Attribute::OptimizeForSize);
1013 MinimizeSize =
1014 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
1015
1016 BlockInfo.clear();
1017 BlockInfo.resize(MF.getNumBlockIDs());
1018
1019 // Visit blocks in reverse post-order so LastCPSRDef is known for all
1020 // predecessors.
1021 ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
1022 bool Modified = false;
1023 for (ReversePostOrderTraversal<MachineFunction*>::rpo_iterator
1024 I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
1025 Modified |= ReduceMBB(**I);
1026 return Modified;
1027 }
1028
1029 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
1030 /// reduction pass.
createThumb2SizeReductionPass()1031 FunctionPass *llvm::createThumb2SizeReductionPass() {
1032 return new Thumb2SizeReduce();
1033 }
1034