1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
12 
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include <map>
15 
16 namespace llvm {
17 
18   namespace Hexagon {
19     const unsigned int StartPacket = 0x1;
20     const unsigned int EndPacket = 0x2;
21   }
22 
23 
24 /// Hexagon target-specific information for each MachineFunction.
25 class HexagonMachineFunctionInfo : public MachineFunctionInfo {
26   // SRetReturnReg - Some subtargets require that sret lowering includes
27   // returning the value of the returned struct in a register. This field
28   // holds the virtual register into which the sret argument is passed.
29   unsigned SRetReturnReg;
30   std::vector<MachineInstr*> AllocaAdjustInsts;
31   int VarArgsFrameIndex;
32   bool HasClobberLR;
33   bool HasEHReturn;
34   std::map<const MachineInstr*, unsigned> PacketInfo;
35   virtual void anchor();
36 
37 public:
HexagonMachineFunctionInfo()38   HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),
39     HasEHReturn(false) {}
40 
HexagonMachineFunctionInfo(MachineFunction & MF)41   HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
42                                                     HasClobberLR(0),
43                                                     HasEHReturn(false) {}
44 
getSRetReturnReg()45   unsigned getSRetReturnReg() const { return SRetReturnReg; }
setSRetReturnReg(unsigned Reg)46   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
47 
addAllocaAdjustInst(MachineInstr * MI)48   void addAllocaAdjustInst(MachineInstr* MI) {
49     AllocaAdjustInsts.push_back(MI);
50   }
getAllocaAdjustInsts()51   const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
52     return AllocaAdjustInsts;
53   }
54 
setVarArgsFrameIndex(int v)55   void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
getVarArgsFrameIndex()56   int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
57 
setStartPacket(MachineInstr * MI)58   void setStartPacket(MachineInstr* MI) {
59     PacketInfo[MI] |= Hexagon::StartPacket;
60   }
setEndPacket(MachineInstr * MI)61   void setEndPacket(MachineInstr* MI)   {
62     PacketInfo[MI] |= Hexagon::EndPacket;
63   }
isStartPacket(const MachineInstr * MI)64   bool isStartPacket(const MachineInstr* MI) const {
65     return (PacketInfo.count(MI) &&
66             (PacketInfo.find(MI)->second & Hexagon::StartPacket));
67   }
isEndPacket(const MachineInstr * MI)68   bool isEndPacket(const MachineInstr* MI) const {
69     return (PacketInfo.count(MI) &&
70             (PacketInfo.find(MI)->second & Hexagon::EndPacket));
71   }
setHasClobberLR(bool v)72   void setHasClobberLR(bool v) { HasClobberLR = v;  }
hasClobberLR()73   bool hasClobberLR() const { return HasClobberLR; }
74 
hasEHReturn()75   bool hasEHReturn() const { return HasEHReturn; };
76   void setHasEHReturn(bool H = true) { HasEHReturn = H; };
77 };
78 } // End llvm namespace
79 
80 #endif
81