1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 
38 using namespace llvm;
39 
40 
HexagonRegisterInfo(HexagonSubtarget & st)41 HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st)
42   : HexagonGenRegisterInfo(Hexagon::R31),
43     Subtarget(st) {
44 }
45 
46 const MCPhysReg *
getCalleeSavedRegs(const MachineFunction * MF) const47 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
48   static const MCPhysReg CalleeSavedRegsV2[] = {
49     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
50   };
51   static const MCPhysReg CalleeSavedRegsV3[] = {
52     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
53     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
54     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
55   };
56 
57   switch(Subtarget.getHexagonArchVersion()) {
58   case HexagonSubtarget::V1:
59     break;
60   case HexagonSubtarget::V2:
61     return CalleeSavedRegsV2;
62   case HexagonSubtarget::V3:
63   case HexagonSubtarget::V4:
64   case HexagonSubtarget::V5:
65     return CalleeSavedRegsV3;
66   }
67   llvm_unreachable("Callee saved registers requested for unknown architecture "
68                    "version");
69 }
70 
getReservedRegs(const MachineFunction & MF) const71 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
72   const {
73   BitVector Reserved(getNumRegs());
74   Reserved.set(HEXAGON_RESERVED_REG_1);
75   Reserved.set(HEXAGON_RESERVED_REG_2);
76   Reserved.set(Hexagon::R29);
77   Reserved.set(Hexagon::R30);
78   Reserved.set(Hexagon::R31);
79   Reserved.set(Hexagon::D14);
80   Reserved.set(Hexagon::D15);
81   Reserved.set(Hexagon::LC0);
82   Reserved.set(Hexagon::LC1);
83   Reserved.set(Hexagon::SA0);
84   Reserved.set(Hexagon::SA1);
85   return Reserved;
86 }
87 
88 
89 const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction * MF) const90 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
91   static const TargetRegisterClass * const CalleeSavedRegClassesV2[] = {
92     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
93     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
94     };
95   static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
96     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
97     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
98     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
99     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
100     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
101     &Hexagon::IntRegsRegClass,     &Hexagon::IntRegsRegClass,
102   };
103 
104   switch(Subtarget.getHexagonArchVersion()) {
105   case HexagonSubtarget::V1:
106     break;
107   case HexagonSubtarget::V2:
108     return CalleeSavedRegClassesV2;
109   case HexagonSubtarget::V3:
110   case HexagonSubtarget::V4:
111   case HexagonSubtarget::V5:
112     return CalleeSavedRegClassesV3;
113   }
114   llvm_unreachable("Callee saved register classes requested for unknown "
115                    "architecture version");
116 }
117 
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const118 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
119                                               int SPAdj, unsigned FIOperandNum,
120                                               RegScavenger *RS) const {
121   //
122   // Hexagon_TODO: Do we need to enforce this for Hexagon?
123   assert(SPAdj == 0 && "Unexpected");
124 
125   MachineInstr &MI = *II;
126   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
127 
128   // Addressable stack objects are accessed using neg. offsets from %fp.
129   MachineFunction &MF = *MI.getParent()->getParent();
130   const HexagonInstrInfo &TII =
131       *static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
132   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
133   MachineFrameInfo &MFI = *MF.getFrameInfo();
134 
135   unsigned FrameReg = getFrameRegister(MF);
136   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
137   if (!TFI->hasFP(MF)) {
138     // We will not reserve space on the stack for the lr and fp registers.
139     Offset -= 2 * Hexagon_WordSize;
140   }
141 
142   const unsigned FrameSize = MFI.getStackSize();
143 
144   if (!MFI.hasVarSizedObjects() &&
145       TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
146       !TII.isSpillPredRegOp(&MI)) {
147     // Replace frame index with a stack pointer reference.
148     MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
149                                                  false, true);
150     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
151   } else {
152     // Replace frame index with a frame pointer reference.
153     if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
154 
155       // If the offset overflows, then correct it.
156       //
157       // For loads, we do not need a reserved register
158       // r0 = memw(r30 + #10000) to:
159       //
160       // r0 = add(r30, #10000)
161       // r0 = memw(r0)
162       if ( (MI.getOpcode() == Hexagon::L2_loadri_io)  ||
163            (MI.getOpcode() == Hexagon::L2_loadrd_io)   ||
164            (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
165            (MI.getOpcode() == Hexagon::L2_loadruh_io) ||
166            (MI.getOpcode() == Hexagon::L2_loadrb_io) ||
167            (MI.getOpcode() == Hexagon::L2_loadrub_io) ||
168            (MI.getOpcode() == Hexagon::LDriw_f) ||
169            (MI.getOpcode() == Hexagon::LDrid_f)) {
170         unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
171           getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
172           MI.getOperand(0).getReg();
173 
174         // Check if offset can fit in addi.
175         if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
176           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
177                   TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
178           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
179                   TII.get(Hexagon::A2_add),
180                   dstReg).addReg(FrameReg).addReg(dstReg);
181         } else {
182           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
183                   TII.get(Hexagon::ADD_ri),
184                   dstReg).addReg(FrameReg).addImm(Offset);
185         }
186 
187         MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
188         MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
189       } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) ||
190                  (MI.getOpcode() == Hexagon::S2_storerd_io) ||
191                  (MI.getOpcode() == Hexagon::S2_storerh_io) ||
192                  (MI.getOpcode() == Hexagon::S2_storerb_io) ||
193                  (MI.getOpcode() == Hexagon::STrid_f) ||
194                  (MI.getOpcode() == Hexagon::STriw_f)) {
195         // For stores, we need a reserved register. Change
196         // memw(r30 + #10000) = r0 to:
197         //
198         // rs = add(r30, #10000);
199         // memw(rs) = r0
200         unsigned resReg = HEXAGON_RESERVED_REG_1;
201 
202         // Check if offset can fit in addi.
203         if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
204           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
205                   TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
206           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
207                   TII.get(Hexagon::A2_add),
208                   resReg).addReg(FrameReg).addReg(resReg);
209         } else {
210           BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
211                   TII.get(Hexagon::ADD_ri),
212                   resReg).addReg(FrameReg).addImm(Offset);
213         }
214         MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
215         MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
216       } else if (TII.isMemOp(&MI)) {
217         // use the constant extender if the instruction provides it
218         // and we are V4TOps.
219         if (Subtarget.hasV4TOps()) {
220           if (TII.isConstExtended(&MI)) {
221             MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
222             MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
223             TII.immediateExtend(&MI);
224           } else {
225             llvm_unreachable("Need to implement for memops");
226           }
227         } else {
228           // Only V3 and older instructions here.
229           unsigned ResReg = HEXAGON_RESERVED_REG_1;
230           if (!MFI.hasVarSizedObjects() &&
231               TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
232             MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(),
233                                                          false, false, false);
234             MI.getOperand(FIOperandNum+1).ChangeToImmediate(FrameSize+Offset);
235           } else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
236             BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
237                     TII.get(Hexagon::CONST32_Int_Real), ResReg).addImm(Offset);
238             BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
239                     TII.get(Hexagon::A2_add), ResReg).addReg(FrameReg).
240               addReg(ResReg);
241             MI.getOperand(FIOperandNum).ChangeToRegister(ResReg, false, false,
242                                                          true);
243             MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
244           } else {
245             BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
246                     TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg).
247               addImm(Offset);
248             MI.getOperand(FIOperandNum).ChangeToRegister(ResReg, false, false,
249                                                          true);
250             MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
251           }
252         }
253       } else {
254         unsigned dstReg = MI.getOperand(0).getReg();
255         BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
256                 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
257         BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
258                 TII.get(Hexagon::A2_add),
259                 dstReg).addReg(FrameReg).addReg(dstReg);
260         // Can we delete MI??? r2 = add (r2, #0).
261         MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
262         MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
263       }
264     } else {
265       // If the offset is small enough to fit in the immediate field, directly
266       // encode it.
267       MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
268       MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
269     }
270   }
271 
272 }
273 
getRARegister() const274 unsigned HexagonRegisterInfo::getRARegister() const {
275   return Hexagon::R31;
276 }
277 
getFrameRegister(const MachineFunction & MF) const278 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
279                                                &MF) const {
280   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
281   if (TFI->hasFP(MF)) {
282     return Hexagon::R30;
283   }
284 
285   return Hexagon::R29;
286 }
287 
getFrameRegister() const288 unsigned HexagonRegisterInfo::getFrameRegister() const {
289   return Hexagon::R30;
290 }
291 
getStackRegister() const292 unsigned HexagonRegisterInfo::getStackRegister() const {
293   return Hexagon::R29;
294 }
295 
296 #define GET_REGINFO_TARGET_DESC
297 #include "HexagonGenRegisterInfo.inc"
298