1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "Mips.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/Target/TargetLowering.h" 24 #include <deque> 25 #include <string> 26 27 namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // FP-to-int truncation node. 64 TruncIntFP, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // Node used to extract integer from accumulator. 72 MFHI, 73 MFLO, 74 75 // Node used to insert integers to accumulator. 76 MTLOHI, 77 78 // Mult nodes. 79 Mult, 80 Multu, 81 82 // MAdd/Sub nodes 83 MAdd, 84 MAddu, 85 MSub, 86 MSubu, 87 88 // DivRem(u) 89 DivRem, 90 DivRemU, 91 DivRem16, 92 DivRemU16, 93 94 BuildPairF64, 95 ExtractElementF64, 96 97 Wrapper, 98 99 DynAlloc, 100 101 Sync, 102 103 Ext, 104 Ins, 105 106 // EXTR.W instrinsic nodes. 107 EXTP, 108 EXTPDP, 109 EXTR_S_H, 110 EXTR_W, 111 EXTR_R_W, 112 EXTR_RS_W, 113 SHILO, 114 MTHLIP, 115 116 // DPA.W intrinsic nodes. 117 MULSAQ_S_W_PH, 118 MAQ_S_W_PHL, 119 MAQ_S_W_PHR, 120 MAQ_SA_W_PHL, 121 MAQ_SA_W_PHR, 122 DPAU_H_QBL, 123 DPAU_H_QBR, 124 DPSU_H_QBL, 125 DPSU_H_QBR, 126 DPAQ_S_W_PH, 127 DPSQ_S_W_PH, 128 DPAQ_SA_L_W, 129 DPSQ_SA_L_W, 130 DPA_W_PH, 131 DPS_W_PH, 132 DPAQX_S_W_PH, 133 DPAQX_SA_W_PH, 134 DPAX_W_PH, 135 DPSX_W_PH, 136 DPSQX_S_W_PH, 137 DPSQX_SA_W_PH, 138 MULSA_W_PH, 139 140 MULT, 141 MULTU, 142 MADD_DSP, 143 MADDU_DSP, 144 MSUB_DSP, 145 MSUBU_DSP, 146 147 // DSP shift nodes. 148 SHLL_DSP, 149 SHRA_DSP, 150 SHRL_DSP, 151 152 // DSP setcc and select_cc nodes. 153 SETCC_DSP, 154 SELECT_CC_DSP, 155 156 // Vector comparisons. 157 // These take a vector and return a boolean. 158 VALL_ZERO, 159 VANY_ZERO, 160 VALL_NONZERO, 161 VANY_NONZERO, 162 163 // These take a vector and return a vector bitmask. 164 VCEQ, 165 VCLE_S, 166 VCLE_U, 167 VCLT_S, 168 VCLT_U, 169 170 // Element-wise vector max/min. 171 VSMAX, 172 VSMIN, 173 VUMAX, 174 VUMIN, 175 176 // Vector Shuffle with mask as an operand 177 VSHF, // Generic shuffle 178 SHF, // 4-element set shuffle. 179 ILVEV, // Interleave even elements 180 ILVOD, // Interleave odd elements 181 ILVL, // Interleave left elements 182 ILVR, // Interleave right elements 183 PCKEV, // Pack even elements 184 PCKOD, // Pack odd elements 185 186 // Vector Lane Copy 187 INSVE, // Copy element from one vector to another 188 189 // Combined (XOR (OR $a, $b), -1) 190 VNOR, 191 192 // Extended vector element extraction 193 VEXTRACT_SEXT_ELT, 194 VEXTRACT_ZEXT_ELT, 195 196 // Load/Store Left/Right nodes. 197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 198 LWR, 199 SWL, 200 SWR, 201 LDL, 202 LDR, 203 SDL, 204 SDR 205 }; 206 } 207 208 //===--------------------------------------------------------------------===// 209 // TargetLowering Implementation 210 //===--------------------------------------------------------------------===// 211 class MipsFunctionInfo; 212 class MipsSubtarget; 213 class MipsCCState; 214 215 class MipsTargetLowering : public TargetLowering { 216 bool isMicroMips; 217 public: 218 explicit MipsTargetLowering(const MipsTargetMachine &TM, 219 const MipsSubtarget &STI); 220 221 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 222 const MipsSubtarget &STI); 223 224 /// createFastISel - This method returns a target specific FastISel object, 225 /// or null if the target does not support "fast" ISel. 226 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 227 const TargetLibraryInfo *libInfo) const override; 228 getScalarShiftAmountTy(EVT LHSTy)229 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 230 231 void LowerOperationWrapper(SDNode *N, 232 SmallVectorImpl<SDValue> &Results, 233 SelectionDAG &DAG) const override; 234 235 /// LowerOperation - Provide custom lowering hooks for some operations. 236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 237 238 /// ReplaceNodeResults - Replace the results of node with an illegal result 239 /// type with new values built out of custom code. 240 /// 241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 242 SelectionDAG &DAG) const override; 243 244 /// getTargetNodeName - This method returns the name of a target specific 245 // DAG node. 246 const char *getTargetNodeName(unsigned Opcode) const override; 247 248 /// getSetCCResultType - get the ISD::SETCC result ValueType 249 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 250 251 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 252 253 MachineBasicBlock * 254 EmitInstrWithCustomInserter(MachineInstr *MI, 255 MachineBasicBlock *MBB) const override; 256 257 struct LTStr { operatorLTStr258 bool operator()(const char *S1, const char *S2) const { 259 return strcmp(S1, S2) < 0; 260 } 261 }; 262 263 void HandleByVal(CCState *, unsigned &, unsigned) const override; 264 265 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 266 267 protected: 268 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 269 270 // This method creates the following nodes, which are necessary for 271 // computing a local symbol's address: 272 // 273 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 274 template <class NodeTy> getAddrLocal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,bool IsN32OrN64)275 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 276 bool IsN32OrN64) const { 277 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 278 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 279 getTargetNode(N, Ty, DAG, GOTFlag)); 280 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 281 MachinePointerInfo::getGOT(), false, false, 282 false, 0); 283 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 284 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 285 getTargetNode(N, Ty, DAG, LoFlag)); 286 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 287 } 288 289 // This method creates the following nodes, which are necessary for 290 // computing a global symbol's address: 291 // 292 // (load (wrapper $gp, %got(sym))) 293 template <class NodeTy> getAddrGlobal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flag,SDValue Chain,const MachinePointerInfo & PtrInfo)294 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 295 unsigned Flag, SDValue Chain, 296 const MachinePointerInfo &PtrInfo) const { 297 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 298 getTargetNode(N, Ty, DAG, Flag)); 299 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 300 } 301 302 // This method creates the following nodes, which are necessary for 303 // computing a global symbol's address in large-GOT mode: 304 // 305 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 306 template <class NodeTy> getAddrGlobalLargeGOT(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned HiFlag,unsigned LoFlag,SDValue Chain,const MachinePointerInfo & PtrInfo)307 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, 308 SelectionDAG &DAG, unsigned HiFlag, 309 unsigned LoFlag, SDValue Chain, 310 const MachinePointerInfo &PtrInfo) const { 311 SDValue Hi = 312 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag)); 313 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 314 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 315 getTargetNode(N, Ty, DAG, LoFlag)); 316 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 317 0); 318 } 319 320 // This method creates the following nodes, which are necessary for 321 // computing a symbol's address in non-PIC mode: 322 // 323 // (add %hi(sym), %lo(sym)) 324 template <class NodeTy> getAddrNonPIC(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)325 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, 326 SelectionDAG &DAG) const { 327 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 328 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 329 return DAG.getNode(ISD::ADD, DL, Ty, 330 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 331 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 332 } 333 334 // This method creates the following nodes, which are necessary for 335 // computing a symbol's address using gp-relative addressing: 336 // 337 // (add $gp, %gp_rel(sym)) 338 template <class NodeTy> getAddrGPRel(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)339 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const { 340 assert(Ty == MVT::i32); 341 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 342 return DAG.getNode(ISD::ADD, DL, Ty, 343 DAG.getRegister(Mips::GP, Ty), 344 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), 345 GPRel)); 346 } 347 348 /// This function fills Ops, which is the list of operands that will later 349 /// be used when a function call node is created. It also generates 350 /// copyToReg nodes to set up argument registers. 351 virtual void 352 getOpndList(SmallVectorImpl<SDValue> &Ops, 353 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 354 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 355 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 356 SDValue Chain) const; 357 358 protected: 359 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 360 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 361 362 // Subtarget Info 363 const MipsSubtarget &Subtarget; 364 365 private: 366 // Create a TargetGlobalAddress node. 367 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 368 unsigned Flag) const; 369 370 // Create a TargetExternalSymbol node. 371 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 372 unsigned Flag) const; 373 374 // Create a TargetBlockAddress node. 375 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 376 unsigned Flag) const; 377 378 // Create a TargetJumpTable node. 379 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 380 unsigned Flag) const; 381 382 // Create a TargetConstantPool node. 383 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 384 unsigned Flag) const; 385 386 // Lower Operand helpers 387 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 388 CallingConv::ID CallConv, bool isVarArg, 389 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, 390 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 391 TargetLowering::CallLoweringInfo &CLI) const; 392 393 // Lower Operand specifics 394 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 395 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 396 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 397 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 398 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 399 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 400 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 401 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 402 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 403 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 404 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 405 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 406 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 407 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 408 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 409 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 410 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 411 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 412 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 413 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 414 bool IsSRA) const; 415 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 416 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 417 418 /// isEligibleForTailCallOptimization - Check whether the call is eligible 419 /// for tail call optimization. 420 virtual bool 421 isEligibleForTailCallOptimization(const CCState &CCInfo, 422 unsigned NextStackOffset, 423 const MipsFunctionInfo &FI) const = 0; 424 425 /// copyByValArg - Copy argument registers which were used to pass a byval 426 /// argument to the stack. Create a stack frame object for the byval 427 /// argument. 428 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 429 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 430 SmallVectorImpl<SDValue> &InVals, 431 const Argument *FuncArg, unsigned FirstReg, 432 unsigned LastReg, const CCValAssign &VA, 433 MipsCCState &State) const; 434 435 /// passByValArg - Pass a byval argument in registers or on stack. 436 void passByValArg(SDValue Chain, SDLoc DL, 437 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 438 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 439 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 440 unsigned FirstReg, unsigned LastReg, 441 const ISD::ArgFlagsTy &Flags, bool isLittle, 442 const CCValAssign &VA) const; 443 444 /// writeVarArgRegs - Write variable function arguments passed in registers 445 /// to the stack. Also create a stack frame object for the first variable 446 /// argument. 447 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 448 SDLoc DL, SelectionDAG &DAG, CCState &State) const; 449 450 SDValue 451 LowerFormalArguments(SDValue Chain, 452 CallingConv::ID CallConv, bool isVarArg, 453 const SmallVectorImpl<ISD::InputArg> &Ins, 454 SDLoc dl, SelectionDAG &DAG, 455 SmallVectorImpl<SDValue> &InVals) const override; 456 457 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 458 SDValue Arg, SDLoc DL, bool IsTailCall, 459 SelectionDAG &DAG) const; 460 461 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 462 SmallVectorImpl<SDValue> &InVals) const override; 463 464 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 465 bool isVarArg, 466 const SmallVectorImpl<ISD::OutputArg> &Outs, 467 LLVMContext &Context) const override; 468 469 SDValue LowerReturn(SDValue Chain, 470 CallingConv::ID CallConv, bool isVarArg, 471 const SmallVectorImpl<ISD::OutputArg> &Outs, 472 const SmallVectorImpl<SDValue> &OutVals, 473 SDLoc dl, SelectionDAG &DAG) const override; 474 475 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 476 477 // Inline asm support 478 ConstraintType 479 getConstraintType(const std::string &Constraint) const override; 480 481 /// Examine constraint string and operand type and determine a weight value. 482 /// The operand object must already have been set up with the operand type. 483 ConstraintWeight getSingleConstraintMatchWeight( 484 AsmOperandInfo &info, const char *constraint) const override; 485 486 /// This function parses registers that appear in inline-asm constraints. 487 /// It returns pair (0, 0) on failure. 488 std::pair<unsigned, const TargetRegisterClass *> 489 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 490 491 std::pair<unsigned, const TargetRegisterClass*> 492 getRegForInlineAsmConstraint(const std::string &Constraint, 493 MVT VT) const override; 494 495 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 496 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 497 /// true it means one of the asm constraint of the inline asm instruction 498 /// being processed is 'm'. 499 void LowerAsmOperandForConstraint(SDValue Op, 500 std::string &Constraint, 501 std::vector<SDValue> &Ops, 502 SelectionDAG &DAG) const override; 503 504 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 505 506 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 507 508 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 509 unsigned SrcAlign, 510 bool IsMemset, bool ZeroMemset, 511 bool MemcpyStrSrc, 512 MachineFunction &MF) const override; 513 514 /// isFPImmLegal - Returns true if the target can instruction select the 515 /// specified FP immediate natively. If false, the legalizer will 516 /// materialize the FP immediate as a load from a constant pool. 517 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 518 519 unsigned getJumpTableEncoding() const override; 520 521 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 522 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, 523 MachineBasicBlock *BB, 524 unsigned Size, unsigned DstReg, 525 unsigned SrcRec) const; 526 527 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 528 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 529 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 530 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 531 bool Nand = false) const; 532 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 533 MachineBasicBlock *BB, unsigned Size) const; 534 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 535 MachineBasicBlock *BB, unsigned Size) const; 536 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; 537 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, 538 MachineBasicBlock *BB, bool isFPCmp, 539 unsigned Opc) const; 540 }; 541 542 /// Create MipsTargetLowering objects. 543 const MipsTargetLowering * 544 createMips16TargetLowering(const MipsTargetMachine &TM, 545 const MipsSubtarget &STI); 546 const MipsTargetLowering * 547 createMipsSETargetLowering(const MipsTargetMachine &TM, 548 const MipsSubtarget &STI); 549 550 namespace Mips { 551 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 552 const TargetLibraryInfo *libInfo); 553 } 554 } 555 556 #endif 557