1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79 80// These are target-independent nodes, but have target-specific formats. 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 84 [SDNPHasChain, SDNPSideEffect, 85 SDNPOptInGlue, SDNPOutGlue]>; 86 87// Nodes used to extract LO/HI registers. 88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 108 [SDNPOutGlue]>; 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 110 [SDNPOutGlue]>; 111 112// Target constant nodes that are not part of any isel patterns and remain 113// unchanged can cause instructions with illegal operands to be emitted. 114// Wrapper node patterns give the instruction selector a chance to replace 115// target constant nodes that would otherwise remain unchanged with ADDiu 116// nodes. Without these wrapper node patterns, the following conditional move 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 118// compiled: 119// movn %got(d)($gp), %got(c)($gp), $4 120// This instruction is illegal since movn can take only register operands. 121 122def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 123 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 125 126def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 127def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 128 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 145 146//===----------------------------------------------------------------------===// 147// Mips Instruction Predicate Definitions. 148//===----------------------------------------------------------------------===// 149def HasMips2 : Predicate<"Subtarget->hasMips2()">, 150 AssemblerPredicate<"FeatureMips2">; 151def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, 152 AssemblerPredicate<"FeatureMips3_32">; 153def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, 154 AssemblerPredicate<"FeatureMips3_32r2">; 155def HasMips3 : Predicate<"Subtarget->hasMips3()">, 156 AssemblerPredicate<"FeatureMips3">; 157def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, 158 AssemblerPredicate<"FeatureMips4_32">; 159def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, 160 AssemblerPredicate<"FeatureMips4_32">; 161def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, 162 AssemblerPredicate<"FeatureMips4_32r2">; 163def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, 164 AssemblerPredicate<"FeatureMips5_32r2">; 165def HasMips32 : Predicate<"Subtarget->hasMips32()">, 166 AssemblerPredicate<"FeatureMips32">; 167def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, 168 AssemblerPredicate<"FeatureMips32r2">; 169def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, 170 AssemblerPredicate<"FeatureMips32r6">; 171def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, 172 AssemblerPredicate<"!FeatureMips32r6">; 173def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, 174 AssemblerPredicate<"FeatureGP64Bit">; 175def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, 176 AssemblerPredicate<"!FeatureGP64Bit">; 177def HasMips64 : Predicate<"Subtarget->hasMips64()">, 178 AssemblerPredicate<"FeatureMips64">; 179def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, 180 AssemblerPredicate<"FeatureMips64r2">; 181def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, 182 AssemblerPredicate<"FeatureMips64r6">; 183def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, 184 AssemblerPredicate<"!FeatureMips64r6">; 185def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, 186 AssemblerPredicate<"FeatureMips16">; 187def HasCnMips : Predicate<"Subtarget->hasCnMips()">, 188 AssemblerPredicate<"FeatureCnMips">; 189def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 190 AssemblerPredicate<"FeatureMips32">; 191def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 192 AssemblerPredicate<"FeatureMips32">; 193def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 194def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, 195 AssemblerPredicate<"!FeatureMips16">; 196def NotDSP : Predicate<"!Subtarget->hasDSP()">; 197def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, 198 AssemblerPredicate<"FeatureMicroMips">; 199def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, 200 AssemblerPredicate<"!FeatureMicroMips">; 201def IsLE : Predicate<"Subtarget->isLittle()">; 202def IsBE : Predicate<"!Subtarget->isLittle()">; 203def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 204 205//===----------------------------------------------------------------------===// 206// Mips GPR size adjectives. 207// They are mutually exclusive. 208//===----------------------------------------------------------------------===// 209 210class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 211class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 212 213//===----------------------------------------------------------------------===// 214// Mips ISA/ASE membership and instruction group membership adjectives. 215// They are mutually exclusive. 216//===----------------------------------------------------------------------===// 217 218// FIXME: I'd prefer to use additive predicates to build the instruction sets 219// but we are short on assembler feature bits at the moment. Using a 220// subtractive predicate will hopefully keep us under the 32 predicate 221// limit long enough to develop an alternative way to handle P1||P2 222// predicates. 223class ISA_MIPS1_NOT_4_32 { 224 list<Predicate> InsnPredicates = [NotMips4_32]; 225} 226class ISA_MIPS1_NOT_32R6_64R6 { 227 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 228} 229class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; } 230class ISA_MIPS2_NOT_32R6_64R6 { 231 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 232} 233class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; } 234class ISA_MIPS3_NOT_32R6_64R6 { 235 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 236} 237class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; } 238class ISA_MIPS32_NOT_32R6_64R6 { 239 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; 240} 241class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } 242class ISA_MIPS32R2_NOT_32R6_64R6 { 243 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; 244} 245class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } 246class ISA_MIPS64_NOT_64R6 { 247 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; 248} 249class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } 250class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } 251class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } 252 253// The portions of MIPS-III that were also added to MIPS32 254class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } 255 256// The portions of MIPS-III that were also added to MIPS32 but were removed in 257// MIPS32r6 and MIPS64r6. 258class INSN_MIPS3_32_NOT_32R6_64R6 { 259 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; 260} 261 262// The portions of MIPS-III that were also added to MIPS32 263class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } 264 265// The portions of MIPS-IV that were also added to MIPS32 but were removed in 266// MIPS32r6 and MIPS64r6. 267class INSN_MIPS4_32_NOT_32R6_64R6 { 268 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; 269} 270 271// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in 272// MIPS32r6 and MIPS64r6. 273class INSN_MIPS4_32R2_NOT_32R6_64R6 { 274 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; 275} 276 277// The portions of MIPS-V that were also added to MIPS32r2 but were removed in 278// MIPS32r6 and MIPS64r6. 279class INSN_MIPS5_32R2_NOT_32R6_64R6 { 280 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; 281} 282 283//===----------------------------------------------------------------------===// 284 285class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { 286 let EncodingPredicates = [HasStdEnc]; 287} 288 289class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 290 InstAlias<Asm, Result, Emit>, PredicateControl; 291 292class IsCommutable { 293 bit isCommutable = 1; 294} 295 296class IsBranch { 297 bit isBranch = 1; 298} 299 300class IsReturn { 301 bit isReturn = 1; 302} 303 304class IsCall { 305 bit isCall = 1; 306} 307 308class IsTailCall { 309 bit isCall = 1; 310 bit isTerminator = 1; 311 bit isReturn = 1; 312 bit isBarrier = 1; 313 bit hasExtraSrcRegAllocReq = 1; 314 bit isCodeGenOnly = 1; 315} 316 317class IsAsCheapAsAMove { 318 bit isAsCheapAsAMove = 1; 319} 320 321class NeverHasSideEffects { 322 bit hasSideEffects = 0; 323} 324 325//===----------------------------------------------------------------------===// 326// Instruction format superclass 327//===----------------------------------------------------------------------===// 328 329include "MipsInstrFormats.td" 330 331//===----------------------------------------------------------------------===// 332// Mips Operand, Complex Patterns and Transformations Definitions. 333//===----------------------------------------------------------------------===// 334 335def MipsJumpTargetAsmOperand : AsmOperandClass { 336 let Name = "JumpTarget"; 337 let ParserMethod = "parseJumpTarget"; 338 let PredicateMethod = "isImm"; 339 let RenderMethod = "addImmOperands"; 340} 341 342// Instruction operand types 343def jmptarget : Operand<OtherVT> { 344 let EncoderMethod = "getJumpTargetOpValue"; 345 let ParserMatchClass = MipsJumpTargetAsmOperand; 346} 347def brtarget : Operand<OtherVT> { 348 let EncoderMethod = "getBranchTargetOpValue"; 349 let OperandType = "OPERAND_PCREL"; 350 let DecoderMethod = "DecodeBranchTarget"; 351 let ParserMatchClass = MipsJumpTargetAsmOperand; 352} 353def calltarget : Operand<iPTR> { 354 let EncoderMethod = "getJumpTargetOpValue"; 355 let ParserMatchClass = MipsJumpTargetAsmOperand; 356} 357 358def simm9 : Operand<i32>; 359def simm10 : Operand<i32>; 360def simm11 : Operand<i32>; 361 362def simm16 : Operand<i32> { 363 let DecoderMethod= "DecodeSimm16"; 364} 365 366def simm19_lsl2 : Operand<i32> { 367 let EncoderMethod = "getSimm19Lsl2Encoding"; 368 let DecoderMethod = "DecodeSimm19Lsl2"; 369 let ParserMatchClass = MipsJumpTargetAsmOperand; 370} 371 372def simm18_lsl3 : Operand<i32> { 373 let EncoderMethod = "getSimm18Lsl3Encoding"; 374 let DecoderMethod = "DecodeSimm18Lsl3"; 375 let ParserMatchClass = MipsJumpTargetAsmOperand; 376} 377 378def simm20 : Operand<i32> { 379} 380 381def uimm20 : Operand<i32> { 382} 383 384def uimm10 : Operand<i32> { 385} 386 387def simm16_64 : Operand<i64> { 388 let DecoderMethod = "DecodeSimm16"; 389} 390 391// Zero 392def uimmz : Operand<i32> { 393 let PrintMethod = "printUnsignedImm"; 394} 395 396// Unsigned Operand 397def uimm2 : Operand<i32> { 398 let PrintMethod = "printUnsignedImm"; 399} 400 401def uimm3 : Operand<i32> { 402 let PrintMethod = "printUnsignedImm"; 403} 404 405def uimm5 : Operand<i32> { 406 let PrintMethod = "printUnsignedImm"; 407} 408 409def uimm6 : Operand<i32> { 410 let PrintMethod = "printUnsignedImm"; 411} 412 413def uimm16 : Operand<i32> { 414 let PrintMethod = "printUnsignedImm"; 415} 416 417def pcrel16 : Operand<i32> { 418} 419 420def MipsMemAsmOperand : AsmOperandClass { 421 let Name = "Mem"; 422 let ParserMethod = "parseMemOperand"; 423} 424 425def MipsMemSimm11AsmOperand : AsmOperandClass { 426 let Name = "MemOffsetSimm11"; 427 let SuperClasses = [MipsMemAsmOperand]; 428 let RenderMethod = "addMemOperands"; 429 let ParserMethod = "parseMemOperand"; 430 let PredicateMethod = "isMemWithSimmOffset<11>"; 431} 432 433def MipsMemSimm16AsmOperand : AsmOperandClass { 434 let Name = "MemOffsetSimm16"; 435 let SuperClasses = [MipsMemAsmOperand]; 436 let RenderMethod = "addMemOperands"; 437 let ParserMethod = "parseMemOperand"; 438 let PredicateMethod = "isMemWithSimmOffset<16>"; 439} 440 441def MipsInvertedImmoperand : AsmOperandClass { 442 let Name = "InvNum"; 443 let RenderMethod = "addImmOperands"; 444 let ParserMethod = "parseInvNum"; 445} 446 447def InvertedImOperand : Operand<i32> { 448 let ParserMatchClass = MipsInvertedImmoperand; 449} 450 451def InvertedImOperand64 : Operand<i64> { 452 let ParserMatchClass = MipsInvertedImmoperand; 453} 454 455class mem_generic : Operand<iPTR> { 456 let PrintMethod = "printMemOperand"; 457 let MIOperandInfo = (ops ptr_rc, simm16); 458 let EncoderMethod = "getMemEncoding"; 459 let ParserMatchClass = MipsMemAsmOperand; 460 let OperandType = "OPERAND_MEMORY"; 461} 462 463// Address operand 464def mem : mem_generic; 465 466// MSA specific address operand 467def mem_msa : mem_generic { 468 let MIOperandInfo = (ops ptr_rc, simm10); 469 let EncoderMethod = "getMSAMemEncoding"; 470} 471 472def mem_simm9 : mem_generic { 473 let MIOperandInfo = (ops ptr_rc, simm9); 474 let EncoderMethod = "getMemEncoding"; 475} 476 477def mem_simm11 : mem_generic { 478 let MIOperandInfo = (ops ptr_rc, simm11); 479 let EncoderMethod = "getMemEncoding"; 480 let ParserMatchClass = MipsMemSimm11AsmOperand; 481} 482 483def mem_simm16 : mem_generic { 484 let MIOperandInfo = (ops ptr_rc, simm16); 485 let EncoderMethod = "getMemEncoding"; 486 let ParserMatchClass = MipsMemSimm16AsmOperand; 487} 488 489def mem_ea : Operand<iPTR> { 490 let PrintMethod = "printMemOperandEA"; 491 let MIOperandInfo = (ops ptr_rc, simm16); 492 let EncoderMethod = "getMemEncoding"; 493 let OperandType = "OPERAND_MEMORY"; 494} 495 496def PtrRC : Operand<iPTR> { 497 let MIOperandInfo = (ops ptr_rc); 498 let DecoderMethod = "DecodePtrRegisterClass"; 499 let ParserMatchClass = GPR32AsmOperand; 500} 501 502// size operand of ext instruction 503def size_ext : Operand<i32> { 504 let EncoderMethod = "getSizeExtEncoding"; 505 let DecoderMethod = "DecodeExtSize"; 506} 507 508// size operand of ins instruction 509def size_ins : Operand<i32> { 510 let EncoderMethod = "getSizeInsEncoding"; 511 let DecoderMethod = "DecodeInsSize"; 512} 513 514// Transformation Function - get the lower 16 bits. 515def LO16 : SDNodeXForm<imm, [{ 516 return getImm(N, N->getZExtValue() & 0xFFFF); 517}]>; 518 519// Transformation Function - get the higher 16 bits. 520def HI16 : SDNodeXForm<imm, [{ 521 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 522}]>; 523 524// Plus 1. 525def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 526 527// Node immediate is zero (e.g. insve.d) 528def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 529 530// Node immediate fits as 16-bit sign extended on target immediate. 531// e.g. addi, andi 532def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 533 534// Node immediate fits as 16-bit sign extended on target immediate. 535// e.g. addi, andi 536def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 537 538// Node immediate fits as 15-bit sign extended on target immediate. 539// e.g. addi, andi 540def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 541 542// Node immediate fits as 16-bit zero extended on target immediate. 543// The LO16 param means that only the lower 16 bits of the node 544// immediate are caught. 545// e.g. addiu, sltiu 546def immZExt16 : PatLeaf<(imm), [{ 547 if (N->getValueType(0) == MVT::i32) 548 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 549 else 550 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 551}], LO16>; 552 553// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 554def immLow16Zero : PatLeaf<(imm), [{ 555 int64_t Val = N->getSExtValue(); 556 return isInt<32>(Val) && !(Val & 0xffff); 557}]>; 558 559// shamt field must fit in 5 bits. 560def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 561 562// True if (N + 1) fits in 16-bit field. 563def immSExt16Plus1 : PatLeaf<(imm), [{ 564 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 565}]>; 566 567// Mips Address Mode! SDNode frameindex could possibily be a match 568// since load and store instructions from stack used it. 569def addr : 570 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 571 572def addrRegImm : 573 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 574 575def addrRegReg : 576 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 577 578def addrDefault : 579 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 580 581def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; 582 583//===----------------------------------------------------------------------===// 584// Instructions specific format 585//===----------------------------------------------------------------------===// 586 587// Arithmetic and logical instructions with 3 register operands. 588class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 589 InstrItinClass Itin = NoItinerary, 590 SDPatternOperator OpNode = null_frag>: 591 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 592 !strconcat(opstr, "\t$rd, $rs, $rt"), 593 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 594 let isCommutable = isComm; 595 let isReMaterializable = 1; 596 let TwoOperandAliasConstraint = "$rd = $rs"; 597} 598 599// Arithmetic and logical instructions with 2 register operands. 600class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 601 InstrItinClass Itin = NoItinerary, 602 SDPatternOperator imm_type = null_frag, 603 SDPatternOperator OpNode = null_frag> : 604 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 605 !strconcat(opstr, "\t$rt, $rs, $imm16"), 606 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 607 Itin, FrmI, opstr> { 608 let isReMaterializable = 1; 609 let TwoOperandAliasConstraint = "$rs = $rt"; 610} 611 612// Arithmetic Multiply ADD/SUB 613class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 614 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 615 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 616 let Defs = [HI0, LO0]; 617 let Uses = [HI0, LO0]; 618 let isCommutable = isComm; 619} 620 621// Logical 622class LogicNOR<string opstr, RegisterOperand RO>: 623 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 624 !strconcat(opstr, "\t$rd, $rs, $rt"), 625 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 626 let isCommutable = 1; 627} 628 629// Shifts 630class shift_rotate_imm<string opstr, Operand ImmOpnd, 631 RegisterOperand RO, InstrItinClass itin, 632 SDPatternOperator OpNode = null_frag, 633 SDPatternOperator PF = null_frag> : 634 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 635 !strconcat(opstr, "\t$rd, $rt, $shamt"), 636 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 637 let TwoOperandAliasConstraint = "$rt = $rd"; 638} 639 640class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 641 SDPatternOperator OpNode = null_frag>: 642 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 643 !strconcat(opstr, "\t$rd, $rt, $rs"), 644 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 645 opstr>; 646 647// Load Upper Imediate 648class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 649 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 650 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 651 let hasSideEffects = 0; 652 let isReMaterializable = 1; 653} 654 655// Memory Load/Store 656class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 657 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 658 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 659 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 660 let DecoderMethod = "DecodeMem"; 661 let canFoldAsLoad = 1; 662 let mayLoad = 1; 663} 664 665class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 666 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 667 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 668 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 669 let DecoderMethod = "DecodeMem"; 670 let mayStore = 1; 671} 672 673// Load/Store Left/Right 674let canFoldAsLoad = 1 in 675class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 676 InstrItinClass Itin> : 677 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 678 !strconcat(opstr, "\t$rt, $addr"), 679 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 680 let DecoderMethod = "DecodeMem"; 681 string Constraints = "$src = $rt"; 682} 683 684class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 685 InstrItinClass Itin> : 686 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 687 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 688 let DecoderMethod = "DecodeMem"; 689} 690 691// COP2 Load/Store 692class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 693 SDPatternOperator OpNode= null_frag> : 694 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 695 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 696 let DecoderMethod = "DecodeFMem2"; 697 let mayLoad = 1; 698} 699 700class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 701 SDPatternOperator OpNode= null_frag> : 702 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 703 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 704 let DecoderMethod = "DecodeFMem2"; 705 let mayStore = 1; 706} 707 708// COP3 Load/Store 709class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 710 SDPatternOperator OpNode= null_frag> : 711 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 712 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 713 let DecoderMethod = "DecodeFMem3"; 714 let mayLoad = 1; 715} 716 717class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 718 SDPatternOperator OpNode= null_frag> : 719 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 720 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 721 let DecoderMethod = "DecodeFMem3"; 722 let mayStore = 1; 723} 724 725// Conditional Branch 726class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 727 RegisterOperand RO, bit DelaySlot = 1> : 728 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 729 !strconcat(opstr, "\t$rs, $rt, $offset"), 730 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 731 FrmI, opstr> { 732 let isBranch = 1; 733 let isTerminator = 1; 734 let hasDelaySlot = DelaySlot; 735 let Defs = [AT]; 736} 737 738class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 739 RegisterOperand RO, bit DelaySlot = 1> : 740 InstSE<(outs), (ins RO:$rs, opnd:$offset), 741 !strconcat(opstr, "\t$rs, $offset"), 742 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, 743 FrmI, opstr> { 744 let isBranch = 1; 745 let isTerminator = 1; 746 let hasDelaySlot = DelaySlot; 747 let Defs = [AT]; 748} 749 750// SetCC 751class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 752 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 753 !strconcat(opstr, "\t$rd, $rs, $rt"), 754 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 755 II_SLT_SLTU, FrmR, opstr>; 756 757class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 758 RegisterOperand RO>: 759 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 760 !strconcat(opstr, "\t$rt, $rs, $imm16"), 761 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 762 II_SLTI_SLTIU, FrmI, opstr>; 763 764// Jump 765class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 766 SDPatternOperator targetoperator, string bopstr> : 767 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 768 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> { 769 let isTerminator=1; 770 let isBarrier=1; 771 let hasDelaySlot = 1; 772 let DecoderMethod = "DecodeJumpTarget"; 773 let Defs = [AT]; 774} 775 776// Unconditional branch 777class UncondBranch<Instruction BEQInst> : 778 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 779 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 780 let isBranch = 1; 781 let isTerminator = 1; 782 let isBarrier = 1; 783 let hasDelaySlot = 1; 784 let AdditionalPredicates = [RelocPIC]; 785 let Defs = [AT]; 786} 787 788// Base class for indirect branch and return instruction classes. 789let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 790class JumpFR<string opstr, RegisterOperand RO, 791 SDPatternOperator operator = null_frag>: 792 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, 793 FrmR, opstr>; 794 795// Indirect branch 796class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> { 797 let isBranch = 1; 798 let isIndirectBranch = 1; 799} 800 801// Jump and Link (Call) 802let isCall=1, hasDelaySlot=1, Defs = [RA] in { 803 class JumpLink<string opstr, DAGOperand opnd> : 804 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 805 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> { 806 let DecoderMethod = "DecodeJumpTarget"; 807 } 808 809 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 810 Register RetReg, RegisterOperand ResRO = RO>: 811 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 812 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 813 814 class JumpLinkReg<string opstr, RegisterOperand RO>: 815 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 816 [], IIBranch, FrmR>; 817 818 class BGEZAL_FT<string opstr, DAGOperand opnd, 819 RegisterOperand RO, bit DelaySlot = 1> : 820 InstSE<(outs), (ins RO:$rs, opnd:$offset), 821 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> { 822 let hasDelaySlot = DelaySlot; 823 } 824 825} 826 827let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 828 hasExtraSrcRegAllocReq = 1, Defs = [AT] in { 829 class TailCall<Instruction JumpInst> : 830 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>, 831 PseudoInstExpansion<(JumpInst jmptarget:$target)>; 832 833 class TailCallReg<RegisterOperand RO, Instruction JRInst, 834 RegisterOperand ResRO = RO> : 835 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>, 836 PseudoInstExpansion<(JRInst ResRO:$rs)>; 837} 838 839class BAL_BR_Pseudo<Instruction RealInst> : 840 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 841 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 842 let isBranch = 1; 843 let isTerminator = 1; 844 let isBarrier = 1; 845 let hasDelaySlot = 1; 846 let Defs = [RA]; 847} 848 849// Syscall 850class SYS_FT<string opstr> : 851 InstSE<(outs), (ins uimm20:$code_), 852 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; 853// Break 854class BRK_FT<string opstr> : 855 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 856 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, 857 FrmOther, opstr>; 858 859// (D)Eret 860class ER_FT<string opstr> : 861 InstSE<(outs), (ins), 862 opstr, [], NoItinerary, FrmOther, opstr>; 863 864// Interrupts 865class DEI_FT<string opstr, RegisterOperand RO> : 866 InstSE<(outs RO:$rt), (ins), 867 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>; 868 869// Wait 870class WAIT_FT<string opstr> : 871 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>; 872 873// Sync 874let hasSideEffects = 1 in 875class SYNC_FT<string opstr> : 876 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 877 NoItinerary, FrmOther, opstr>; 878 879class SYNCI_FT<string opstr> : 880 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], 881 NoItinerary, FrmOther, opstr> { 882 let hasSideEffects = 1; 883 let DecoderMethod = "DecodeSyncI"; 884} 885 886let hasSideEffects = 1 in 887class TEQ_FT<string opstr, RegisterOperand RO> : 888 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 889 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, 890 FrmI, opstr>; 891 892class TEQI_FT<string opstr, RegisterOperand RO> : 893 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 894 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; 895// Mul, Div 896class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 897 list<Register> DefRegs> : 898 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 899 itin, FrmR, opstr> { 900 let isCommutable = 1; 901 let Defs = DefRegs; 902 let hasSideEffects = 0; 903} 904 905// Pseudo multiply/divide instruction with explicit accumulator register 906// operands. 907class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 908 SDPatternOperator OpNode, InstrItinClass Itin, 909 bit IsComm = 1, bit HasSideEffects = 0, 910 bit UsesCustomInserter = 0> : 911 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 912 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 913 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 914 let isCommutable = IsComm; 915 let hasSideEffects = HasSideEffects; 916 let usesCustomInserter = UsesCustomInserter; 917} 918 919// Pseudo multiply add/sub instruction with explicit accumulator register 920// operands. 921class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 922 InstrItinClass itin> 923 : PseudoSE<(outs ACC64:$ac), 924 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 925 [(set ACC64:$ac, 926 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 927 itin>, 928 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 929 string Constraints = "$acin = $ac"; 930} 931 932class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 933 list<Register> DefRegs> : 934 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 935 [], itin, FrmR, opstr> { 936 let Defs = DefRegs; 937} 938 939// Move from Hi/Lo 940class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 941 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 942 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 943 944class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 945 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 946 FrmR, opstr> { 947 let Uses = [UseReg]; 948 let hasSideEffects = 0; 949} 950 951class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 952 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 953 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 954 II_MTHI_MTLO>; 955 956class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 957 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 958 FrmR, opstr> { 959 let Defs = DefRegs; 960 let hasSideEffects = 0; 961} 962 963class EffectiveAddress<string opstr, RegisterOperand RO> : 964 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 965 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI, 966 !strconcat(opstr, "_lea")> { 967 let isCodeGenOnly = 1; 968 let DecoderMethod = "DecodeMem"; 969} 970 971// Count Leading Ones/Zeros in Word 972class CountLeading0<string opstr, RegisterOperand RO>: 973 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 974 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>; 975 976class CountLeading1<string opstr, RegisterOperand RO>: 977 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 978 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>; 979 980// Sign Extend in Register. 981class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 982 InstrItinClass itin> : 983 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 984 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 985 986// Subword Swap 987class SubwordSwap<string opstr, RegisterOperand RO>: 988 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 989 NoItinerary, FrmR, opstr> { 990 let hasSideEffects = 0; 991} 992 993// Read Hardware 994class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 995 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 996 II_RDHWR, FrmR, "rdhwr">; 997 998// Ext and Ins 999class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1000 SDPatternOperator Op = null_frag>: 1001 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 1002 !strconcat(opstr, " $rt, $rs, $pos, $size"), 1003 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 1004 FrmR, opstr>, ISA_MIPS32R2; 1005 1006class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1007 SDPatternOperator Op = null_frag>: 1008 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 1009 !strconcat(opstr, " $rt, $rs, $pos, $size"), 1010 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 1011 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 { 1012 let Constraints = "$src = $rt"; 1013} 1014 1015// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 1016class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 1017 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 1018 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 1019 1020// Atomic Compare & Swap. 1021class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 1022 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 1023 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 1024 1025class LLBase<string opstr, RegisterOperand RO> : 1026 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 1027 [], NoItinerary, FrmI> { 1028 let DecoderMethod = "DecodeMem"; 1029 let mayLoad = 1; 1030} 1031 1032class SCBase<string opstr, RegisterOperand RO> : 1033 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 1034 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 1035 let DecoderMethod = "DecodeMem"; 1036 let mayStore = 1; 1037 let Constraints = "$rt = $dst"; 1038} 1039 1040class MFC3OP<string asmstr, RegisterOperand RO> : 1041 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 1042 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 1043 1044class TrapBase<Instruction RealInst> 1045 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 1046 PseudoInstExpansion<(RealInst 0, 0)> { 1047 let isBarrier = 1; 1048 let isTerminator = 1; 1049 let isCodeGenOnly = 1; 1050} 1051 1052//===----------------------------------------------------------------------===// 1053// Pseudo instructions 1054//===----------------------------------------------------------------------===// 1055 1056// Return RA. 1057let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 1058def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 1059 1060let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1061def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 1062 [(callseq_start timm:$amt)]>; 1063def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1064 [(callseq_end timm:$amt1, timm:$amt2)]>; 1065} 1066 1067let usesCustomInserter = 1 in { 1068 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 1069 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 1070 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 1071 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 1072 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 1073 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 1074 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 1075 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 1076 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 1077 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 1078 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 1079 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 1080 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 1081 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 1082 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 1083 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 1084 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 1085 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 1086 1087 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 1088 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 1089 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 1090 1091 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 1092 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 1093 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 1094} 1095 1096/// Pseudo instructions for loading and storing accumulator registers. 1097let isPseudo = 1, isCodeGenOnly = 1 in { 1098 def LOAD_ACC64 : Load<"", ACC64>; 1099 def STORE_ACC64 : Store<"", ACC64>; 1100} 1101 1102// We need these two pseudo instructions to avoid offset calculation for long 1103// branches. See the comment in file MipsLongBranch.cpp for detailed 1104// explanation. 1105 1106// Expands to: lui $dst, %hi($tgt - $baltgt) 1107def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 1108 (ins brtarget:$tgt, brtarget:$baltgt), []>; 1109 1110// Expands to: addiu $dst, $src, %lo($tgt - $baltgt) 1111def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 1112 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 1113 1114//===----------------------------------------------------------------------===// 1115// Instruction definition 1116//===----------------------------------------------------------------------===// 1117//===----------------------------------------------------------------------===// 1118// MipsI Instructions 1119//===----------------------------------------------------------------------===// 1120 1121/// Arithmetic Instructions (ALU Immediate) 1122let AdditionalPredicates = [NotInMicroMips] in { 1123def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, 1124 add>, ADDI_FM<0x9>, IsAsCheapAsAMove; 1125} 1126def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, 1127 ISA_MIPS1_NOT_32R6_64R6; 1128def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 1129 SLTI_FM<0xa>; 1130def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 1131 SLTI_FM<0xb>; 1132let AdditionalPredicates = [NotInMicroMips] in { 1133def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, 1134 and>, ADDI_FM<0xc>; 1135} 1136def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, 1137 or>, 1138 ADDI_FM<0xd>; 1139def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, 1140 xor>, 1141 ADDI_FM<0xe>; 1142def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 1143 1144/// Arithmetic Instructions (3-Operand, R-Type) 1145def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 1146 ADD_FM<0, 0x21>; 1147def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 1148 ADD_FM<0, 0x23>; 1149let Defs = [HI0, LO0] in 1150def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 1151 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; 1152def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 1153def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 1154def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 1155def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 1156def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 1157 ADD_FM<0, 0x24>; 1158def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 1159 ADD_FM<0, 0x25>; 1160def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 1161 ADD_FM<0, 0x26>; 1162def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 1163 1164/// Shift Instructions 1165let AdditionalPredicates = [NotInMicroMips] in { 1166def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 1167 immZExt5>, SRA_FM<0, 0>; 1168def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 1169 immZExt5>, SRA_FM<2, 0>; 1170} 1171def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 1172 immZExt5>, SRA_FM<3, 0>; 1173def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 1174 SRLV_FM<4, 0>; 1175def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 1176 SRLV_FM<6, 0>; 1177def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 1178 SRLV_FM<7, 0>; 1179 1180// Rotate Instructions 1181def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 1182 immZExt5>, 1183 SRA_FM<2, 1>, ISA_MIPS32R2; 1184def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 1185 SRLV_FM<6, 1>, ISA_MIPS32R2; 1186 1187/// Load and Store Instructions 1188/// aligned 1189def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; 1190def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, 1191 LW_FM<0x24>; 1192def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, 1193 LW_FM<0x21>; 1194def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; 1195def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 1196 LW_FM<0x23>; 1197def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; 1198def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; 1199def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; 1200 1201/// load/store left/right 1202let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1203 AdditionalPredicates = [NotInMicroMips] in { 1204def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 1205 ISA_MIPS1_NOT_32R6_64R6; 1206def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 1207 ISA_MIPS1_NOT_32R6_64R6; 1208def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 1209 ISA_MIPS1_NOT_32R6_64R6; 1210def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 1211 ISA_MIPS1_NOT_32R6_64R6; 1212} 1213 1214// COP2 Memory Instructions 1215def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, 1216 ISA_MIPS1_NOT_32R6_64R6; 1217def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, 1218 ISA_MIPS1_NOT_32R6_64R6; 1219def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, 1220 ISA_MIPS2_NOT_32R6_64R6; 1221def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, 1222 ISA_MIPS2_NOT_32R6_64R6; 1223 1224// COP3 Memory Instructions 1225let DecoderNamespace = "COP3_" in { 1226 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; 1227 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; 1228 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, 1229 ISA_MIPS2; 1230 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, 1231 ISA_MIPS2; 1232} 1233 1234def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; 1235def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; 1236 1237def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; 1238def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; 1239def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2; 1240def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2; 1241def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2; 1242def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2; 1243 1244def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, 1245 ISA_MIPS2_NOT_32R6_64R6; 1246def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, 1247 ISA_MIPS2_NOT_32R6_64R6; 1248def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, 1249 ISA_MIPS2_NOT_32R6_64R6; 1250def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, 1251 ISA_MIPS2_NOT_32R6_64R6; 1252def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, 1253 ISA_MIPS2_NOT_32R6_64R6; 1254def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, 1255 ISA_MIPS2_NOT_32R6_64R6; 1256 1257def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; 1258def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; 1259def TRAP : TrapBase<BREAK>; 1260def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; 1261 1262def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; 1263def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; 1264 1265def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; 1266def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; 1267 1268let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1269 AdditionalPredicates = [NotInMicroMips] in { 1270def WAIT : WAIT_FT<"wait">, WAIT_FM; 1271 1272/// Load-linked, Store-conditional 1273def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6; 1274def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6; 1275} 1276 1277/// Jump and Branch Instructions 1278def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 1279 AdditionalRequires<[RelocStatic]>, IsBranch; 1280def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; 1281def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; 1282def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>, 1283 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; 1284def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; 1285def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>, 1286 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; 1287def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 1288 BGEZ_FM<1, 1>; 1289def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>, 1290 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; 1291def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1292 BGEZ_FM<7, 0>; 1293def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>, 1294 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; 1295def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 1296 BGEZ_FM<6, 0>; 1297def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>, 1298 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; 1299def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1300 BGEZ_FM<1, 0>; 1301def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>, 1302 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; 1303def B : UncondBranch<BEQ>; 1304 1305def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; 1306let AdditionalPredicates = [NotInMicroMips] in { 1307 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1308 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1309} 1310 1311// FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32. 1312def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6; 1313def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, 1314 ISA_MIPS1_NOT_32R6_64R6; 1315def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>, 1316 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; 1317def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, 1318 ISA_MIPS1_NOT_32R6_64R6; 1319def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>, 1320 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; 1321def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1322def TAILCALL : TailCall<J>; 1323def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; 1324 1325// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 1326// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 1327class PseudoIndirectBranchBase<RegisterOperand RO> : 1328 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> { 1329 let isTerminator=1; 1330 let isBarrier=1; 1331 let hasDelaySlot = 1; 1332 let isBranch = 1; 1333 let isIndirectBranch = 1; 1334} 1335 1336def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>; 1337 1338// Return instructions are matched as a RetRA instruction, then ar expanded 1339// into PseudoReturn/PseudoReturn64 after register allocation. Finally, 1340// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 1341// ISA. 1342class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs), 1343 [], IIBranch> { 1344 let isTerminator = 1; 1345 let isBarrier = 1; 1346 let hasDelaySlot = 1; 1347 let isReturn = 1; 1348 let isCodeGenOnly = 1; 1349 let hasCtrlDep = 1; 1350 let hasExtraSrcRegAllocReq = 1; 1351} 1352 1353def PseudoReturn : PseudoReturnBase<GPR32Opnd>; 1354 1355// Exception handling related node and instructions. 1356// The conversion sequence is: 1357// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1358// MIPSeh_return -> (stack change + indirect branch) 1359// 1360// MIPSeh_return takes the place of regular return instruction 1361// but takes two arguments (V1, V0) which are used for storing 1362// the offset and return address respectively. 1363def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1364 1365def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1366 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1367 1368let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1369 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1370 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1371 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1372 GPR64:$dst), 1373 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1374} 1375 1376/// Multiply and Divide Instructions. 1377def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 1378 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; 1379def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 1380 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; 1381def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 1382 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; 1383def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 1384 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; 1385 1386def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, 1387 ISA_MIPS1_NOT_32R6_64R6; 1388def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, 1389 ISA_MIPS1_NOT_32R6_64R6; 1390let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1391 AdditionalPredicates = [NotInMicroMips] in { 1392def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, 1393 ISA_MIPS1_NOT_32R6_64R6; 1394def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, 1395 ISA_MIPS1_NOT_32R6_64R6; 1396} 1397 1398/// Sign Ext In Register Instructions. 1399def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 1400 SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 1401def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 1402 SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 1403 1404/// Count Leading 1405def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, 1406 ISA_MIPS32_NOT_32R6_64R6; 1407def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, 1408 ISA_MIPS32_NOT_32R6_64R6; 1409 1410/// Word Swap Bytes Within Halfwords 1411def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; 1412 1413/// No operation. 1414def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1415 1416// FrameIndexes are legalized when they are operands from load/store 1417// instructions. The same not happens for stack address copies, so an 1418// add op with mem ComplexPattern is used and the stack address copy 1419// can be matched. It's similar to Sparc LEA_ADDRi 1420def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1421 1422// MADD*/MSUB* 1423def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, 1424 ISA_MIPS32_NOT_32R6_64R6; 1425def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, 1426 ISA_MIPS32_NOT_32R6_64R6; 1427def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, 1428 ISA_MIPS32_NOT_32R6_64R6; 1429def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, 1430 ISA_MIPS32_NOT_32R6_64R6; 1431 1432let AdditionalPredicates = [NotDSP] in { 1433def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, 1434 ISA_MIPS1_NOT_32R6_64R6; 1435def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, 1436 ISA_MIPS1_NOT_32R6_64R6; 1437def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6; 1438def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6; 1439def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6; 1440def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, 1441 ISA_MIPS32_NOT_32R6_64R6; 1442def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, 1443 ISA_MIPS32_NOT_32R6_64R6; 1444def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, 1445 ISA_MIPS32_NOT_32R6_64R6; 1446def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, 1447 ISA_MIPS32_NOT_32R6_64R6; 1448} 1449 1450def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 1451 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1452def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 1453 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1454 1455def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1456 1457def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1458def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1459 1460/// Move Control Registers From/To CPU Registers 1461def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; 1462def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; 1463def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1464def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1465 1466class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1467 FrmOther, asmstr>; 1468def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>; 1469def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>; 1470def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2; 1471 1472// JR_HB and JALR_HB are defined here using the new style naming 1473// scheme because some of this code is shared with Mips32r6InstrInfo.td 1474// and because of that it doesn't follow the naming convention of the 1475// rest of the file. To avoid a mixture of old vs new style, the new 1476// style was chosen. 1477class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1478 dag OutOperandList = (outs); 1479 dag InOperandList = (ins GPROpnd:$rs); 1480 string AsmString = !strconcat(instr_asm, "\t$rs"); 1481 list<dag> Pattern = []; 1482} 1483 1484class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1485 dag OutOperandList = (outs GPROpnd:$rd); 1486 dag InOperandList = (ins GPROpnd:$rs); 1487 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 1488 list<dag> Pattern = []; 1489} 1490 1491class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1492 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 1493 let isBranch=1; 1494 let isIndirectBranch=1; 1495 let hasDelaySlot=1; 1496 let isTerminator=1; 1497 let isBarrier=1; 1498} 1499 1500class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1501 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> { 1502 let isIndirectBranch=1; 1503 let hasDelaySlot=1; 1504} 1505 1506class JR_HB_ENC : JR_HB_FM<8>; 1507class JALR_HB_ENC : JALR_HB_FM<9>; 1508 1509def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; 1510def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; 1511 1512class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1513 FrmOther, asmstr>; 1514def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; 1515def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; 1516def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; 1517def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; 1518 1519class CacheOp<string instr_asm, Operand MemOpnd> : 1520 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), 1521 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, 1522 instr_asm> { 1523 let DecoderMethod = "DecodeCacheOp"; 1524} 1525 1526def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>, 1527 INSN_MIPS3_32_NOT_32R6_64R6; 1528def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>, 1529 INSN_MIPS3_32_NOT_32R6_64R6; 1530 1531//===----------------------------------------------------------------------===// 1532// Instruction aliases 1533//===----------------------------------------------------------------------===// 1534def : MipsInstAlias<"move $dst, $src", 1535 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1536 GPR_32 { 1537 let AdditionalPredicates = [NotInMicroMips]; 1538} 1539def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, 1540 ISA_MIPS1_NOT_32R6_64R6; 1541def : MipsInstAlias<"addu $rs, $rt, $imm", 1542 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1543def : MipsInstAlias<"addu $rs, $imm", 1544 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; 1545def : MipsInstAlias<"add $rs, $rt, $imm", 1546 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>, 1547 ISA_MIPS1_NOT_32R6_64R6; 1548def : MipsInstAlias<"add $rs, $imm", 1549 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>, 1550 ISA_MIPS1_NOT_32R6_64R6; 1551def : MipsInstAlias<"and $rs, $rt, $imm", 1552 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1553def : MipsInstAlias<"and $rs, $imm", 1554 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; 1555def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1556let Predicates = [NotInMicroMips] in { 1557def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1558} 1559def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1560def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1561def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; 1562def : MipsInstAlias<"not $rt, $rs", 1563 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1564def : MipsInstAlias<"neg $rt, $rs", 1565 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1566def : MipsInstAlias<"negu $rt", 1567 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; 1568def : MipsInstAlias<"negu $rt, $rs", 1569 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1570def : MipsInstAlias<"slt $rs, $rt, $imm", 1571 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1572def : MipsInstAlias<"sltu $rt, $rs, $imm", 1573 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; 1574def : MipsInstAlias<"xor $rs, $rt, $imm", 1575 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1576def : MipsInstAlias<"or $rs, $rt, $imm", 1577 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1578def : MipsInstAlias<"or $rs, $imm", 1579 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; 1580def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1581def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1582def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1583def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1584def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1585def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1586def : MipsInstAlias<"bnez $rs,$offset", 1587 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1588def : MipsInstAlias<"beqz $rs,$offset", 1589 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1590def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; 1591 1592def : MipsInstAlias<"break", (BREAK 0, 0), 1>; 1593def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1594def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; 1595def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; 1596 1597def : MipsInstAlias<"teq $rs, $rt", 1598 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1599def : MipsInstAlias<"tge $rs, $rt", 1600 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1601def : MipsInstAlias<"tgeu $rs, $rt", 1602 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1603def : MipsInstAlias<"tlt $rs, $rt", 1604 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1605def : MipsInstAlias<"tltu $rs, $rt", 1606 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1607def : MipsInstAlias<"tne $rs, $rt", 1608 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1609 1610def : MipsInstAlias<"sll $rd, $rt, $rs", 1611 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1612def : MipsInstAlias<"sub, $rd, $rs, $imm", 1613 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 1614 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; 1615def : MipsInstAlias<"sub $rs, $imm", 1616 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 1617 0>, ISA_MIPS1_NOT_32R6_64R6; 1618def : MipsInstAlias<"subu, $rd, $rs, $imm", 1619 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 1620 InvertedImOperand:$imm), 0>; 1621def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 1622 InvertedImOperand:$imm), 0>; 1623def : MipsInstAlias<"sra $rd, $rt, $rs", 1624 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1625def : MipsInstAlias<"srl $rd, $rt, $rs", 1626 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1627def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; 1628def : MipsInstAlias<"sync", 1629 (SYNC 0), 1>, ISA_MIPS2; 1630//===----------------------------------------------------------------------===// 1631// Assembler Pseudo Instructions 1632//===----------------------------------------------------------------------===// 1633 1634class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1635 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1636 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1637def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1638 1639class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1640 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1641 !strconcat(instr_asm, "\t$rt, $addr")> ; 1642def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1643 1644class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1645 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1646 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1647def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1648 1649//===----------------------------------------------------------------------===// 1650// Arbitrary patterns that map to one or more instructions 1651//===----------------------------------------------------------------------===// 1652 1653// Load/store pattern templates. 1654class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1655 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1656 1657class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1658 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1659 1660// Small immediates 1661let AdditionalPredicates = [NotInMicroMips] in { 1662def : MipsPat<(i32 immSExt16:$in), 1663 (ADDiu ZERO, imm:$in)>; 1664def : MipsPat<(i32 immZExt16:$in), 1665 (ORi ZERO, imm:$in)>; 1666} 1667def : MipsPat<(i32 immLow16Zero:$in), 1668 (LUi (HI16 imm:$in))>; 1669 1670// Arbitrary immediates 1671def : MipsPat<(i32 imm:$imm), 1672 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1673 1674// Carry MipsPatterns 1675def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1676 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1677let AdditionalPredicates = [NotDSP] in { 1678 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1679 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1680 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1681 (ADDiu GPR32:$src, imm:$imm)>; 1682} 1683 1684// Support multiplication for pre-Mips32 targets that don't have 1685// the MUL instruction. 1686def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs), 1687 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>, 1688 ISA_MIPS1_NOT_32R6_64R6; 1689 1690// SYNC 1691def : MipsPat<(MipsSync (i32 immz)), 1692 (SYNC 0)>, ISA_MIPS2; 1693 1694// Call 1695def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1696 (JAL tglobaladdr:$dst)>; 1697def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1698 (JAL texternalsym:$dst)>; 1699//def : MipsPat<(MipsJmpLink GPR32:$dst), 1700// (JALR GPR32:$dst)>; 1701 1702// Tail call 1703def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1704 (TAILCALL tglobaladdr:$dst)>; 1705def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1706 (TAILCALL texternalsym:$dst)>; 1707// hi/lo relocs 1708def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1709def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1710def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1711def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1712def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1713def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1714 1715def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1716def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1717def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1718def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1719def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1720def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1721 1722def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1723 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1724def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1725 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1726def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1727 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1728def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1729 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1730def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1731 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1732 1733// gp_rel relocs 1734def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1735 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1736def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1737 (ADDiu GPR32:$gp, tconstpool:$in)>; 1738 1739// wrapper_pic 1740class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1741 MipsPat<(MipsWrapper RC:$gp, node:$in), 1742 (ADDiuOp RC:$gp, node:$in)>; 1743 1744def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1745def : WrapperPat<tconstpool, ADDiu, GPR32>; 1746def : WrapperPat<texternalsym, ADDiu, GPR32>; 1747def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1748def : WrapperPat<tjumptable, ADDiu, GPR32>; 1749def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1750 1751// Mips does not have "not", so we expand our way 1752def : MipsPat<(not GPR32:$in), 1753 (NOR GPR32Opnd:$in, ZERO)>; 1754 1755// extended loads 1756def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1757def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1758def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1759 1760// peepholes 1761def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1762 1763// brcond patterns 1764multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1765 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1766 Instruction SLTiuOp, Register ZEROReg> { 1767def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1768 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1769def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1770 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1771 1772def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1773 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1774def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1775 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1776def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1777 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1778def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1779 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1780def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1781 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1782def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1783 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1784 1785def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1786 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1787def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1788 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1789 1790def : MipsPat<(brcond RC:$cond, bb:$dst), 1791 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1792} 1793 1794defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1795 1796def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1797 (BLEZ i32:$lhs, bb:$dst)>; 1798def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1799 (BGEZ i32:$lhs, bb:$dst)>; 1800 1801// setcc patterns 1802multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1803 Instruction SLTuOp, Register ZEROReg> { 1804 def : MipsPat<(seteq RC:$lhs, 0), 1805 (SLTiuOp RC:$lhs, 1)>; 1806 def : MipsPat<(setne RC:$lhs, 0), 1807 (SLTuOp ZEROReg, RC:$lhs)>; 1808 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1809 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1810 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1811 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1812} 1813 1814multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1815 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1816 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1817 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1818 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1819} 1820 1821multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1822 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1823 (SLTOp RC:$rhs, RC:$lhs)>; 1824 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1825 (SLTuOp RC:$rhs, RC:$lhs)>; 1826} 1827 1828multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1829 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1830 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1831 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1832 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1833} 1834 1835multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1836 Instruction SLTiuOp> { 1837 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1838 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1839 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1840 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1841} 1842 1843defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1844defm : SetlePats<GPR32, SLT, SLTu>; 1845defm : SetgtPats<GPR32, SLT, SLTu>; 1846defm : SetgePats<GPR32, SLT, SLTu>; 1847defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1848 1849// bswap pattern 1850def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1851 1852// Load halfword/word patterns. 1853let AddedComplexity = 40 in { 1854 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1855 def : LoadRegImmPat<LH, i32, sextloadi16>; 1856 def : LoadRegImmPat<LW, i32, load>; 1857} 1858 1859//===----------------------------------------------------------------------===// 1860// Floating Point Support 1861//===----------------------------------------------------------------------===// 1862 1863include "MipsInstrFPU.td" 1864include "Mips64InstrInfo.td" 1865include "MipsCondMov.td" 1866 1867include "Mips32r6InstrInfo.td" 1868include "Mips64r6InstrInfo.td" 1869 1870// 1871// Mips16 1872 1873include "Mips16InstrFormats.td" 1874include "Mips16InstrInfo.td" 1875 1876// DSP 1877include "MipsDSPInstrFormats.td" 1878include "MipsDSPInstrInfo.td" 1879 1880// MSA 1881include "MipsMSAInstrFormats.td" 1882include "MipsMSAInstrInfo.td" 1883 1884// Micromips 1885include "MicroMipsInstrFormats.td" 1886include "MicroMipsInstrInfo.td" 1887include "MicroMipsInstrFPU.td" 1888