1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Contains the definition of a TargetInstrInfo class that is common 12 /// to all AMD GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H 17 #define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H 18 19 #include "AMDGPURegisterInfo.h" 20 #include "llvm/Target/TargetInstrInfo.h" 21 #include <map> 22 23 #define GET_INSTRINFO_HEADER 24 #define GET_INSTRINFO_ENUM 25 #define GET_INSTRINFO_OPERAND_ENUM 26 #include "AMDGPUGenInstrInfo.inc" 27 28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT 29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT 30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE 31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE 32 33 namespace llvm { 34 35 class AMDGPUSubtarget; 36 class MachineFunction; 37 class MachineInstr; 38 class MachineInstrBuilder; 39 40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { 41 private: 42 const AMDGPURegisterInfo RI; 43 virtual void anchor(); 44 protected: 45 const AMDGPUSubtarget &ST; 46 public: 47 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st); 48 49 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; 50 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 52 unsigned &DstReg, unsigned &SubIdx) const override; 53 54 unsigned isLoadFromStackSlot(const MachineInstr *MI, 55 int &FrameIndex) const override; 56 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 57 int &FrameIndex) const override; 58 bool hasLoadFromStackSlot(const MachineInstr *MI, 59 const MachineMemOperand *&MMO, 60 int &FrameIndex) const override; 61 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 62 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 63 int &FrameIndex) const; 64 bool hasStoreFromStackSlot(const MachineInstr *MI, 65 const MachineMemOperand *&MMO, 66 int &FrameIndex) const; 67 68 MachineInstr * 69 convertToThreeAddress(MachineFunction::iterator &MFI, 70 MachineBasicBlock::iterator &MBBI, 71 LiveVariables *LV) const override; 72 73 74 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 75 76 void storeRegToStackSlot(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MI, 78 unsigned SrcReg, bool isKill, int FrameIndex, 79 const TargetRegisterClass *RC, 80 const TargetRegisterInfo *TRI) const override; 81 void loadRegFromStackSlot(MachineBasicBlock &MBB, 82 MachineBasicBlock::iterator MI, 83 unsigned DestReg, int FrameIndex, 84 const TargetRegisterClass *RC, 85 const TargetRegisterInfo *TRI) const override; 86 87 protected: 88 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 89 MachineInstr *MI, 90 const SmallVectorImpl<unsigned> &Ops, 91 int FrameIndex) const override; 92 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 93 MachineInstr *MI, 94 const SmallVectorImpl<unsigned> &Ops, 95 MachineInstr *LoadMI) const override; 96 public: 97 /// \returns the smallest register index that will be accessed by an indirect 98 /// read or write or -1 if indirect addressing is not used by this program. 99 int getIndirectIndexBegin(const MachineFunction &MF) const; 100 101 /// \returns the largest register index that will be accessed by an indirect 102 /// read or write or -1 if indirect addressing is not used by this program. 103 int getIndirectIndexEnd(const MachineFunction &MF) const; 104 105 bool canFoldMemoryOperand(const MachineInstr *MI, 106 const SmallVectorImpl<unsigned> &Ops) const override; 107 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 108 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 109 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 110 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 111 SmallVectorImpl<SDNode *> &NewNodes) const override; 112 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 113 bool UnfoldLoad, bool UnfoldStore, 114 unsigned *LoadRegIndex = nullptr) const override; 115 116 bool enableClusterLoads() const override; 117 118 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 119 int64_t Offset1, int64_t Offset2, 120 unsigned NumLoads) const override; 121 122 bool 123 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 124 void insertNoop(MachineBasicBlock &MBB, 125 MachineBasicBlock::iterator MI) const override; 126 bool isPredicated(const MachineInstr *MI) const override; 127 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 128 const SmallVectorImpl<MachineOperand> &Pred2) const override; 129 bool DefinesPredicate(MachineInstr *MI, 130 std::vector<MachineOperand> &Pred) const override; 131 bool isPredicable(MachineInstr *MI) const override; 132 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 133 134 // Helper functions that check the opcode for status information 135 bool isRegisterStore(const MachineInstr &MI) const; 136 bool isRegisterLoad(const MachineInstr &MI) const; 137 138 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction. 139 /// Return -1 if the target-specific opcode for the pseudo instruction does 140 /// not exist. If Opcode is not a pseudo instruction, this is identity. 141 int pseudoToMCOpcode(int Opcode) const; 142 143 /// \brief Return the descriptor of the target-specific machine instruction 144 /// that corresponds to the specified pseudo or native opcode. getMCOpcodeFromPseudo(unsigned Opcode)145 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const { 146 return get(pseudoToMCOpcode(Opcode)); 147 } 148 149 //===---------------------------------------------------------------------===// 150 // Pure virtual funtions to be implemented by sub-classes. 151 //===---------------------------------------------------------------------===// 152 153 virtual bool isMov(unsigned opcode) const = 0; 154 155 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and 156 /// \p Channel 157 /// 158 /// We model indirect addressing using a virtual address space that can be 159 /// accesed with loads and stores. The "Indirect Address" is the memory 160 /// address in this virtual address space that maps to the given \p RegIndex 161 /// and \p Channel. 162 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 163 unsigned Channel) const = 0; 164 165 /// \returns The register class to be used for loading and storing values 166 /// from an "Indirect Address" . 167 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0; 168 169 /// \brief Build instruction(s) for an indirect register write. 170 /// 171 /// \returns The instruction that performs the indirect register write 172 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 173 MachineBasicBlock::iterator I, 174 unsigned ValueReg, unsigned Address, 175 unsigned OffsetReg) const = 0; 176 177 /// \brief Build instruction(s) for an indirect register read. 178 /// 179 /// \returns The instruction that performs the indirect register read 180 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 181 MachineBasicBlock::iterator I, 182 unsigned ValueReg, unsigned Address, 183 unsigned OffsetReg) const = 0; 184 185 /// \brief Build a MOV instruction. 186 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 187 MachineBasicBlock::iterator I, 188 unsigned DstReg, unsigned SrcReg) const = 0; 189 190 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the 191 /// equivalent opcode that writes \p Channels Channels. 192 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; 193 194 }; 195 196 namespace AMDGPU { 197 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 198 } // End namespace AMDGPU 199 200 } // End llvm namespace 201 202 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) 203 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) 204 205 #endif 206