1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
17 #include "AMDGPU.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "AMDGPUGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 
33 class SIMachineFunctionInfo;
34 
35 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
36 
37 public:
38   enum Generation {
39     R600 = 0,
40     R700,
41     EVERGREEN,
42     NORTHERN_ISLANDS,
43     SOUTHERN_ISLANDS,
44     SEA_ISLANDS,
45     VOLCANIC_ISLANDS,
46   };
47 
48   enum {
49     FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
50   };
51 
52 private:
53   std::string DevName;
54   bool Is64bit;
55   bool DumpCode;
56   bool R600ALUInst;
57   bool HasVertexCache;
58   short TexVTXClauseSize;
59   Generation Gen;
60   bool FP64;
61   bool FP64Denormals;
62   bool FP32Denormals;
63   bool CaymanISA;
64   bool FlatAddressSpace;
65   bool EnableIRStructurizer;
66   bool EnablePromoteAlloca;
67   bool EnableIfCvt;
68   bool EnableLoadStoreOpt;
69   unsigned WavefrontSize;
70   bool CFALUBug;
71   int LocalMemorySize;
72   bool EnableVGPRSpilling;
73   bool SGPRInitBug;
74 
75   const DataLayout DL;
76   AMDGPUFrameLowering FrameLowering;
77   std::unique_ptr<AMDGPUTargetLowering> TLInfo;
78   std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
79   InstrItineraryData InstrItins;
80   Triple TargetTriple;
81 
82 public:
83   AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
84   AMDGPUSubtarget &initializeSubtargetDependencies(StringRef GPU, StringRef FS);
85 
getFrameLowering()86   const AMDGPUFrameLowering *getFrameLowering() const override {
87     return &FrameLowering;
88   }
getInstrInfo()89   const AMDGPUInstrInfo *getInstrInfo() const override {
90     return InstrInfo.get();
91   }
getRegisterInfo()92   const AMDGPURegisterInfo *getRegisterInfo() const override {
93     return &InstrInfo->getRegisterInfo();
94   }
getTargetLowering()95   AMDGPUTargetLowering *getTargetLowering() const override {
96     return TLInfo.get();
97   }
getDataLayout()98   const DataLayout *getDataLayout() const override { return &DL; }
getInstrItineraryData()99   const InstrItineraryData *getInstrItineraryData() const override {
100     return &InstrItins;
101   }
102 
103   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
104 
is64bit()105   bool is64bit() const {
106     return Is64bit;
107   }
108 
hasVertexCache()109   bool hasVertexCache() const {
110     return HasVertexCache;
111   }
112 
getTexVTXClauseSize()113   short getTexVTXClauseSize() const {
114     return TexVTXClauseSize;
115   }
116 
getGeneration()117   Generation getGeneration() const {
118     return Gen;
119   }
120 
hasHWFP64()121   bool hasHWFP64() const {
122     return FP64;
123   }
124 
hasCaymanISA()125   bool hasCaymanISA() const {
126     return CaymanISA;
127   }
128 
hasFP32Denormals()129   bool hasFP32Denormals() const {
130     return FP32Denormals;
131   }
132 
hasFP64Denormals()133   bool hasFP64Denormals() const {
134     return FP64Denormals;
135   }
136 
hasFlatAddressSpace()137   bool hasFlatAddressSpace() const {
138     return FlatAddressSpace;
139   }
140 
hasBFE()141   bool hasBFE() const {
142     return (getGeneration() >= EVERGREEN);
143   }
144 
hasBFI()145   bool hasBFI() const {
146     return (getGeneration() >= EVERGREEN);
147   }
148 
hasBFM()149   bool hasBFM() const {
150     return hasBFE();
151   }
152 
hasBCNT(unsigned Size)153   bool hasBCNT(unsigned Size) const {
154     if (Size == 32)
155       return (getGeneration() >= EVERGREEN);
156 
157     if (Size == 64)
158       return (getGeneration() >= SOUTHERN_ISLANDS);
159 
160     return false;
161   }
162 
hasMulU24()163   bool hasMulU24() const {
164     return (getGeneration() >= EVERGREEN);
165   }
166 
hasMulI24()167   bool hasMulI24() const {
168     return (getGeneration() >= SOUTHERN_ISLANDS ||
169             hasCaymanISA());
170   }
171 
hasFFBL()172   bool hasFFBL() const {
173     return (getGeneration() >= EVERGREEN);
174   }
175 
hasFFBH()176   bool hasFFBH() const {
177     return (getGeneration() >= EVERGREEN);
178   }
179 
IsIRStructurizerEnabled()180   bool IsIRStructurizerEnabled() const {
181     return EnableIRStructurizer;
182   }
183 
isPromoteAllocaEnabled()184   bool isPromoteAllocaEnabled() const {
185     return EnablePromoteAlloca;
186   }
187 
isIfCvtEnabled()188   bool isIfCvtEnabled() const {
189     return EnableIfCvt;
190   }
191 
loadStoreOptEnabled()192   bool loadStoreOptEnabled() const {
193     return EnableLoadStoreOpt;
194   }
195 
getWavefrontSize()196   unsigned getWavefrontSize() const {
197     return WavefrontSize;
198   }
199 
200   unsigned getStackEntrySize() const;
201 
hasCFAluBug()202   bool hasCFAluBug() const {
203     assert(getGeneration() <= NORTHERN_ISLANDS);
204     return CFALUBug;
205   }
206 
getLocalMemorySize()207   int getLocalMemorySize() const {
208     return LocalMemorySize;
209   }
210 
hasSGPRInitBug()211   bool hasSGPRInitBug() const {
212     return SGPRInitBug;
213   }
214 
215   unsigned getAmdKernelCodeChipID() const;
216 
enableMachineScheduler()217   bool enableMachineScheduler() const override {
218     return getGeneration() <= NORTHERN_ISLANDS;
219   }
220 
221   void overrideSchedPolicy(MachineSchedPolicy &Policy,
222                            MachineInstr *begin, MachineInstr *end,
223                            unsigned NumRegionInstrs) const override;
224 
225   // Helper functions to simplify if statements
isTargetELF()226   bool isTargetELF() const {
227     return false;
228   }
229 
getDeviceName()230   StringRef getDeviceName() const {
231     return DevName;
232   }
233 
dumpCode()234   bool dumpCode() const {
235     return DumpCode;
236   }
r600ALUEncoding()237   bool r600ALUEncoding() const {
238     return R600ALUInst;
239   }
isAmdHsaOS()240   bool isAmdHsaOS() const {
241     return TargetTriple.getOS() == Triple::AMDHSA;
242   }
243   bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
244 
getMaxWavesPerCU()245   unsigned getMaxWavesPerCU() const {
246     if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
247       return 10;
248 
249     // FIXME: Not sure what this is for other subtagets.
250     llvm_unreachable("do not know max waves per CU for this subtarget.");
251   }
252 };
253 
254 } // End namespace llvm
255 
256 #endif
257