1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20
21  field bits<1> SALU = 0;
22  field bits<1> VALU = 0;
23
24  field bits<1> SOP1 = 0;
25  field bits<1> SOP2 = 0;
26  field bits<1> SOPC = 0;
27  field bits<1> SOPK = 0;
28  field bits<1> SOPP = 0;
29
30  field bits<1> VOP1 = 0;
31  field bits<1> VOP2 = 0;
32  field bits<1> VOP3 = 0;
33  field bits<1> VOPC = 0;
34
35  field bits<1> MUBUF = 0;
36  field bits<1> MTBUF = 0;
37  field bits<1> SMRD = 0;
38  field bits<1> DS = 0;
39  field bits<1> MIMG = 0;
40  field bits<1> FLAT = 0;
41  field bits<1> WQM = 0;
42
43  // These need to be kept in sync with the enum in SIInstrFlags.
44  let TSFlags{0} = VM_CNT;
45  let TSFlags{1} = EXP_CNT;
46  let TSFlags{2} = LGKM_CNT;
47
48  let TSFlags{3} = SALU;
49  let TSFlags{4} = VALU;
50
51  let TSFlags{5} = SOP1;
52  let TSFlags{6} = SOP2;
53  let TSFlags{7} = SOPC;
54  let TSFlags{8} = SOPK;
55  let TSFlags{9} = SOPP;
56
57  let TSFlags{10} = VOP1;
58  let TSFlags{11} = VOP2;
59  let TSFlags{12} = VOP3;
60  let TSFlags{13} = VOPC;
61
62  let TSFlags{14} = MUBUF;
63  let TSFlags{15} = MTBUF;
64  let TSFlags{16} = SMRD;
65  let TSFlags{17} = DS;
66  let TSFlags{18} = MIMG;
67  let TSFlags{19} = FLAT;
68  let TSFlags{20} = WQM;
69
70  // Most instructions require adjustments after selection to satisfy
71  // operand requirements.
72  let hasPostISelHook = 1;
73  let SchedRW = [Write32Bit];
74}
75
76class Enc32 {
77
78  field bits<32> Inst;
79  int Size = 4;
80}
81
82class Enc64 {
83
84  field bits<64> Inst;
85  int Size = 8;
86}
87
88let Uses = [EXEC] in {
89
90class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
91    InstSI <outs, ins, asm, pattern> {
92
93  let mayLoad = 0;
94  let mayStore = 0;
95  let hasSideEffects = 0;
96  let UseNamedOperandTable = 1;
97  let VALU = 1;
98}
99
100class VOPCCommon <dag ins, string asm, list<dag> pattern> :
101    VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
102
103  let DisableEncoding = "$dst";
104  let VOPC = 1;
105  let Size = 4;
106}
107
108class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
109    VOPAnyCommon <outs, ins, asm, pattern> {
110
111  let VOP1 = 1;
112  let Size = 4;
113}
114
115class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
116    VOPAnyCommon <outs, ins, asm, pattern> {
117
118  let VOP2 = 1;
119  let Size = 4;
120}
121
122class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
123    VOPAnyCommon <outs, ins, asm, pattern> {
124
125  // Using complex patterns gives VOP3 patterns a very high complexity rating,
126  // but standalone patterns are almost always prefered, so we need to adjust the
127  // priority lower.  The goal is to use a high number to reduce complexity to
128  // zero (or less than zero).
129  let AddedComplexity = -1000;
130
131  let VOP3 = 1;
132  int Size = 8;
133}
134
135} // End Uses = [EXEC]
136
137//===----------------------------------------------------------------------===//
138// Scalar operations
139//===----------------------------------------------------------------------===//
140
141class SOP1e <bits<8> op> : Enc32 {
142
143  bits<7> SDST;
144  bits<8> SSRC0;
145
146  let Inst{7-0} = SSRC0;
147  let Inst{15-8} = op;
148  let Inst{22-16} = SDST;
149  let Inst{31-23} = 0x17d; //encoding;
150}
151
152class SOP2e <bits<7> op> : Enc32 {
153
154  bits<7> SDST;
155  bits<8> SSRC0;
156  bits<8> SSRC1;
157
158  let Inst{7-0} = SSRC0;
159  let Inst{15-8} = SSRC1;
160  let Inst{22-16} = SDST;
161  let Inst{29-23} = op;
162  let Inst{31-30} = 0x2; // encoding
163}
164
165class SOPCe <bits<7> op> : Enc32 {
166
167  bits<8> SSRC0;
168  bits<8> SSRC1;
169
170  let Inst{7-0} = SSRC0;
171  let Inst{15-8} = SSRC1;
172  let Inst{22-16} = op;
173  let Inst{31-23} = 0x17e;
174}
175
176class SOPKe <bits<5> op> : Enc32 {
177
178  bits <7> SDST;
179  bits <16> SIMM16;
180
181  let Inst{15-0} = SIMM16;
182  let Inst{22-16} = SDST;
183  let Inst{27-23} = op;
184  let Inst{31-28} = 0xb; //encoding
185}
186
187class SOPPe <bits<7> op> : Enc32 {
188
189  bits <16> simm16;
190
191  let Inst{15-0} = simm16;
192  let Inst{22-16} = op;
193  let Inst{31-23} = 0x17f; // encoding
194}
195
196class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
197
198  bits<7> SDST;
199  bits<7> SBASE;
200  bits<8> OFFSET;
201
202  let Inst{7-0} = OFFSET;
203  let Inst{8} = imm;
204  let Inst{14-9} = SBASE{6-1};
205  let Inst{21-15} = SDST;
206  let Inst{26-22} = op;
207  let Inst{31-27} = 0x18; //encoding
208}
209
210let SchedRW = [WriteSALU] in {
211class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
212    InstSI<outs, ins, asm, pattern> {
213  let mayLoad = 0;
214  let mayStore = 0;
215  let hasSideEffects = 0;
216  let SALU = 1;
217  let SOP1 = 1;
218}
219
220class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
221    InstSI <outs, ins, asm, pattern> {
222
223  let mayLoad = 0;
224  let mayStore = 0;
225  let hasSideEffects = 0;
226  let SALU = 1;
227  let SOP2 = 1;
228
229  let UseNamedOperandTable = 1;
230}
231
232class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
233  InstSI<outs, ins, asm, pattern>, SOPCe <op> {
234
235  let DisableEncoding = "$dst";
236  let mayLoad = 0;
237  let mayStore = 0;
238  let hasSideEffects = 0;
239  let SALU = 1;
240  let SOPC = 1;
241
242  let UseNamedOperandTable = 1;
243}
244
245class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
246   InstSI <outs, ins , asm, pattern> {
247
248  let mayLoad = 0;
249  let mayStore = 0;
250  let hasSideEffects = 0;
251  let SALU = 1;
252  let SOPK = 1;
253
254  let UseNamedOperandTable = 1;
255}
256
257class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
258		InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
259
260  let mayLoad = 0;
261  let mayStore = 0;
262  let hasSideEffects = 0;
263  let isCodeGenOnly = 0;
264  let SALU = 1;
265  let SOPP = 1;
266
267  let UseNamedOperandTable = 1;
268}
269
270} // let SchedRW = [WriteSALU]
271
272class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
273    InstSI<outs, ins, asm, pattern> {
274
275  let LGKM_CNT = 1;
276  let SMRD = 1;
277  let mayStore = 0;
278  let mayLoad = 1;
279  let hasSideEffects = 0;
280  let UseNamedOperandTable = 1;
281  let SchedRW = [WriteSMEM];
282}
283
284//===----------------------------------------------------------------------===//
285// Vector ALU operations
286//===----------------------------------------------------------------------===//
287
288class VOP1e <bits<8> op> : Enc32 {
289
290  bits<8> VDST;
291  bits<9> SRC0;
292
293  let Inst{8-0} = SRC0;
294  let Inst{16-9} = op;
295  let Inst{24-17} = VDST;
296  let Inst{31-25} = 0x3f; //encoding
297}
298
299class VOP2e <bits<6> op> : Enc32 {
300  bits<8> vdst;
301  bits<9> src0;
302  bits<8> src1;
303
304  let Inst{8-0} = src0;
305  let Inst{16-9} = src1;
306  let Inst{24-17} = vdst;
307  let Inst{30-25} = op;
308  let Inst{31} = 0x0; //encoding
309}
310
311class VOP2_MADKe <bits<6> op> : Enc64 {
312
313  bits<8>  vdst;
314  bits<9>  src0;
315  bits<8>  vsrc1;
316  bits<32> src2;
317
318  let Inst{8-0} = src0;
319  let Inst{16-9} = vsrc1;
320  let Inst{24-17} = vdst;
321  let Inst{30-25} = op;
322  let Inst{31} = 0x0; // encoding
323  let Inst{63-32} = src2;
324}
325
326class VOP3e <bits<9> op> : Enc64 {
327
328  bits<8> dst;
329  bits<2> src0_modifiers;
330  bits<9> src0;
331  bits<2> src1_modifiers;
332  bits<9> src1;
333  bits<2> src2_modifiers;
334  bits<9> src2;
335  bits<1> clamp;
336  bits<2> omod;
337
338  let Inst{7-0} = dst;
339  let Inst{8} = src0_modifiers{1};
340  let Inst{9} = src1_modifiers{1};
341  let Inst{10} = src2_modifiers{1};
342  let Inst{11} = clamp;
343  let Inst{25-17} = op;
344  let Inst{31-26} = 0x34; //encoding
345  let Inst{40-32} = src0;
346  let Inst{49-41} = src1;
347  let Inst{58-50} = src2;
348  let Inst{60-59} = omod;
349  let Inst{61} = src0_modifiers{0};
350  let Inst{62} = src1_modifiers{0};
351  let Inst{63} = src2_modifiers{0};
352}
353
354class VOP3be <bits<9> op> : Enc64 {
355
356  bits<8> dst;
357  bits<2> src0_modifiers;
358  bits<9> src0;
359  bits<2> src1_modifiers;
360  bits<9> src1;
361  bits<2> src2_modifiers;
362  bits<9> src2;
363  bits<7> sdst;
364  bits<2> omod;
365
366  let Inst{7-0} = dst;
367  let Inst{14-8} = sdst;
368  let Inst{25-17} = op;
369  let Inst{31-26} = 0x34; //encoding
370  let Inst{40-32} = src0;
371  let Inst{49-41} = src1;
372  let Inst{58-50} = src2;
373  let Inst{60-59} = omod;
374  let Inst{61} = src0_modifiers{0};
375  let Inst{62} = src1_modifiers{0};
376  let Inst{63} = src2_modifiers{0};
377}
378
379class VOPCe <bits<8> op> : Enc32 {
380
381  bits<9> SRC0;
382  bits<8> VSRC1;
383
384  let Inst{8-0} = SRC0;
385  let Inst{16-9} = VSRC1;
386  let Inst{24-17} = op;
387  let Inst{31-25} = 0x3e;
388}
389
390class VINTRPe <bits<2> op> : Enc32 {
391
392  bits<8> VDST;
393  bits<8> VSRC;
394  bits<2> ATTRCHAN;
395  bits<6> ATTR;
396
397  let Inst{7-0} = VSRC;
398  let Inst{9-8} = ATTRCHAN;
399  let Inst{15-10} = ATTR;
400  let Inst{17-16} = op;
401  let Inst{25-18} = VDST;
402  let Inst{31-26} = 0x32; // encoding
403}
404
405class DSe <bits<8> op> : Enc64 {
406
407  bits<8> vdst;
408  bits<1> gds;
409  bits<8> addr;
410  bits<8> data0;
411  bits<8> data1;
412  bits<8> offset0;
413  bits<8> offset1;
414
415  let Inst{7-0} = offset0;
416  let Inst{15-8} = offset1;
417  let Inst{17} = gds;
418  let Inst{25-18} = op;
419  let Inst{31-26} = 0x36; //encoding
420  let Inst{39-32} = addr;
421  let Inst{47-40} = data0;
422  let Inst{55-48} = data1;
423  let Inst{63-56} = vdst;
424}
425
426class MUBUFe <bits<7> op> : Enc64 {
427
428  bits<12> offset;
429  bits<1> offen;
430  bits<1> idxen;
431  bits<1> glc;
432  bits<1> addr64;
433  bits<1> lds;
434  bits<8> vaddr;
435  bits<8> vdata;
436  bits<7> srsrc;
437  bits<1> slc;
438  bits<1> tfe;
439  bits<8> soffset;
440
441  let Inst{11-0} = offset;
442  let Inst{12} = offen;
443  let Inst{13} = idxen;
444  let Inst{14} = glc;
445  let Inst{15} = addr64;
446  let Inst{16} = lds;
447  let Inst{24-18} = op;
448  let Inst{31-26} = 0x38; //encoding
449  let Inst{39-32} = vaddr;
450  let Inst{47-40} = vdata;
451  let Inst{52-48} = srsrc{6-2};
452  let Inst{54} = slc;
453  let Inst{55} = tfe;
454  let Inst{63-56} = soffset;
455}
456
457class MTBUFe <bits<3> op> : Enc64 {
458
459  bits<8> VDATA;
460  bits<12> OFFSET;
461  bits<1> OFFEN;
462  bits<1> IDXEN;
463  bits<1> GLC;
464  bits<1> ADDR64;
465  bits<4> DFMT;
466  bits<3> NFMT;
467  bits<8> VADDR;
468  bits<7> SRSRC;
469  bits<1> SLC;
470  bits<1> TFE;
471  bits<8> SOFFSET;
472
473  let Inst{11-0} = OFFSET;
474  let Inst{12} = OFFEN;
475  let Inst{13} = IDXEN;
476  let Inst{14} = GLC;
477  let Inst{15} = ADDR64;
478  let Inst{18-16} = op;
479  let Inst{22-19} = DFMT;
480  let Inst{25-23} = NFMT;
481  let Inst{31-26} = 0x3a; //encoding
482  let Inst{39-32} = VADDR;
483  let Inst{47-40} = VDATA;
484  let Inst{52-48} = SRSRC{6-2};
485  let Inst{54} = SLC;
486  let Inst{55} = TFE;
487  let Inst{63-56} = SOFFSET;
488}
489
490class MIMGe <bits<7> op> : Enc64 {
491
492  bits<8> VDATA;
493  bits<4> DMASK;
494  bits<1> UNORM;
495  bits<1> GLC;
496  bits<1> DA;
497  bits<1> R128;
498  bits<1> TFE;
499  bits<1> LWE;
500  bits<1> SLC;
501  bits<8> VADDR;
502  bits<7> SRSRC;
503  bits<7> SSAMP;
504
505  let Inst{11-8} = DMASK;
506  let Inst{12} = UNORM;
507  let Inst{13} = GLC;
508  let Inst{14} = DA;
509  let Inst{15} = R128;
510  let Inst{16} = TFE;
511  let Inst{17} = LWE;
512  let Inst{24-18} = op;
513  let Inst{25} = SLC;
514  let Inst{31-26} = 0x3c;
515  let Inst{39-32} = VADDR;
516  let Inst{47-40} = VDATA;
517  let Inst{52-48} = SRSRC{6-2};
518  let Inst{57-53} = SSAMP{6-2};
519}
520
521class FLATe<bits<7> op> : Enc64 {
522  bits<8> addr;
523  bits<8> data;
524  bits<8> vdst;
525  bits<1> slc;
526  bits<1> glc;
527  bits<1> tfe;
528
529  // 15-0 is reserved.
530  let Inst{16} = glc;
531  let Inst{17} = slc;
532  let Inst{24-18} = op;
533  let Inst{31-26} = 0x37; // Encoding.
534  let Inst{39-32} = addr;
535  let Inst{47-40} = data;
536  // 54-48 is reserved.
537  let Inst{55} = tfe;
538  let Inst{63-56} = vdst;
539}
540
541class EXPe : Enc64 {
542  bits<4> EN;
543  bits<6> TGT;
544  bits<1> COMPR;
545  bits<1> DONE;
546  bits<1> VM;
547  bits<8> VSRC0;
548  bits<8> VSRC1;
549  bits<8> VSRC2;
550  bits<8> VSRC3;
551
552  let Inst{3-0} = EN;
553  let Inst{9-4} = TGT;
554  let Inst{10} = COMPR;
555  let Inst{11} = DONE;
556  let Inst{12} = VM;
557  let Inst{31-26} = 0x3e;
558  let Inst{39-32} = VSRC0;
559  let Inst{47-40} = VSRC1;
560  let Inst{55-48} = VSRC2;
561  let Inst{63-56} = VSRC3;
562}
563
564let Uses = [EXEC] in {
565
566class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
567    VOP1Common <outs, ins, asm, pattern>,
568    VOP1e<op>;
569
570class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
571    VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
572
573class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
574    VOPCCommon <ins, asm, pattern>, VOPCe <op>;
575
576class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
577    InstSI <outs, ins, asm, pattern> {
578  let mayLoad = 1;
579  let mayStore = 0;
580  let hasSideEffects = 0;
581}
582
583} // End Uses = [EXEC]
584
585//===----------------------------------------------------------------------===//
586// Vector I/O operations
587//===----------------------------------------------------------------------===//
588
589let Uses = [EXEC] in {
590
591class DS <dag outs, dag ins, string asm, list<dag> pattern> :
592    InstSI <outs, ins, asm, pattern> {
593
594  let LGKM_CNT = 1;
595  let DS = 1;
596  let UseNamedOperandTable = 1;
597  let DisableEncoding = "$m0";
598  let SchedRW = [WriteLDS];
599}
600
601class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
602    InstSI<outs, ins, asm, pattern> {
603
604  let VM_CNT = 1;
605  let EXP_CNT = 1;
606  let MUBUF = 1;
607
608  let hasSideEffects = 0;
609  let UseNamedOperandTable = 1;
610  let SchedRW = [WriteVMEM];
611}
612
613class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
614    InstSI<outs, ins, asm, pattern> {
615
616  let VM_CNT = 1;
617  let EXP_CNT = 1;
618  let MTBUF = 1;
619
620  let hasSideEffects = 0;
621  let UseNamedOperandTable = 1;
622  let SchedRW = [WriteVMEM];
623}
624
625class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
626    InstSI<outs, ins, asm, pattern>, FLATe <op> {
627  let FLAT = 1;
628  // Internally, FLAT instruction are executed as both an LDS and a
629  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
630  // and are not considered done until both have been decremented.
631  let VM_CNT = 1;
632  let LGKM_CNT = 1;
633
634  let Uses = [EXEC, FLAT_SCR]; // M0
635
636  let UseNamedOperandTable = 1;
637  let hasSideEffects = 0;
638}
639
640class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
641    InstSI <outs, ins, asm, pattern>, MIMGe <op> {
642
643  let VM_CNT = 1;
644  let EXP_CNT = 1;
645  let MIMG = 1;
646
647  let hasSideEffects = 0; // XXX ????
648}
649
650
651} // End Uses = [EXEC]
652