1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains XCore frame information that doesn't fit anywhere else
11 // cleanly...
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "XCoreFrameLowering.h"
16 #include "XCore.h"
17 #include "XCoreInstrInfo.h"
18 #include "XCoreMachineFunctionInfo.h"
19 #include "XCoreSubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include <algorithm> // std::sort
32
33 using namespace llvm;
34
35 static const unsigned FramePtr = XCore::R10;
36 static const int MaxImmU16 = (1<<16) - 1;
37
38 // helper functions. FIXME: Eliminate.
isImmU6(unsigned val)39 static inline bool isImmU6(unsigned val) {
40 return val < (1 << 6);
41 }
42
isImmU16(unsigned val)43 static inline bool isImmU16(unsigned val) {
44 return val < (1 << 16);
45 }
46
47 // Helper structure with compare function for handling stack slots.
48 namespace {
49 struct StackSlotInfo {
50 int FI;
51 int Offset;
52 unsigned Reg;
StackSlotInfo__anon05d4b7140111::StackSlotInfo53 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){};
54 };
55 } // end anonymous namespace
56
CompareSSIOffset(const StackSlotInfo & a,const StackSlotInfo & b)57 static bool CompareSSIOffset(const StackSlotInfo& a, const StackSlotInfo& b) {
58 return a.Offset < b.Offset;
59 }
60
61
EmitDefCfaRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,MachineModuleInfo * MMI,unsigned DRegNum)62 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MBBI, DebugLoc dl,
64 const TargetInstrInfo &TII,
65 MachineModuleInfo *MMI, unsigned DRegNum) {
66 unsigned CFIIndex = MMI->addFrameInst(
67 MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
68 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
69 .addCFIIndex(CFIIndex);
70 }
71
EmitDefCfaOffset(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,MachineModuleInfo * MMI,int Offset)72 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MBBI, DebugLoc dl,
74 const TargetInstrInfo &TII,
75 MachineModuleInfo *MMI, int Offset) {
76 unsigned CFIIndex =
77 MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
78 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
79 .addCFIIndex(CFIIndex);
80 }
81
EmitCfiOffset(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,MachineModuleInfo * MMI,unsigned DRegNum,int Offset)82 static void EmitCfiOffset(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI, DebugLoc dl,
84 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
85 unsigned DRegNum, int Offset) {
86 unsigned CFIIndex = MMI->addFrameInst(
87 MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
89 .addCFIIndex(CFIIndex);
90 }
91
92 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
93 /// frame. During these steps, it may be necessary to spill registers.
94 /// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only
95 /// as far as to make 'OffsetFromBottom' reachable using an STWSP_lru6.
96 /// \param OffsetFromTop the spill offset from the top of the frame.
97 /// \param [in,out] Adjusted the current SP offset from the top of the frame.
IfNeededExtSP(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,MachineModuleInfo * MMI,int OffsetFromTop,int & Adjusted,int FrameSize,bool emitFrameMoves)98 static void IfNeededExtSP(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MBBI, DebugLoc dl,
100 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
101 int OffsetFromTop, int &Adjusted, int FrameSize,
102 bool emitFrameMoves) {
103 while (OffsetFromTop > Adjusted) {
104 assert(Adjusted < FrameSize && "OffsetFromTop is beyond FrameSize");
105 int remaining = FrameSize - Adjusted;
106 int OpImm = (remaining > MaxImmU16) ? MaxImmU16 : remaining;
107 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
109 Adjusted += OpImm;
110 if (emitFrameMoves)
111 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
112 }
113 }
114
115 /// The SP register is moved in steps of 'MaxImmU16' towards the top of the
116 /// frame. During these steps, it may be necessary to re-load registers.
117 /// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
118 /// as far as to make 'OffsetFromTop' reachable using an LDAWSP_lru6.
119 /// \param OffsetFromTop the spill offset from the top of the frame.
120 /// \param [in,out] RemainingAdj the current SP offset from the top of the
121 /// frame.
IfNeededLDAWSP(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,int OffsetFromTop,int & RemainingAdj)122 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MBBI, DebugLoc dl,
124 const TargetInstrInfo &TII, int OffsetFromTop,
125 int &RemainingAdj) {
126 while (OffsetFromTop < RemainingAdj - MaxImmU16) {
127 assert(RemainingAdj && "OffsetFromTop is beyond FrameSize");
128 int OpImm = (RemainingAdj > MaxImmU16) ? MaxImmU16 : RemainingAdj;
129 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
131 RemainingAdj -= OpImm;
132 }
133 }
134
135 /// Creates an ordered list of registers that are spilled
136 /// during the emitPrologue/emitEpilogue.
137 /// Registers are ordered according to their frame offset.
138 /// As offsets are negative, the largest offsets will be first.
GetSpillList(SmallVectorImpl<StackSlotInfo> & SpillList,MachineFrameInfo * MFI,XCoreFunctionInfo * XFI,bool fetchLR,bool fetchFP)139 static void GetSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
140 MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
141 bool fetchLR, bool fetchFP) {
142 if (fetchLR) {
143 int Offset = MFI->getObjectOffset(XFI->getLRSpillSlot());
144 SpillList.push_back(StackSlotInfo(XFI->getLRSpillSlot(),
145 Offset,
146 XCore::LR));
147 }
148 if (fetchFP) {
149 int Offset = MFI->getObjectOffset(XFI->getFPSpillSlot());
150 SpillList.push_back(StackSlotInfo(XFI->getFPSpillSlot(),
151 Offset,
152 FramePtr));
153 }
154 std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
155 }
156
157 /// Creates an ordered list of EH info register 'spills'.
158 /// These slots are only used by the unwinder and calls to llvm.eh.return().
159 /// Registers are ordered according to their frame offset.
160 /// As offsets are negative, the largest offsets will be first.
GetEHSpillList(SmallVectorImpl<StackSlotInfo> & SpillList,MachineFrameInfo * MFI,XCoreFunctionInfo * XFI,const TargetLowering * TL)161 static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
162 MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
163 const TargetLowering *TL) {
164 assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
165 const int* EHSlot = XFI->getEHSpillSlot();
166 SpillList.push_back(StackSlotInfo(EHSlot[0],
167 MFI->getObjectOffset(EHSlot[0]),
168 TL->getExceptionPointerRegister()));
169 SpillList.push_back(StackSlotInfo(EHSlot[0],
170 MFI->getObjectOffset(EHSlot[1]),
171 TL->getExceptionSelectorRegister()));
172 std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
173 }
174
175
176 static MachineMemOperand *
getFrameIndexMMO(MachineBasicBlock & MBB,int FrameIndex,unsigned flags)177 getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) {
178 MachineFunction *MF = MBB.getParent();
179 const MachineFrameInfo &MFI = *MF->getFrameInfo();
180 MachineMemOperand *MMO =
181 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
182 flags, MFI.getObjectSize(FrameIndex),
183 MFI.getObjectAlignment(FrameIndex));
184 return MMO;
185 }
186
187
188 /// Restore clobbered registers with their spill slot value.
189 /// The SP will be adjusted at the same time, thus the SpillList must be ordered
190 /// with the largest (negative) offsets first.
191 static void
RestoreSpillList(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc dl,const TargetInstrInfo & TII,int & RemainingAdj,SmallVectorImpl<StackSlotInfo> & SpillList)192 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
193 DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj,
194 SmallVectorImpl<StackSlotInfo> &SpillList) {
195 for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
196 assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
197 assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
198 int OffsetFromTop = - SpillList[i].Offset/4;
199 IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
200 int Offset = RemainingAdj - OffsetFromTop;
201 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
202 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
203 .addImm(Offset)
204 .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
205 MachineMemOperand::MOLoad));
206 }
207 }
208
209 //===----------------------------------------------------------------------===//
210 // XCoreFrameLowering:
211 //===----------------------------------------------------------------------===//
212
XCoreFrameLowering(const XCoreSubtarget & sti)213 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
214 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
215 // Do nothing
216 }
217
hasFP(const MachineFunction & MF) const218 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
219 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
220 MF.getFrameInfo()->hasVarSizedObjects();
221 }
222
emitPrologue(MachineFunction & MF) const223 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
224 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
225 MachineBasicBlock::iterator MBBI = MBB.begin();
226 MachineFrameInfo *MFI = MF.getFrameInfo();
227 MachineModuleInfo *MMI = &MF.getMMI();
228 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
229 const XCoreInstrInfo &TII =
230 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
231 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
232 // Debug location must be unknown since the first debug location is used
233 // to determine the end of the prologue.
234 DebugLoc dl;
235
236 if (MFI->getMaxAlignment() > getStackAlignment())
237 report_fatal_error("emitPrologue unsupported alignment: "
238 + Twine(MFI->getMaxAlignment()));
239
240 const AttributeSet &PAL = MF.getFunction()->getAttributes();
241 if (PAL.hasAttrSomewhere(Attribute::Nest))
242 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
243 // FIX: Needs addMemOperand() but can't use getFixedStack() or getStack().
244
245 // Work out frame sizes.
246 // We will adjust the SP in stages towards the final FrameSize.
247 assert(MFI->getStackSize()%4 == 0 && "Misaligned frame size");
248 const int FrameSize = MFI->getStackSize() / 4;
249 int Adjusted = 0;
250
251 bool saveLR = XFI->hasLRSpillSlot();
252 bool UseENTSP = saveLR && FrameSize
253 && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
254 if (UseENTSP)
255 saveLR = false;
256 bool FP = hasFP(MF);
257 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
258
259 if (UseENTSP) {
260 // Allocate space on the stack at the same time as saving LR.
261 Adjusted = (FrameSize > MaxImmU16) ? MaxImmU16 : FrameSize;
262 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
263 MBB.addLiveIn(XCore::LR);
264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
265 MIB.addImm(Adjusted);
266 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
267 true);
268 if (emitFrameMoves) {
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
270 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
271 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0);
272 }
273 }
274
275 // If necessary, save LR and FP to the stack, as we EXTSP.
276 SmallVector<StackSlotInfo,2> SpillList;
277 GetSpillList(SpillList, MFI, XFI, saveLR, FP);
278 // We want the nearest (negative) offsets first, so reverse list.
279 std::reverse(SpillList.begin(), SpillList.end());
280 for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
281 assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
282 assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
283 int OffsetFromTop = - SpillList[i].Offset/4;
284 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
285 emitFrameMoves);
286 int Offset = Adjusted - OffsetFromTop;
287 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
288 MBB.addLiveIn(SpillList[i].Reg);
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
290 .addReg(SpillList[i].Reg, RegState::Kill)
291 .addImm(Offset)
292 .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
293 MachineMemOperand::MOStore));
294 if (emitFrameMoves) {
295 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
296 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillList[i].Offset);
297 }
298 }
299
300 // Complete any remaining Stack adjustment.
301 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, FrameSize, Adjusted, FrameSize,
302 emitFrameMoves);
303 assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
304
305 if (FP) {
306 // Set the FP from the SP.
307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
308 if (emitFrameMoves)
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MMI,
310 MRI->getDwarfRegNum(FramePtr, true));
311 }
312
313 if (emitFrameMoves) {
314 // Frame moves for callee saved.
315 for (const auto &SpillLabel : XFI->getSpillLabels()) {
316 MachineBasicBlock::iterator Pos = SpillLabel.first;
317 ++Pos;
318 const CalleeSavedInfo &CSI = SpillLabel.second;
319 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
320 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
321 EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset);
322 }
323 if (XFI->hasEHSpillSlot()) {
324 // The unwinder requires stack slot & CFI offsets for the exception info.
325 // We do not save/spill these registers.
326 SmallVector<StackSlotInfo,2> SpillList;
327 GetEHSpillList(SpillList, MFI, XFI,
328 MF.getSubtarget().getTargetLowering());
329 assert(SpillList.size()==2 && "Unexpected SpillList size");
330 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
331 MRI->getDwarfRegNum(SpillList[0].Reg, true),
332 SpillList[0].Offset);
333 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
334 MRI->getDwarfRegNum(SpillList[1].Reg, true),
335 SpillList[1].Offset);
336 }
337 }
338 }
339
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const340 void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
341 MachineBasicBlock &MBB) const {
342 MachineFrameInfo *MFI = MF.getFrameInfo();
343 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
344 const XCoreInstrInfo &TII =
345 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
346 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
347 DebugLoc dl = MBBI->getDebugLoc();
348 unsigned RetOpcode = MBBI->getOpcode();
349
350 // Work out frame sizes.
351 // We will adjust the SP in stages towards the final FrameSize.
352 int RemainingAdj = MFI->getStackSize();
353 assert(RemainingAdj%4 == 0 && "Misaligned frame size");
354 RemainingAdj /= 4;
355
356 if (RetOpcode == XCore::EH_RETURN) {
357 // 'Restore' the exception info the unwinder has placed into the stack
358 // slots.
359 SmallVector<StackSlotInfo,2> SpillList;
360 GetEHSpillList(SpillList, MFI, XFI, MF.getSubtarget().getTargetLowering());
361 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
362
363 // Return to the landing pad.
364 unsigned EhStackReg = MBBI->getOperand(0).getReg();
365 unsigned EhHandlerReg = MBBI->getOperand(1).getReg();
366 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
367 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
368 MBB.erase(MBBI); // Erase the previous return instruction.
369 return;
370 }
371
372 bool restoreLR = XFI->hasLRSpillSlot();
373 bool UseRETSP = restoreLR && RemainingAdj
374 && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
375 if (UseRETSP)
376 restoreLR = false;
377 bool FP = hasFP(MF);
378
379 if (FP) // Restore the stack pointer.
380 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
381
382 // If necessary, restore LR and FP from the stack, as we EXTSP.
383 SmallVector<StackSlotInfo,2> SpillList;
384 GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
385 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
386
387 if (RemainingAdj) {
388 // Complete all but one of the remaining Stack adjustments.
389 IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
390 if (UseRETSP) {
391 // Fold prologue into return instruction
392 assert(RetOpcode == XCore::RETSP_u6
393 || RetOpcode == XCore::RETSP_lu6);
394 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
395 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
396 .addImm(RemainingAdj);
397 for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
398 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
399 MBB.erase(MBBI); // Erase the previous return instruction.
400 } else {
401 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 :
402 XCore::LDAWSP_lru6;
403 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
404 // Don't erase the return instruction.
405 }
406 } // else Don't erase the return instruction.
407 }
408
409 bool XCoreFrameLowering::
spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const410 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
411 MachineBasicBlock::iterator MI,
412 const std::vector<CalleeSavedInfo> &CSI,
413 const TargetRegisterInfo *TRI) const {
414 if (CSI.empty())
415 return true;
416
417 MachineFunction *MF = MBB.getParent();
418 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
419 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
420 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
421
422 DebugLoc DL;
423 if (MI != MBB.end() && !MI->isDebugValue())
424 DL = MI->getDebugLoc();
425
426 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
427 it != CSI.end(); ++it) {
428 unsigned Reg = it->getReg();
429 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
430 "LR & FP are always handled in emitPrologue");
431
432 // Add the callee-saved register as live-in. It's killed at the spill.
433 MBB.addLiveIn(Reg);
434 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
435 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
436 if (emitFrameMoves) {
437 auto Store = MI;
438 --Store;
439 XFI->getSpillLabels().push_back(std::make_pair(Store, *it));
440 }
441 }
442 return true;
443 }
444
445 bool XCoreFrameLowering::
restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const446 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator MI,
448 const std::vector<CalleeSavedInfo> &CSI,
449 const TargetRegisterInfo *TRI) const{
450 MachineFunction *MF = MBB.getParent();
451 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
452 bool AtStart = MI == MBB.begin();
453 MachineBasicBlock::iterator BeforeI = MI;
454 if (!AtStart)
455 --BeforeI;
456 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
457 it != CSI.end(); ++it) {
458 unsigned Reg = it->getReg();
459 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
460 "LR & FP are always handled in emitEpilogue");
461
462 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
463 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
464 assert(MI != MBB.begin() &&
465 "loadRegFromStackSlot didn't insert any code!");
466 // Insert in reverse order. loadRegFromStackSlot can insert multiple
467 // instructions.
468 if (AtStart)
469 MI = MBB.begin();
470 else {
471 MI = BeforeI;
472 ++MI;
473 }
474 }
475 return true;
476 }
477
478 // This function eliminates ADJCALLSTACKDOWN,
479 // ADJCALLSTACKUP pseudo instructions
480 void XCoreFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const481 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
482 MachineBasicBlock::iterator I) const {
483 const XCoreInstrInfo &TII =
484 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
485 if (!hasReservedCallFrame(MF)) {
486 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
487 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
488 MachineInstr *Old = I;
489 uint64_t Amount = Old->getOperand(0).getImm();
490 if (Amount != 0) {
491 // We need to keep the stack aligned properly. To do this, we round the
492 // amount of space needed for the outgoing arguments up to the next
493 // alignment boundary.
494 unsigned Align = getStackAlignment();
495 Amount = (Amount+Align-1)/Align*Align;
496
497 assert(Amount%4 == 0);
498 Amount /= 4;
499
500 bool isU6 = isImmU6(Amount);
501 if (!isU6 && !isImmU16(Amount)) {
502 // FIX could emit multiple instructions in this case.
503 #ifndef NDEBUG
504 errs() << "eliminateCallFramePseudoInstr size too big: "
505 << Amount << "\n";
506 #endif
507 llvm_unreachable(nullptr);
508 }
509
510 MachineInstr *New;
511 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
512 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
513 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
514 .addImm(Amount);
515 } else {
516 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
517 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
518 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
519 .addImm(Amount);
520 }
521
522 // Replace the pseudo instruction with a new instruction...
523 MBB.insert(I, New);
524 }
525 }
526
527 MBB.erase(I);
528 }
529
530 void XCoreFrameLowering::
processFunctionBeforeCalleeSavedScan(MachineFunction & MF,RegScavenger * RS) const531 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
532 RegScavenger *RS) const {
533 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
534
535 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
536
537 if (!LRUsed && !MF.getFunction()->isVarArg() &&
538 MF.getFrameInfo()->estimateStackSize(MF))
539 // If we need to extend the stack it is more efficient to use entsp / retsp.
540 // We force the LR to be saved so these instructions are used.
541 LRUsed = true;
542
543 if (MF.getMMI().callsUnwindInit() || MF.getMMI().callsEHReturn()) {
544 // The unwinder expects to find spill slots for the exception info regs R0
545 // & R1. These are used during llvm.eh.return() to 'restore' the exception
546 // info. N.B. we do not spill or restore R0, R1 during normal operation.
547 XFI->createEHSpillSlot(MF);
548 // As we will have a stack, we force the LR to be saved.
549 LRUsed = true;
550 }
551
552 if (LRUsed) {
553 // We will handle the LR in the prologue/epilogue
554 // and allocate space on the stack ourselves.
555 MF.getRegInfo().setPhysRegUnused(XCore::LR);
556 XFI->createLRSpillSlot(MF);
557 }
558
559 if (hasFP(MF))
560 // A callee save register is used to hold the FP.
561 // This needs saving / restoring in the epilogue / prologue.
562 XFI->createFPSpillSlot(MF);
563 }
564
565 void XCoreFrameLowering::
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const566 processFunctionBeforeFrameFinalized(MachineFunction &MF,
567 RegScavenger *RS) const {
568 assert(RS && "requiresRegisterScavenging failed");
569 MachineFrameInfo *MFI = MF.getFrameInfo();
570 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
571 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
572 // Reserve slots close to SP or frame pointer for Scavenging spills.
573 // When using SP for small frames, we don't need any scratch registers.
574 // When using SP for large frames, we may need 2 scratch registers.
575 // When using FP, for large or small frames, we may need 1 scratch register.
576 if (XFI->isLargeFrame(MF) || hasFP(MF))
577 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
578 RC->getAlignment(),
579 false));
580 if (XFI->isLargeFrame(MF) && !hasFP(MF))
581 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
582 RC->getAlignment(),
583 false));
584 }
585