1; Disable machine cse to stress the different path of the algorithm. 2; Otherwise, we always fall in the simple case, i.e., only one definition. 3; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s 4; The REGULAR run just checks that the inputs passed to promote const expose 5; the appropriate patterns. 6; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s 7 8%struct.uint8x16x4_t = type { [4 x <16 x i8>] } 9 10; Constant is a structure 11define %struct.uint8x16x4_t @test1() { 12; PROMOTED-LABEL: test1: 13; Promote constant has created a big constant for the whole structure 14; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE 15; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF 16; Destination registers are defined by the ABI 17; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]] 18; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32] 19; PROMOTED-NEXT: ret 20 21; REGULAR-LABEL: test1: 22; Regular access is quite bad, it performs 4 loads, one for each chunk of 23; the structure 24; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 25; Destination registers are defined by the ABI 26; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 27; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 28; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 29; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE 30; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF] 31; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE 32; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF] 33; REGULAR-NEXT: ret 34entry: 35 ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] } 36} 37 38; Two different uses of the same constant in the same basic block 39define <16 x i8> @test2(<16 x i8> %arg) { 40entry: 41; PROMOTED-LABEL: test2: 42; In stress mode, constant vector are promoted 43; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE 44; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] 45; Destination register is defined by ABI 46; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 47; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]] 48; PROMOTED-NEXT: ret 49 50; REGULAR-LABEL: test2: 51; Regular access is strickly the same as promoted access. 52; The difference is that the address (and thus the space in memory) is not 53; shared between constants 54; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 55; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 56; Destination register is defined by ABI 57; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 58; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]] 59; REGULAR-NEXT: ret 60 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 61 %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 62 %add.i9 = add <16 x i8> %add.i, %mul.i 63 ret <16 x i8> %add.i9 64} 65 66; Two different uses of the sane constant in two different basic blocks, 67; one dominates the other 68define <16 x i8> @test3(<16 x i8> %arg, i32 %path) { 69; PROMOTED-LABEL: test3: 70; In stress mode, constant vector are promoted 71; Since, the constant is the same as the previous function, 72; the same address must be used 73; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 74; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] 75; Destination register is defined by ABI 76; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 77; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]] 78; Next BB 79; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE 80; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTV2]]@PAGEOFF] 81; Next BB 82; PROMOTED-NEXT: [[LABEL]]: 83; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 84; PROMOTED-NEXT: add.16b v0, v0, [[DESTV]] 85; PROMOTED-NEXT: ret 86 87; REGULAR-LABEL: test3: 88; Regular mode does not elimitate common sub expression by its own. 89; In other words, the same loads appears several times. 90; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1:lCP.*]]@PAGE 91; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] 92; Destination register is defined by ABI 93; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 94; REGULAR-NEXT: cbz w0, [[LABELelse:LBB.*]] 95; Next BB 96; Redundant load 97; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1]]@PAGE 98; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] 99; REGULAR-NEXT: b [[LABELend:LBB.*]] 100; Next BB 101; REGULAR-NEXT: [[LABELelse]] 102; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE 103; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL2]]@PAGEOFF] 104; Next BB 105; REGULAR-NEXT: [[LABELend]]: 106; REGULAR-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 107; REGULAR-NEXT: add.16b v0, v0, [[DESTV]] 108; REGULAR-NEXT: ret 109entry: 110 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 111 %tobool = icmp eq i32 %path, 0 112 br i1 %tobool, label %if.else, label %if.then 113 114if.then: ; preds = %entry 115 %mul.i13 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 116 br label %if.end 117 118if.else: ; preds = %entry 119 %mul.i = mul <16 x i8> %add.i, <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85> 120 br label %if.end 121 122if.end: ; preds = %if.else, %if.then 123 %ret2.0 = phi <16 x i8> [ %mul.i13, %if.then ], [ %mul.i, %if.else ] 124 %add.i12 = add <16 x i8> %add.i, %ret2.0 125 ret <16 x i8> %add.i12 126} 127 128; Two different uses of the sane constant in two different basic blocks, 129; none dominates the other 130define <16 x i8> @test4(<16 x i8> %arg, i32 %path) { 131; PROMOTED-LABEL: test4: 132; In stress mode, constant vector are promoted 133; Since, the constant is the same as the previous function, 134; the same address must be used 135; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 136; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] 137; Destination register is defined by ABI 138; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 139; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] 140; Next BB 141; PROMOTED: mul.16b v0, v0, v[[REGNUM]] 142; Next BB 143; PROMOTED-NEXT: [[LABEL]]: 144; PROMOTED-NEXT: ret 145 146 147; REGULAR-LABEL: test4: 148; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE 149; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] 150; Destination register is defined by ABI 151; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 152; REGULAR-NEXT: cbz w0, [[LABEL:LBB.*]] 153; Next BB 154; Redundant expression 155; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3]]@PAGE 156; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] 157; Destination register is defined by ABI 158; REGULAR-NEXT: mul.16b v0, v0, v[[REGNUM]] 159; Next BB 160; REGULAR-NEXT: [[LABEL]]: 161; REGULAR-NEXT: ret 162entry: 163 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 164 %tobool = icmp eq i32 %path, 0 165 br i1 %tobool, label %if.end, label %if.then 166 167if.then: ; preds = %entry 168 %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 169 br label %if.end 170 171if.end: ; preds = %entry, %if.then 172 %ret.0 = phi <16 x i8> [ %mul.i, %if.then ], [ %add.i, %entry ] 173 ret <16 x i8> %ret.0 174} 175 176; Two different uses of the sane constant in two different basic blocks, 177; one is in a phi. 178define <16 x i8> @test5(<16 x i8> %arg, i32 %path) { 179; PROMOTED-LABEL: test5: 180; In stress mode, constant vector are promoted 181; Since, the constant is the same as the previous function, 182; the same address must be used 183; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 184; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] 185; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] 186; Next BB 187; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 188; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]] 189; Next BB 190; PROMOTED-NEXT: [[LABEL]]: 191; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]] 192; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] 193; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] 194; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] 195; PROMOTED-NEXT: ret 196 197; REGULAR-LABEL: test5: 198; REGULAR: cbz w0, [[LABELelse:LBB.*]] 199; Next BB 200; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 201; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 202; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 203; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]] 204; REGULAR-NEXT: b [[LABELend:LBB.*]] 205; Next BB 206; REGULAR-NEXT: [[LABELelse]] 207; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 208; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 209; Next BB 210; REGULAR-NEXT: [[LABELend]]: 211; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]] 212; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] 213; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] 214; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] 215; REGULAR-NEXT: ret 216entry: 217 %tobool = icmp eq i32 %path, 0 218 br i1 %tobool, label %if.end, label %if.then 219 220if.then: ; preds = %entry 221 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 222 %mul.i26 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 223 br label %if.end 224 225if.end: ; preds = %entry, %if.then 226 %ret.0 = phi <16 x i8> [ %mul.i26, %if.then ], [ <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, %entry ] 227 %mul.i25 = mul <16 x i8> %ret.0, %ret.0 228 %mul.i24 = mul <16 x i8> %mul.i25, %mul.i25 229 %mul.i23 = mul <16 x i8> %mul.i24, %mul.i24 230 %mul.i = mul <16 x i8> %mul.i23, %mul.i23 231 ret <16 x i8> %mul.i 232} 233 234define void @accessBig(i64* %storage) { 235; PROMOTED-LABEL: accessBig: 236; PROMOTED: adrp 237; PROMOTED: ret 238 %addr = bitcast i64* %storage to <1 x i80>* 239 store <1 x i80> <i80 483673642326615442599424>, <1 x i80>* %addr 240 ret void 241} 242 243define void @asmStatement() { 244; PROMOTED-LABEL: asmStatement: 245; PROMOTED-NOT: adrp 246; PROMOTED: ret 247 call void asm sideeffect "bfxil w0, w0, $0, $1", "i,i"(i32 28, i32 4) 248 ret void 249} 250 251