1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
2
3define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
4; CHECK-LABEL: vmin_u8x8:
5; CHECK: uminv.8b        b[[REG:[0-9]+]], v0
6; CHECK: fmov    [[REG2:w[0-9]+]], s[[REG]]
7; CHECK-NOT: and
8; CHECK: cbz     [[REG2]],
9entry:
10  %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
11  %tmp = trunc i32 %vminv.i to i8
12  %tobool = icmp eq i8 %tmp, 0
13  br i1 %tobool, label %return, label %if.then
14
15if.then:
16  %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
17  br label %return
18
19return:
20  %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
21  ret i32 %retval.0
22}
23
24declare i32 @bar(...)
25
26define i32 @vmin_u4x16(<4 x i16> %a) nounwind ssp {
27; CHECK-LABEL: vmin_u4x16:
28; CHECK: uminv.4h        h[[REG:[0-9]+]], v0
29; CHECK: fmov    [[REG2:w[0-9]+]], s[[REG]]
30; CHECK-NOT: and
31; CHECK: cbz     [[REG2]],
32entry:
33  %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
34  %tmp = trunc i32 %vminv.i to i16
35  %tobool = icmp eq i16 %tmp, 0
36  br i1 %tobool, label %return, label %if.then
37
38if.then:
39  %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
40  br label %return
41
42return:
43  %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
44  ret i32 %retval.0
45}
46
47define i32 @vmin_u8x16(<8 x i16> %a) nounwind ssp {
48; CHECK-LABEL: vmin_u8x16:
49; CHECK: uminv.8h        h[[REG:[0-9]+]], v0
50; CHECK: fmov    [[REG2:w[0-9]+]], s[[REG]]
51; CHECK-NOT: and
52; CHECK: cbz     [[REG2]],
53entry:
54  %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
55  %tmp = trunc i32 %vminv.i to i16
56  %tobool = icmp eq i16 %tmp, 0
57  br i1 %tobool, label %return, label %if.then
58
59if.then:
60  %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
61  br label %return
62
63return:
64  %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
65  ret i32 %retval.0
66}
67
68define i32 @vmin_u16x8(<16 x i8> %a) nounwind ssp {
69; CHECK-LABEL: vmin_u16x8:
70; CHECK: uminv.16b        b[[REG:[0-9]+]], v0
71; CHECK: fmov     [[REG2:w[0-9]+]], s[[REG]]
72; CHECK-NOT: and
73; CHECK: cbz     [[REG2]],
74entry:
75  %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
76  %tmp = trunc i32 %vminv.i to i8
77  %tobool = icmp eq i8 %tmp, 0
78  br i1 %tobool, label %return, label %if.then
79
80if.then:
81  %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
82  br label %return
83
84return:
85  %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
86  ret i32 %retval.0
87}
88
89declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
90declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
91declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
92declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
93