1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2; Check that we generate matching compare insn.
3
4; Function Attrs: nounwind
5define i32 @neqi(i32 %argc) #0 {
6entry:
7  %p = alloca i8, align 1
8  %0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512)
9  %conv = zext i1 %0 to i8
10  store volatile i8 %conv, i8* %p, align 1
11  %p.0.p.0. = load volatile i8* %p, align 1
12  %conv1 = zext i8 %p.0.p.0. to i32
13  ret i32 %conv1
14}
15; CHECK:	p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512)
16
17; Function Attrs: nounwind readnone
18declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1
19
20; Function Attrs: nounwind
21define i32 @ngti(i32 %argc) #0 {
22entry:
23  %p = alloca i8, align 1
24  %0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4)
25  %conv = zext i1 %0 to i8
26  store volatile i8 %conv, i8* %p, align 1
27  %p.0.p.0. = load volatile i8* %p, align 1
28  %conv1 = zext i8 %p.0.p.0. to i32
29  ret i32 %conv1
30}
31; CHECK:	p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4)
32
33; Function Attrs: nounwind readnone
34declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1
35
36; Function Attrs: nounwind
37define i32 @ngtui(i32 %argc) #0 {
38entry:
39  %p = alloca i8, align 1
40  %0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4)
41  %conv = zext i1 %0 to i8
42  store volatile i8 %conv, i8* %p, align 1
43  %p.0.p.0. = load volatile i8* %p, align 1
44  %conv1 = zext i8 %p.0.p.0. to i32
45  ret i32 %conv1
46}
47; CHECK: 	p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4)
48
49; Function Attrs: nounwind readnone
50declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1
51