1; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2; Check that we generate new value jump, both registers, with one
3; of the registers as new.
4
5@Reg = common global i8 0, align 1
6define i32 @main() nounwind {
7entry:
8; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
9  %Reg2 = alloca i8, align 1
10  %0 = load i8* %Reg2, align 1
11  %conv0 = zext i8 %0 to i32
12  %1 = load i8* @Reg, align 1
13  %conv1 = zext i8 %1 to i32
14  %tobool = icmp sle i32 %conv0, %conv1
15  br i1 %tobool, label %if.then, label %if.else
16
17if.then:
18  call void @bar(i32 1, i32 2)
19  br label %if.end
20
21if.else:
22  call void @baz(i32 10, i32 20)
23  br label %if.end
24
25if.end:
26  ret i32 0
27}
28
29declare void @bar(i32, i32)
30declare void @baz(i32, i32)
31