1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s
2; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s
3
4define void @loadstore_v16i8_near() nounwind {
5  ; MIPS32-AE: loadstore_v16i8_near:
6
7  %1 = alloca <16 x i8>
8  %2 = load volatile <16 x i8>* %1
9  ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp)
10  store volatile <16 x i8> %2, <16 x i8>* %1
11  ; MIPS32-AE: st.b [[R1]], 0($sp)
12
13  ret void
14  ; MIPS32-AE: .size loadstore_v16i8_near
15}
16
17define void @loadstore_v16i8_just_under_simm10() nounwind {
18  ; MIPS32-AE: loadstore_v16i8_just_under_simm10:
19
20  %1 = alloca <16 x i8>
21  %2 = alloca [496 x i8] ; Push the frame right up to 512 bytes
22
23  %3 = load volatile <16 x i8>* %1
24  ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp)
25  store volatile <16 x i8> %3, <16 x i8>* %1
26  ; MIPS32-AE: st.b [[R1]], 496($sp)
27
28  ret void
29  ; MIPS32-AE: .size loadstore_v16i8_just_under_simm10
30}
31
32define void @loadstore_v16i8_just_over_simm10() nounwind {
33  ; MIPS32-AE: loadstore_v16i8_just_over_simm10:
34
35  %1 = alloca <16 x i8>
36  %2 = alloca [497 x i8] ; Push the frame just over 512 bytes
37
38  %3 = load volatile <16 x i8>* %1
39  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
40  ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
41  store volatile <16 x i8> %3, <16 x i8>* %1
42  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
43  ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
44
45  ret void
46  ; MIPS32-AE: .size loadstore_v16i8_just_over_simm10
47}
48
49define void @loadstore_v16i8_just_under_simm16() nounwind {
50  ; MIPS32-AE: loadstore_v16i8_just_under_simm16:
51
52  %1 = alloca <16 x i8>
53  %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
54
55  %3 = load volatile <16 x i8>* %1
56  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
57  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
58  ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
59  store volatile <16 x i8> %3, <16 x i8>* %1
60  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
61  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
62  ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
63
64  ret void
65  ; MIPS32-AE: .size loadstore_v16i8_just_under_simm16
66}
67
68define void @loadstore_v16i8_just_over_simm16() nounwind {
69  ; MIPS32-AE: loadstore_v16i8_just_over_simm16:
70
71  %1 = alloca <16 x i8>
72  %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
73
74  %3 = load volatile <16 x i8>* %1
75  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
76  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
77  ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
78  store volatile <16 x i8> %3, <16 x i8>* %1
79  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
80  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
81  ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
82
83  ret void
84  ; MIPS32-AE: .size loadstore_v16i8_just_over_simm16
85}
86
87define void @loadstore_v8i16_near() nounwind {
88  ; MIPS32-AE: loadstore_v8i16_near:
89
90  %1 = alloca <8 x i16>
91  %2 = load volatile <8 x i16>* %1
92  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp)
93  store volatile <8 x i16> %2, <8 x i16>* %1
94  ; MIPS32-AE: st.h [[R1]], 0($sp)
95
96  ret void
97  ; MIPS32-AE: .size loadstore_v8i16_near
98}
99
100define void @loadstore_v8i16_unaligned() nounwind {
101  ; MIPS32-AE: loadstore_v8i16_unaligned:
102
103  %1 = alloca [2 x <8 x i16>]
104  %2 = bitcast [2 x <8 x i16>]* %1 to i8*
105  %3 = getelementptr i8* %2, i32 1
106  %4 = bitcast i8* %3 to [2 x <8 x i16>]*
107  %5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0
108
109  %6 = load volatile <8 x i16>* %5
110  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
111  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
112  store volatile <8 x i16> %6, <8 x i16>* %5
113  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
114  ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
115
116  ret void
117  ; MIPS32-AE: .size loadstore_v8i16_unaligned
118}
119
120define void @loadstore_v8i16_just_under_simm10() nounwind {
121  ; MIPS32-AE: loadstore_v8i16_just_under_simm10:
122
123  %1 = alloca <8 x i16>
124  %2 = alloca [1008 x i8] ; Push the frame right up to 1024 bytes
125
126  %3 = load volatile <8 x i16>* %1
127  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
128  store volatile <8 x i16> %3, <8 x i16>* %1
129  ; MIPS32-AE: st.h [[R1]], 1008($sp)
130
131  ret void
132  ; MIPS32-AE: .size loadstore_v8i16_just_under_simm10
133}
134
135define void @loadstore_v8i16_just_over_simm10() nounwind {
136  ; MIPS32-AE: loadstore_v8i16_just_over_simm10:
137
138  %1 = alloca <8 x i16>
139  %2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
140
141  %3 = load volatile <8 x i16>* %1
142  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
143  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
144  store volatile <8 x i16> %3, <8 x i16>* %1
145  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
146  ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
147
148  ret void
149  ; MIPS32-AE: .size loadstore_v8i16_just_over_simm10
150}
151
152define void @loadstore_v8i16_just_under_simm16() nounwind {
153  ; MIPS32-AE: loadstore_v8i16_just_under_simm16:
154
155  %1 = alloca <8 x i16>
156  %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
157
158  %3 = load volatile <8 x i16>* %1
159  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
160  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
161  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
162  store volatile <8 x i16> %3, <8 x i16>* %1
163  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
164  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
165  ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
166
167  ret void
168  ; MIPS32-AE: .size loadstore_v8i16_just_under_simm16
169}
170
171define void @loadstore_v8i16_just_over_simm16() nounwind {
172  ; MIPS32-AE: loadstore_v8i16_just_over_simm16:
173
174  %1 = alloca <8 x i16>
175  %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
176
177  %3 = load volatile <8 x i16>* %1
178  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
179  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
180  ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
181  store volatile <8 x i16> %3, <8 x i16>* %1
182  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
183  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
184  ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
185
186  ret void
187  ; MIPS32-AE: .size loadstore_v8i16_just_over_simm16
188}
189
190define void @loadstore_v4i32_near() nounwind {
191  ; MIPS32-AE: loadstore_v4i32_near:
192
193  %1 = alloca <4 x i32>
194  %2 = load volatile <4 x i32>* %1
195  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp)
196  store volatile <4 x i32> %2, <4 x i32>* %1
197  ; MIPS32-AE: st.w [[R1]], 0($sp)
198
199  ret void
200  ; MIPS32-AE: .size loadstore_v4i32_near
201}
202
203define void @loadstore_v4i32_unaligned() nounwind {
204  ; MIPS32-AE: loadstore_v4i32_unaligned:
205
206  %1 = alloca [2 x <4 x i32>]
207  %2 = bitcast [2 x <4 x i32>]* %1 to i8*
208  %3 = getelementptr i8* %2, i32 1
209  %4 = bitcast i8* %3 to [2 x <4 x i32>]*
210  %5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0
211
212  %6 = load volatile <4 x i32>* %5
213  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
214  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
215  store volatile <4 x i32> %6, <4 x i32>* %5
216  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
217  ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
218
219  ret void
220  ; MIPS32-AE: .size loadstore_v4i32_unaligned
221}
222
223define void @loadstore_v4i32_just_under_simm10() nounwind {
224  ; MIPS32-AE: loadstore_v4i32_just_under_simm10:
225
226  %1 = alloca <4 x i32>
227  %2 = alloca [2032 x i8] ; Push the frame right up to 2048 bytes
228
229  %3 = load volatile <4 x i32>* %1
230  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
231  store volatile <4 x i32> %3, <4 x i32>* %1
232  ; MIPS32-AE: st.w [[R1]], 2032($sp)
233
234  ret void
235  ; MIPS32-AE: .size loadstore_v4i32_just_under_simm10
236}
237
238define void @loadstore_v4i32_just_over_simm10() nounwind {
239  ; MIPS32-AE: loadstore_v4i32_just_over_simm10:
240
241  %1 = alloca <4 x i32>
242  %2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
243
244  %3 = load volatile <4 x i32>* %1
245  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
246  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
247  store volatile <4 x i32> %3, <4 x i32>* %1
248  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
249  ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
250
251  ret void
252  ; MIPS32-AE: .size loadstore_v4i32_just_over_simm10
253}
254
255define void @loadstore_v4i32_just_under_simm16() nounwind {
256  ; MIPS32-AE: loadstore_v4i32_just_under_simm16:
257
258  %1 = alloca <4 x i32>
259  %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
260
261  %3 = load volatile <4 x i32>* %1
262  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
263  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
264  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
265  store volatile <4 x i32> %3, <4 x i32>* %1
266  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
267  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
268  ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
269
270  ret void
271  ; MIPS32-AE: .size loadstore_v4i32_just_under_simm16
272}
273
274define void @loadstore_v4i32_just_over_simm16() nounwind {
275  ; MIPS32-AE: loadstore_v4i32_just_over_simm16:
276
277  %1 = alloca <4 x i32>
278  %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
279
280  %3 = load volatile <4 x i32>* %1
281  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
282  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
283  ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
284  store volatile <4 x i32> %3, <4 x i32>* %1
285  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
286  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
287  ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
288
289  ret void
290  ; MIPS32-AE: .size loadstore_v4i32_just_over_simm16
291}
292
293define void @loadstore_v2i64_near() nounwind {
294  ; MIPS32-AE: loadstore_v2i64_near:
295
296  %1 = alloca <2 x i64>
297  %2 = load volatile <2 x i64>* %1
298  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp)
299  store volatile <2 x i64> %2, <2 x i64>* %1
300  ; MIPS32-AE: st.d [[R1]], 0($sp)
301
302  ret void
303  ; MIPS32-AE: .size loadstore_v2i64_near
304}
305
306define void @loadstore_v2i64_unaligned() nounwind {
307  ; MIPS32-AE: loadstore_v2i64_unaligned:
308
309  %1 = alloca [2 x <2 x i64>]
310  %2 = bitcast [2 x <2 x i64>]* %1 to i8*
311  %3 = getelementptr i8* %2, i32 1
312  %4 = bitcast i8* %3 to [2 x <2 x i64>]*
313  %5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0
314
315  %6 = load volatile <2 x i64>* %5
316  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
317  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
318  store volatile <2 x i64> %6, <2 x i64>* %5
319  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
320  ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
321
322  ret void
323  ; MIPS32-AE: .size loadstore_v2i64_unaligned
324}
325
326define void @loadstore_v2i64_just_under_simm10() nounwind {
327  ; MIPS32-AE: loadstore_v2i64_just_under_simm10:
328
329  %1 = alloca <2 x i64>
330  %2 = alloca [4080 x i8] ; Push the frame right up to 4096 bytes
331
332  %3 = load volatile <2 x i64>* %1
333  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
334  store volatile <2 x i64> %3, <2 x i64>* %1
335  ; MIPS32-AE: st.d [[R1]], 4080($sp)
336
337  ret void
338  ; MIPS32-AE: .size loadstore_v2i64_just_under_simm10
339}
340
341define void @loadstore_v2i64_just_over_simm10() nounwind {
342  ; MIPS32-AE: loadstore_v2i64_just_over_simm10:
343
344  %1 = alloca <2 x i64>
345  %2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
346
347  %3 = load volatile <2 x i64>* %1
348  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
349  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
350  store volatile <2 x i64> %3, <2 x i64>* %1
351  ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
352  ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
353
354  ret void
355  ; MIPS32-AE: .size loadstore_v2i64_just_over_simm10
356}
357
358define void @loadstore_v2i64_just_under_simm16() nounwind {
359  ; MIPS32-AE: loadstore_v2i64_just_under_simm16:
360
361  %1 = alloca <2 x i64>
362  %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
363
364  %3 = load volatile <2 x i64>* %1
365  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
366  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
367  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
368  store volatile <2 x i64> %3, <2 x i64>* %1
369  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
370  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
371  ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
372
373  ret void
374  ; MIPS32-AE: .size loadstore_v2i64_just_under_simm16
375}
376
377define void @loadstore_v2i64_just_over_simm16() nounwind {
378  ; MIPS32-AE: loadstore_v2i64_just_over_simm16:
379
380  %1 = alloca <2 x i64>
381  %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
382
383  %3 = load volatile <2 x i64>* %1
384  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
385  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
386  ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
387  store volatile <2 x i64> %3, <2 x i64>* %1
388  ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
389  ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
390  ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
391
392  ret void
393  ; MIPS32-AE: .size loadstore_v2i64_just_over_simm16
394}
395