1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
3
4target triple = "nvptx-unknown-cuda"
5
6declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
7declare i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)*)
8
9
10; SM20-LABEL: .entry foo
11; SM30-LABEL: .entry foo
12define void @foo(i64 %img, i32 %val, i32 %idx) {
13; SM20: ld.param.u64    %rd[[SURFREG:[0-9]+]], [foo_param_0];
14; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
15; SM30: ld.param.u64    %rd[[SURFREG:[0-9]+]], [foo_param_0];
16; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17  tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
18  ret void
19}
20
21
22@surf0 = internal addrspace(1) global i64 0, align 8
23
24
25
26; SM20-LABEL: .entry bar
27; SM30-LABEL: .entry bar
28define void @bar(i32 %val, i32 %idx) {
29; SM30: mov.u64 %rd[[SURFHANDLE:[0-9]+]], surf0
30  %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
31; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33  tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
34  ret void
35}
36
37
38!nvvm.annotations = !{!1, !2, !3}
39!1 = !{void (i64, i32, i32)* @foo, !"kernel", i32 1}
40!2 = !{void (i32, i32)* @bar, !"kernel", i32 1}
41!3 = !{i64 addrspace(1)* @surf0, !"surface", i32 1}
42
43