1; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; Function Attrs: nounwind readnone
6define zeroext i32 @bs4(i32 zeroext %a) #0 {
7entry:
8  %0 = tail call i32 @llvm.bswap.i32(i32 %a)
9  ret i32 %0
10
11; CHECK-LABEL: @bs4
12; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
13; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
14; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
15; CHECK: mr 3, [[REG1]]
16; CHECK: blr
17}
18
19define i64 @bs8(i64 %x) #0 {
20entry:
21  %0 = tail call i64 @llvm.bswap.i64(i64 %x)
22  ret i64 %0
23
24; CHECK-LABEL: @bs8
25; CHECK-DAG: rldicl [[REG1:[0-9]+]], 3, 16, 0
26; CHECK-DAG: rldicl [[REG2:[0-9]+]], 3, 8, 0
27; CHECK-DAG: rldicl [[REG3:[0-9]+]], 3, 24, 0
28; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
29; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 32, 0
30; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
31; CHECK-DAG: rldicl [[REG5:[0-9]+]], 3, 48, 0
32; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
33; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 56, 0
34; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
35; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
36; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
37; CHECK: mr 3, [[REG2]]
38; CHECK: blr
39}
40
41define i64 @test1(i64 %i0, i64 %i1) #0 {
42entry:
43  %0 = lshr i64 %i1, 8
44  %and = and i64 %0, 5963776000
45  ret i64 %and
46
47; CHECK-LABEL: @test1
48; CHECK-DAG: li [[REG1:[0-9]+]], 11375
49; CHECK-DAG: rldicl [[REG3:[0-9]+]], 4, 56, 0
50; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
51; CHECK: and 3, [[REG3]], [[REG2]]
52; CHECK: blr
53}
54
55define i64 @test2(i64 %i0, i64 %i1) #0 {
56entry:
57  %0 = lshr i64 %i1, 6
58  %and = and i64 %0, 133434808670355456
59  ret i64 %and
60
61; CHECK-LABEL: @test2
62; CHECK-DAG: lis [[REG1:[0-9]+]], 474
63; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 58, 0
64; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648
65; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
66; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
67; CHECK: and 3, [[REG5]], [[REG4]]
68; CHECK: blr
69}
70
71define i64 @test3(i64 %i0, i64 %i1) #0 {
72entry:
73  %0 = shl i64 %i0, 34
74  %and = and i64 %0, 191795733152661504
75  ret i64 %and
76
77; CHECK-LABEL: @test3
78; CHECK-DAG: lis [[REG1:[0-9]+]], 170
79; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 34, 0
80; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861
81; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
82; CHECK: and 3, [[REG4]], [[REG3]]
83; CHECK: blr
84}
85
86define i64 @test4(i64 %i0, i64 %i1) #0 {
87entry:
88  %0 = lshr i64 %i1, 15
89  %and = and i64 %0, 58195968
90  ret i64 %and
91
92; CHECK-LABEL: @test4
93; CHECK: rldicl [[REG1:[0-9]+]], 4, 49, 0
94; CHECK: andis. 3, [[REG1]], 888
95; CHECK: blr
96}
97
98define i64 @test5(i64 %i0, i64 %i1) #0 {
99entry:
100  %0 = shl i64 %i1, 12
101  %and = and i64 %0, 127252959854592
102  ret i64 %and
103
104; CHECK-LABEL: @test5
105; CHECK-DAG: lis [[REG1:[0-9]+]], 3703
106; CHECK-DAG: rldicl [[REG4:[0-9]+]], 4, 12, 0
107; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951
108; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
109; CHECK: and 3, [[REG4]], [[REG3]]
110; CHECK: blr
111}
112
113; Function Attrs: nounwind readnone
114define zeroext i32 @test6(i32 zeroext %x) #0 {
115entry:
116  %and = lshr i32 %x, 16
117  %shr = and i32 %and, 255
118  %and1 = shl i32 %x, 16
119  %shl = and i32 %and1, 16711680
120  %or = or i32 %shr, %shl
121  ret i32 %or
122
123; CHECK-LABEL: @test6
124; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31
125; CHECK: rlwimi [[REG1]], 3, 16, 8, 15
126; CHECK: mr 3, [[REG1]]
127; CHECK: blr
128}
129
130define i64 @test7(i64 %i0, i64 %i1) #0 {
131entry:
132  %0 = lshr i64 %i0, 5
133  %and = and i64 %0, 58195968
134  ret i64 %and
135
136; CHECK-LABEL: @test7
137; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12
138; CHECK: rlwimi [[REG1]], 3, 27, 6, 7
139; CHECK: mr 3, [[REG1]]
140; CHECK: blr
141}
142
143define i64 @test8(i64 %i0, i64 %i1) #0 {
144entry:
145  %0 = lshr i64 %i0, 1
146  %and = and i64 %0, 169172533248
147  ret i64 %and
148
149; CHECK-LABEL: @test8
150; CHECK-DAG: lis [[REG1:[0-9]+]], 4
151; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 63, 0
152; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527
153; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
154; CHECK: and 3, [[REG4]], [[REG3]]
155; CHECK: blr
156}
157
158define i64 @test9(i64 %i0, i64 %i1) #0 {
159entry:
160  %0 = lshr i64 %i1, 14
161  %and = and i64 %0, 18848677888
162  %1 = shl i64 %i1, 51
163  %and3 = and i64 %1, 405323966463344640
164  %or4 = or i64 %and, %and3
165  ret i64 %or4
166
167; CHECK-LABEL: @test9
168; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
169; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 62, 0
170; CHECK-DAG: rldicl [[REG6:[0-9]+]], 4, 50, 0
171; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
172; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
173; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
174; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
175; CHECK: and 3, [[REG6]], [[REG4]]
176; CHECK: blr
177}
178
179define i64 @test10(i64 %i0, i64 %i1) #0 {
180entry:
181  %0 = shl i64 %i0, 37
182  %and = and i64 %0, 15881483390550016
183  %1 = shl i64 %i0, 25
184  %and3 = and i64 %1, 2473599172608
185  %or4 = or i64 %and, %and3
186  ret i64 %or4
187
188; CHECK-LABEL: @test10
189; CHECK-DAG: lis [[REG1:[0-9]+]], 1
190; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 25, 0
191; CHECK-DAG: rldicl [[REG7:[0-9]+]], 3, 37, 0
192; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183
193; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017
194; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
195; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37
196; CHECK-DAG: and [[REG8:[0-9]+]], [[REG6]], [[REG4]]
197; CHECK-DAG: and [[REG9:[0-9]+]], [[REG7]], [[REG5]]
198; CHECK: or 3, [[REG9]], [[REG8]]
199; CHECK: blr
200}
201
202define i64 @test11(i64 %x) #0 {
203entry:
204  %and = and i64 %x, 4294967295
205  %shl = shl i64 %x, 32
206  %or = or i64 %and, %shl
207  ret i64 %or
208
209; CHECK-LABEL: @test11
210; CHECK: rlwinm 3, 3, 0, 1, 0
211; CHECK: blr
212}
213
214define i64 @test12(i64 %x) #0 {
215entry:
216  %and = and i64 %x, 4294905855
217  %shl = shl i64 %x, 32
218  %or = or i64 %and, %shl
219  ret i64 %or
220
221; CHECK-LABEL: @test12
222; CHECK: rlwinm 3, 3, 0, 20, 15
223; CHECK: blr
224}
225
226define i64 @test13(i64 %x) #0 {
227entry:
228  %shl = shl i64 %x, 4
229  %and = and i64 %shl, 240
230  %shr = lshr i64 %x, 28
231  %and1 = and i64 %shr, 15
232  %or = or i64 %and, %and1
233  ret i64 %or
234
235; CHECK-LABEL: @test13
236; CHECK: rlwinm 3, 3, 4, 24, 31
237; CHECK: blr
238}
239
240define i64 @test14(i64 %x) #0 {
241entry:
242  %shl = shl i64 %x, 4
243  %and = and i64 %shl, 240
244  %shr = lshr i64 %x, 28
245  %and1 = and i64 %shr, 15
246  %and2 = and i64 %x, -4294967296
247  %or = or i64 %and1, %and2
248  %or3 = or i64 %or, %and
249  ret i64 %or3
250
251; CHECK-LABEL: @test14
252; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31
253; CHECK: rlwimi [[REG1]], 3, 4, 24, 31
254; CHECK: mr 3, [[REG1]]
255; CHECK: blr
256}
257
258define i64 @test15(i64 %x) #0 {
259entry:
260  %shl = shl i64 %x, 4
261  %and = and i64 %shl, 240
262  %shr = lshr i64 %x, 28
263  %and1 = and i64 %shr, 15
264  %and2 = and i64 %x, -256
265  %or = or i64 %and1, %and2
266  %or3 = or i64 %or, %and
267  ret i64 %or3
268
269; CHECK-LABEL: @test15
270; CHECK: rlwimi 3, 3, 4, 24, 31
271; CHECK: blr
272}
273
274; Function Attrs: nounwind readnone
275declare i32 @llvm.bswap.i32(i32) #0
276declare i64 @llvm.bswap.i64(i64) #0
277
278attributes #0 = { nounwind readnone }
279
280