1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s 2 3; Use a 64-bit value with lo bits that can be represented as an inline constant 4; CHECK-LABEL: {{^}}i64_imm_inline_lo: 5; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5 6; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]] 7; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]: 8define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { 9entry: 10 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 11 ret void 12} 13 14; Use a 64-bit value with hi bits that can be represented as an inline constant 15; CHECK-LABEL: {{^}}i64_imm_inline_hi: 16; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5 17; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]] 18; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]] 19define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { 20entry: 21 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 22 ret void 23} 24 25; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32 26; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} 27; CHECK-NEXT: buffer_store_dword [[REG]] 28define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { 29 store float 0.0, float addrspace(1)* %out 30 ret void 31} 32 33; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32 34; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 35; CHECK-NEXT: buffer_store_dword [[REG]] 36define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) { 37 store float -0.0, float addrspace(1)* %out 38 ret void 39} 40 41; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32 42; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}} 43; CHECK-NEXT: buffer_store_dword [[REG]] 44define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) { 45 store float 0.5, float addrspace(1)* %out 46 ret void 47} 48 49; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32 50; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}} 51; CHECK-NEXT: buffer_store_dword [[REG]] 52define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) { 53 store float -0.5, float addrspace(1)* %out 54 ret void 55} 56 57; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32 58; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} 59; CHECK-NEXT: buffer_store_dword [[REG]] 60define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) { 61 store float 1.0, float addrspace(1)* %out 62 ret void 63} 64 65; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32 66; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} 67; CHECK-NEXT: buffer_store_dword [[REG]] 68define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) { 69 store float -1.0, float addrspace(1)* %out 70 ret void 71} 72 73; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32 74; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}} 75; CHECK-NEXT: buffer_store_dword [[REG]] 76define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) { 77 store float 2.0, float addrspace(1)* %out 78 ret void 79} 80 81; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32 82; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}} 83; CHECK-NEXT: buffer_store_dword [[REG]] 84define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) { 85 store float -2.0, float addrspace(1)* %out 86 ret void 87} 88 89; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32 90; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}} 91; CHECK-NEXT: buffer_store_dword [[REG]] 92define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) { 93 store float 4.0, float addrspace(1)* %out 94 ret void 95} 96 97; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32 98; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}} 99; CHECK-NEXT: buffer_store_dword [[REG]] 100define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) { 101 store float -4.0, float addrspace(1)* %out 102 ret void 103} 104 105; CHECK-LABEL: {{^}}store_literal_imm_f32: 106; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000 107; CHECK-NEXT: buffer_store_dword [[REG]] 108define void @store_literal_imm_f32(float addrspace(1)* %out) { 109 store float 4096.0, float addrspace(1)* %out 110 ret void 111} 112 113; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32 114; CHECK: s_load_dword [[VAL:s[0-9]+]] 115; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}} 116; CHECK-NEXT: buffer_store_dword [[REG]] 117define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { 118 %y = fadd float %x, 0.0 119 store float %y, float addrspace(1)* %out 120 ret void 121} 122 123; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32 124; CHECK: s_load_dword [[VAL:s[0-9]+]] 125; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}} 126; CHECK-NEXT: buffer_store_dword [[REG]] 127define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { 128 %y = fadd float %x, 0.5 129 store float %y, float addrspace(1)* %out 130 ret void 131} 132 133; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32 134; CHECK: s_load_dword [[VAL:s[0-9]+]] 135; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}} 136; CHECK-NEXT: buffer_store_dword [[REG]] 137define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { 138 %y = fadd float %x, -0.5 139 store float %y, float addrspace(1)* %out 140 ret void 141} 142 143; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32 144; CHECK: s_load_dword [[VAL:s[0-9]+]] 145; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}} 146; CHECK-NEXT: buffer_store_dword [[REG]] 147define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { 148 %y = fadd float %x, 1.0 149 store float %y, float addrspace(1)* %out 150 ret void 151} 152 153; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32 154; CHECK: s_load_dword [[VAL:s[0-9]+]] 155; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}} 156; CHECK-NEXT: buffer_store_dword [[REG]] 157define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { 158 %y = fadd float %x, -1.0 159 store float %y, float addrspace(1)* %out 160 ret void 161} 162 163; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32 164; CHECK: s_load_dword [[VAL:s[0-9]+]] 165; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}} 166; CHECK-NEXT: buffer_store_dword [[REG]] 167define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { 168 %y = fadd float %x, 2.0 169 store float %y, float addrspace(1)* %out 170 ret void 171} 172 173; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32 174; CHECK: s_load_dword [[VAL:s[0-9]+]] 175; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}} 176; CHECK-NEXT: buffer_store_dword [[REG]] 177define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { 178 %y = fadd float %x, -2.0 179 store float %y, float addrspace(1)* %out 180 ret void 181} 182 183; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32 184; CHECK: s_load_dword [[VAL:s[0-9]+]] 185; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}} 186; CHECK-NEXT: buffer_store_dword [[REG]] 187define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { 188 %y = fadd float %x, 4.0 189 store float %y, float addrspace(1)* %out 190 ret void 191} 192 193; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32 194; CHECK: s_load_dword [[VAL:s[0-9]+]] 195; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}} 196; CHECK-NEXT: buffer_store_dword [[REG]] 197define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { 198 %y = fadd float %x, -4.0 199 store float %y, float addrspace(1)* %out 200 ret void 201} 202 203; CHECK-LABEL: @commute_add_inline_imm_0.5_f32 204; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 205; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] 206; CHECK-NEXT: buffer_store_dword [[REG]] 207define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 208 %x = load float addrspace(1)* %in 209 %y = fadd float %x, 0.5 210 store float %y, float addrspace(1)* %out 211 ret void 212} 213 214; CHECK-LABEL: @commute_add_literal_f32 215; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 216; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] 217; CHECK-NEXT: buffer_store_dword [[REG]] 218define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 219 %x = load float addrspace(1)* %in 220 %y = fadd float %x, 1024.0 221 store float %y, float addrspace(1)* %out 222 ret void 223} 224 225; CHECK-LABEL: {{^}}add_inline_imm_1_f32 226; CHECK: s_load_dword [[VAL:s[0-9]+]] 227; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}} 228; CHECK-NEXT: buffer_store_dword [[REG]] 229define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) { 230 %y = fadd float %x, 0x36a0000000000000 231 store float %y, float addrspace(1)* %out 232 ret void 233} 234 235; CHECK-LABEL: {{^}}add_inline_imm_2_f32 236; CHECK: s_load_dword [[VAL:s[0-9]+]] 237; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}} 238; CHECK-NEXT: buffer_store_dword [[REG]] 239define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) { 240 %y = fadd float %x, 0x36b0000000000000 241 store float %y, float addrspace(1)* %out 242 ret void 243} 244 245; CHECK-LABEL: {{^}}add_inline_imm_16_f32 246; CHECK: s_load_dword [[VAL:s[0-9]+]] 247; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]] 248; CHECK-NEXT: buffer_store_dword [[REG]] 249define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) { 250 %y = fadd float %x, 0x36e0000000000000 251 store float %y, float addrspace(1)* %out 252 ret void 253} 254 255; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32 256; CHECK: s_load_dword [[VAL:s[0-9]+]] 257; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]] 258; CHECK-NEXT: buffer_store_dword [[REG]] 259define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) { 260 %y = fadd float %x, 0xffffffffe0000000 261 store float %y, float addrspace(1)* %out 262 ret void 263} 264 265; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32 266; CHECK: s_load_dword [[VAL:s[0-9]+]] 267; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]] 268; CHECK-NEXT: buffer_store_dword [[REG]] 269define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) { 270 %y = fadd float %x, 0xffffffffc0000000 271 store float %y, float addrspace(1)* %out 272 ret void 273} 274 275; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32 276; CHECK: s_load_dword [[VAL:s[0-9]+]] 277; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]] 278; CHECK-NEXT: buffer_store_dword [[REG]] 279define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) { 280 %y = fadd float %x, 0xfffffffe00000000 281 store float %y, float addrspace(1)* %out 282 ret void 283} 284 285; CHECK-LABEL: {{^}}add_inline_imm_63_f32 286; CHECK: s_load_dword [[VAL:s[0-9]+]] 287; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]] 288; CHECK-NEXT: buffer_store_dword [[REG]] 289define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) { 290 %y = fadd float %x, 0x36ff800000000000 291 store float %y, float addrspace(1)* %out 292 ret void 293} 294 295; CHECK-LABEL: {{^}}add_inline_imm_64_f32 296; CHECK: s_load_dword [[VAL:s[0-9]+]] 297; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]] 298; CHECK-NEXT: buffer_store_dword [[REG]] 299define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) { 300 %y = fadd float %x, 0x3700000000000000 301 store float %y, float addrspace(1)* %out 302 ret void 303} 304 305; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64 306; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 307; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]] 308; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 309define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { 310 %y = fadd double %x, 0.0 311 store double %y, double addrspace(1)* %out 312 ret void 313} 314 315; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64 316; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 317; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]] 318; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 319define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { 320 %y = fadd double %x, 0.5 321 store double %y, double addrspace(1)* %out 322 ret void 323} 324 325; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64 326; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 327; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]] 328; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 329define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { 330 %y = fadd double %x, -0.5 331 store double %y, double addrspace(1)* %out 332 ret void 333} 334 335; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64 336; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 337; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]] 338; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 339define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { 340 %y = fadd double %x, 1.0 341 store double %y, double addrspace(1)* %out 342 ret void 343} 344 345; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64 346; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 347; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]] 348; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 349define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { 350 %y = fadd double %x, -1.0 351 store double %y, double addrspace(1)* %out 352 ret void 353} 354 355; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64 356; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 357; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]] 358; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 359define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { 360 %y = fadd double %x, 2.0 361 store double %y, double addrspace(1)* %out 362 ret void 363} 364 365; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64 366; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 367; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]] 368; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 369define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { 370 %y = fadd double %x, -2.0 371 store double %y, double addrspace(1)* %out 372 ret void 373} 374 375; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64 376; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 377; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]] 378; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 379define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { 380 %y = fadd double %x, 4.0 381 store double %y, double addrspace(1)* %out 382 ret void 383} 384 385; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64 386; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 387; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]] 388; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 389define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { 390 %y = fadd double %x, -4.0 391 store double %y, double addrspace(1)* %out 392 ret void 393} 394 395 396; CHECK-LABEL: {{^}}add_inline_imm_1_f64 397; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 398; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]] 399; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 400define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { 401 %y = fadd double %x, 0x0000000000000001 402 store double %y, double addrspace(1)* %out 403 ret void 404} 405 406; CHECK-LABEL: {{^}}add_inline_imm_2_f64 407; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 408; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]] 409; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 410define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { 411 %y = fadd double %x, 0x0000000000000002 412 store double %y, double addrspace(1)* %out 413 ret void 414} 415 416; CHECK-LABEL: {{^}}add_inline_imm_16_f64 417; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 418; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]] 419; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 420define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { 421 %y = fadd double %x, 0x0000000000000010 422 store double %y, double addrspace(1)* %out 423 ret void 424} 425 426; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64 427; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 428; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]] 429; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 430define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { 431 %y = fadd double %x, 0xffffffffffffffff 432 store double %y, double addrspace(1)* %out 433 ret void 434} 435 436; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64 437; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 438; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]] 439; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 440define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { 441 %y = fadd double %x, 0xfffffffffffffffe 442 store double %y, double addrspace(1)* %out 443 ret void 444} 445 446; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64 447; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 448; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]] 449; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 450define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { 451 %y = fadd double %x, 0xfffffffffffffff0 452 store double %y, double addrspace(1)* %out 453 ret void 454} 455 456; CHECK-LABEL: {{^}}add_inline_imm_63_f64 457; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 458; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]] 459; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 460define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { 461 %y = fadd double %x, 0x000000000000003F 462 store double %y, double addrspace(1)* %out 463 ret void 464} 465 466; CHECK-LABEL: {{^}}add_inline_imm_64_f64 467; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 468; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]] 469; CHECK-NEXT: buffer_store_dwordx2 [[REG]] 470define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { 471 %y = fadd double %x, 0x0000000000000040 472 store double %y, double addrspace(1)* %out 473 ret void 474} 475 476 477; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64 478; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0 479; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0 480; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 481define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { 482 store double 0.0, double addrspace(1)* %out 483 ret void 484} 485