1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; FIXME: Enable for VI.
5
6declare i32 @llvm.r600.read.tidig.x() nounwind readnone
7declare void @llvm.AMDGPU.barrier.global() nounwind noduplicate
8declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone
9declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
10
11; GCN-LABEL: {{^}}test_div_fmas_f32:
12; GCN-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
13; GCN-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
14; GCN-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
15; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
16; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
17; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
18; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
19; GCN: buffer_store_dword [[RESULT]],
20; GCN: s_endpgm
21define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
22  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
23  store float %result, float addrspace(1)* %out, align 4
24  ret void
25}
26
27; SI-LABEL: {{^}}test_div_fmas_f64:
28; SI: v_div_fmas_f64
29define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
30  %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
31  store double %result, double addrspace(1)* %out, align 8
32  ret void
33}
34
35; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
36; SI: v_cmp_eq_i32_e64 vcc, s{{[0-9]+}}, 0
37; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
38define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
39  %cmp = icmp eq i32 %i, 0
40  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
41  store float %result, float addrspace(1)* %out, align 4
42  ret void
43}
44
45; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
46; SI: s_mov_b64 vcc, 0
47; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
48define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
49  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
50  store float %result, float addrspace(1)* %out, align 4
51  ret void
52}
53
54; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
55; SI: s_mov_b64 vcc, -1
56; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
57define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
58  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
59  store float %result, float addrspace(1)* %out, align 4
60  ret void
61}
62
63; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
64; SI-DAG: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
65; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0
66; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
67; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
68; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
69; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
70
71; SI: v_div_fmas_f32 {{v[0-9]+}}, [[B]], [[A]], [[C]]
72; SI: s_endpgm
73define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
74  %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
75  %gep.a = getelementptr float addrspace(1)* %in, i32 %tid
76  %gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
77  %gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
78  %gep.out = getelementptr float addrspace(1)* %out, i32 2
79
80  %a = load float addrspace(1)* %gep.a
81  %b = load float addrspace(1)* %gep.b
82  %c = load float addrspace(1)* %gep.c
83
84  %cmp0 = icmp eq i32 %tid, 0
85  %cmp1 = icmp ne i32 %d, 0
86  %and = and i1 %cmp0, %cmp1
87
88  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
89  store float %result, float addrspace(1)* %gep.out, align 4
90  ret void
91}
92
93; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
94; SI: v_cmp_eq_i32_e64 [[CMPTID:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
95; SI: s_and_saveexec_b64 [[CMPTID]], [[CMPTID]]
96; SI: s_xor_b64 [[CMPTID]], exec, [[CMPTID]]
97
98; SI: buffer_load_dword [[LOAD:v[0-9]+]]
99; SI: v_cmp_ne_i32_e64 [[CMPLOAD:s\[[0-9]+:[0-9]+\]]], [[LOAD]], 0
100; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, [[CMPLOAD]]
101
102
103; SI: BB6_2:
104; SI: s_or_b64 exec, exec, [[CMPTID]]
105; SI: v_cmp_ne_i32_e32 vcc, 0, v0
106; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
107; SI: buffer_store_dword
108; SI: s_endpgm
109define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
110entry:
111  %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
112  %gep.out = getelementptr float addrspace(1)* %out, i32 2
113  %gep.a = getelementptr float addrspace(1)* %in, i32 %tid
114  %gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
115  %gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
116
117  %a = load float addrspace(1)* %gep.a
118  %b = load float addrspace(1)* %gep.b
119  %c = load float addrspace(1)* %gep.c
120
121  %cmp0 = icmp eq i32 %tid, 0
122  br i1 %cmp0, label %bb, label %exit
123
124bb:
125  %val = load i32 addrspace(1)* %dummy
126  %cmp1 = icmp ne i32 %val, 0
127  br label %exit
128
129exit:
130  %cond = phi i1 [false, %entry], [%cmp1, %bb]
131  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
132  store float %result, float addrspace(1)* %gep.out, align 4
133  ret void
134}
135