1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4; SI-LABEL: {{^}}kill_gs_const:
5; SI-NOT: v_cmpx_le_f32
6; SI: s_mov_b64 exec, 0
7
8define void @kill_gs_const() #0 {
9main_body:
10  %0 = icmp ule i32 0, 3
11  %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
12  call void @llvm.AMDGPU.kill(float %1)
13  %2 = icmp ule i32 3, 0
14  %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
15  call void @llvm.AMDGPU.kill(float %3)
16  ret void
17}
18
19; SI-LABEL: {{^}}kill_vcc_implicit_def:
20; SI-NOT: v_cmp_gt_f32_e32 vcc,
21; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
22; SI: v_cmp_lt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
23; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
24define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
25entry:
26  %tmp0 = fcmp olt float %13, 0.0
27  call void @llvm.AMDGPU.kill(float %14)
28  %tmp1 = select i1 %tmp0, float 1.0, float 0.0
29  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
30  ret void
31}
32
33declare void @llvm.AMDGPU.kill(float)
34declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
35
36attributes #0 = { "ShaderType"="2" }
37attributes #1 = { "ShaderType"="0" }
38
39!0 = !{!"const", null, i32 1}
40