1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 3declare i32 @llvm.r600.read.tidig.x() readnone 4 5; This is broken because the low half of the 64-bit add remains on the 6; SALU, but the upper half does not. The addc expects the carry bit 7; set in vcc, which is undefined since the low scalar half add sets 8; scc instead. 9 10; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_0: 11; SI: v_add_i32 12; SI: v_addc_u32 13define void @imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 %val) { 14 %vec.0 = insertelement <2 x i32> undef, i32 %val, i32 0 15 %vec.1 = insertelement <2 x i32> %vec.0, i32 999999, i32 1 16 %bc = bitcast <2 x i32> %vec.1 to i64 17 %add = add i64 %bc, 399 18 store i64 %add, i64 addrspace(1)* %out, align 8 19 ret void 20} 21 22; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_1: 23; SI: v_add_i32 24; SI: v_addc_u32 25define void @imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64 %val1) { 26 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 27 %vec.1 = insertelement <2 x i32> %vec.0, i32 99999, i32 1 28 %bc = bitcast <2 x i32> %vec.1 to i64 29 %add = add i64 %bc, %val1 30 store i64 %add, i64 addrspace(1)* %out, align 8 31 ret void 32} 33 34; Doesn't use constants 35; FUNC-LABEL @imp_def_vcc_split_i64_add_2 36; SI: v_add_i32 37; SI: v_addc_u32 38define void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { 39 %tid = call i32 @llvm.r600.read.tidig.x() readnone 40 %gep = getelementptr i32 addrspace(1)* %in, i32 %tid 41 %load = load i32 addrspace(1)* %gep 42 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 43 %vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1 44 %bc = bitcast <2 x i32> %vec.1 to i64 45 %add = add i64 %bc, %val1 46 store i64 %add, i64 addrspace(1)* %out, align 8 47 ret void 48} 49