1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 3 4; FUNC-LABEL: {{^}}lshr_i32: 5; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 6; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7define void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 8 %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 9 %a = load i32 addrspace(1)* %in 10 %b = load i32 addrspace(1)* %b_ptr 11 %result = lshr i32 %a, %b 12 store i32 %result, i32 addrspace(1)* %out 13 ret void 14} 15 16; FUNC-LABEL: {{^}}lshr_v2i32: 17; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 18; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 19 20; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 21; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 22define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 23 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 24 %a = load <2 x i32> addrspace(1)* %in 25 %b = load <2 x i32> addrspace(1)* %b_ptr 26 %result = lshr <2 x i32> %a, %b 27 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 28 ret void 29} 30 31; FUNC-LABEL: {{^}}lshr_v4i32: 32; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 33; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 34; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 35; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 36 37; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 38; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 39; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 40; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 41define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 42 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 43 %a = load <4 x i32> addrspace(1)* %in 44 %b = load <4 x i32> addrspace(1)* %b_ptr 45 %result = lshr <4 x i32> %a, %b 46 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 47 ret void 48} 49 50; FUNC-LABEL: {{^}}lshr_i64: 51; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 52 53; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 54; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 55; EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 56; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 57; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 58; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} 59; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} 60; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} 61; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 62; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 63; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 64define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 65 %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 66 %a = load i64 addrspace(1)* %in 67 %b = load i64 addrspace(1)* %b_ptr 68 %result = lshr i64 %a, %b 69 store i64 %result, i64 addrspace(1)* %out 70 ret void 71} 72 73; FUNC-LABEL: {{^}}lshr_v2i64: 74; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 75; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 76 77; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 78; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 79; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] 80; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] 81; EG-DAG: LSHL {{.*}}, 1 82; EG-DAG: LSHL {{.*}}, 1 83; EG-DAG: LSHR {{.*}}, [[SHA]] 84; EG-DAG: LSHR {{.*}}, [[SHB]] 85; EG-DAG: LSHR {{.*}}, [[SHA]] 86; EG-DAG: LSHR {{.*}}, [[SHB]] 87; EG-DAG: OR_INT 88; EG-DAG: OR_INT 89; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 90; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 91; EG-DAG: LSHR 92; EG-DAG: LSHR 93; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 94; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 95; EG-DAG: CNDE_INT {{.*}}, 0.0 96; EG-DAG: CNDE_INT {{.*}}, 0.0 97; EG-DAG: CNDE_INT 98; EG-DAG: CNDE_INT 99define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 100 %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 101 %a = load <2 x i64> addrspace(1)* %in 102 %b = load <2 x i64> addrspace(1)* %b_ptr 103 %result = lshr <2 x i64> %a, %b 104 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 105 ret void 106} 107 108; FUNC-LABEL: {{^}}lshr_v4i64: 109; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 110; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 111; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 112; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 113 114; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 115; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 116; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 117; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 118; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] 119; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] 120; EG-DAG: LSHL {{\*? *}}[[COMPSHC]] 121; EG-DAG: LSHL {{\*? *}}[[COMPSHD]] 122; EG-DAG: LSHL {{.*}}, 1 123; EG-DAG: LSHL {{.*}}, 1 124; EG-DAG: LSHL {{.*}}, 1 125; EG-DAG: LSHL {{.*}}, 1 126; EG-DAG: LSHR {{.*}}, [[SHA]] 127; EG-DAG: LSHR {{.*}}, [[SHB]] 128; EG-DAG: LSHR {{.*}}, [[SHC]] 129; EG-DAG: LSHR {{.*}}, [[SHD]] 130; EG-DAG: LSHR {{.*}}, [[SHA]] 131; EG-DAG: LSHR {{.*}}, [[SHB]] 132; EG-DAG: LSHR {{.*}}, [[SHC]] 133; EG-DAG: LSHR {{.*}}, [[SHD]] 134; EG-DAG: OR_INT 135; EG-DAG: OR_INT 136; EG-DAG: OR_INT 137; EG-DAG: OR_INT 138; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 139; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 140; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 141; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 142; EG-DAG: LSHR 143; EG-DAG: LSHR 144; EG-DAG: LSHR 145; EG-DAG: LSHR 146; EG-DAG: LSHR 147; EG-DAG: LSHR 148; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 149; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 150; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 151; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 152; EG-DAG: CNDE_INT {{.*}}, 0.0 153; EG-DAG: CNDE_INT {{.*}}, 0.0 154; EG-DAG: CNDE_INT {{.*}}, 0.0 155; EG-DAG: CNDE_INT {{.*}}, 0.0 156; EG-DAG: CNDE_INT 157; EG-DAG: CNDE_INT 158; EG-DAG: CNDE_INT 159; EG-DAG: CNDE_INT 160define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 161 %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 162 %a = load <4 x i64> addrspace(1)* %in 163 %b = load <4 x i64> addrspace(1)* %b_ptr 164 %result = lshr <4 x i64> %a, %b 165 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 166 ret void 167} 168